WEDPF2M64-XBX3 HI-RELIABILITY PRODUCT 2Mx64 3.3V Simultaneous Operation Multi-Chip Package *Preliminary FEATURES n Access Times of 70, 100, 120, 150ns n Unlock Bypass Program command Reduces overall programming time when issuing multiple program command sequences n Packaging 119 ball stacked TSOP BGA n 1,000,000 Erase/Program Cycles n Ready/Busy output (RY/BY) Hardware method for detecting program or erase cycle completion n Sector Architecture 252 32K word sectors and 32 4K word sectors n Hardware reset pin (RESET) Hardware method of resetting the internal state machine to the read mode Any combination of sectors can be concurrently erased. Also supports full chip erase n Organized as 2Mx64 n WP/ACC input pin Write protect (WP) function allows protection of two outermost boot sectors, regardless of sector protect status n Commercial, Industrial and Military Temperature Ranges n 3.3 Volt for Read and Write Operations Acceleration (ACC) function accelerates program timing n Simultaneous Read/Write Operation Data can be continuously read from one bank while executing erase/program functions in other banks n Sector Protection Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector n Embedded Erase and Program Algorithms n Erase Suspend/Resume Supports reading data from or programing data to a sector not being erased Temporary Sector Unprotect allows changing data in protected sectors in-system n Data Polling and Toggle Bits Provides a software method of detecting the status of program or erase cycles Note:For programming information refer to Flash Programming WEDPF2M64-XXX3 Application Note. * Preliminary datasheet. This datasheet describes a product that is not fully qualified or characterized and is subject to change without notice. Sept. 2001 Rev. 3 1 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WEDPF2M64-XBX3 FIG 1: PIN CONFIGURATION FOR WEDPF2M64-XBX3 PIN DESCRIPTION TOP VIEW 1 H A14 2 WE3 3 DQ58 4 5 DQ59 DQ60 6 DQ54 7 8 DQ55 DQ36 9 10 11 12 13 14 15 DQ45 DQ46 DQ28 DQ22 DQ31 A16 Chip Selects WE2 DQ51 DQ52 DQ62 DQ63 DQ44 DQ37 DQ38 DQ20 DQ29 DQ23 DQ15 DQ7 F A10 A13 WE4 DQ53 VSS VSS VSS VSS VSS DQ39 DQ21 DQ30 DQ14 DQ6 E A19 A20 A8 A9 DQ61 VSS VSS VSS VSS VSS DQ47 DQ12 DQ5 DQ13 DQ4 D A21/NC C A18 A17 A7 A6 B A5 A4 A3 DQ50 A2 A1 DQ57 A VCC VCC VCC VCC VCC DQ9 DQ2 DQ10 DQ3 DQ11 VCC VCC VCC VCC VCC DQ25 DQ16 DQ0 DQ8 DQ1 DQ56 DQ43 DQ42 DQ41 DQ33 DQ27 DQ26 DQ17 CS3 CS1 OE DQ48 DQ34 DQ40 DQ32 DQ18 DQ24 CS4 CS2 A DQ19 Write Enables Output Enable A15 DQ35 WE1-4 OE A11 DQ49 Address Inputs NC A12 RY/BY WP/AC A0-20 CS 1-4 G RESET WE1 I/O 0-63 Data Inputs/Outputs RESET Reset/Powerdown VCC VSS Power Supply Ground BLOCK DIAGRAM wedpf2m64-xbx3pc.eps White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com 2 WEDPF2M64-XBX3 ABSOLUTE MAXIMUM RATINGS Parameter CAPACITANCE (TA = +25C) Unit Parameter Symbol Conditions Max Unit Operating Temperature -55 to +125 C Supply Voltage Range (VCC) -0.5 to +4.0 V WE1-4 capacitance C WE VIN = 0 V, f = 1.0 MHz 8 pF -0.5 to Vcc +0.5 V CS1-4 capacitance C CS VIN = 0 V, f = 1.0 MHz 10 pF -65 to +150 C Data I/O capacitance C I/O V I/O = 0 V, f = 1.0 MHz 12 pF Address input capacitance C AD V IN = 0 V, f = 1.0 MHz 25 pF RESET capacitance C RS V IN = 0 V, f = 1.0 MHz 20 pF RY/BY capacitance C RB V IN = 0 V, f = 1.0 MHz 20 pF WP/AC capacitance C WA V IN = 0 V, f = 1.0 MHz 30 pF Signal Voltage Range Storage Temperature Range Endurance (write/erase cycles) 1,000,000 min. cycles NOTES: 1. Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Max Supply Voltage V CC 3.0 3.6 Input High Voltage V IH Input Low Voltage V IL -0.5 +0.8 Operating Temp. (Mil.) TA -55 +125 C Operating Temp. (Ind.) TA -40 +85 C 0.7 x Vcc V CC + 0.3 This parameter is guaranteed by design but not tested. Unit DATA RETENTION V V Parameter V Test Conditions Min Unit Minimum Pattern Data 150C 10 Years Retention Time 125C 20 Years DC CHARACTERISTICS - CMOS COMPATIBLE (VCC = 3.3V, VSS = 0V, TA = -55C to +125C) Parameter Max Unit I LI V CC = 3.6, V IN = GND or VCC 10 A I LOx32 V CC = 3.6, V IN = GND or VCC 10 A I CC1 CS = VIL, OE = V IH, f = 5MHz 65 mA VCC Active Current for Program or Erase (2) I CC2 CS = VIL, OE = VIH 120 mA V CC Standby Current I CC3 V CC = 3.6, CS = VIH, f = 5MHz 20 mA V CC Reset Current (2) I CC4 RESET = V SS 0.3V 1 20 mA Automatic Sleep Mode (2,4) I CC5 V IH = V CC 0.3 V; V IL = V SS 0.3 V 1 20 mA V CC Active Read-While-Program Current (1,2) I CC6 V CC Active Program-While-Erase Current (1,2) I CC7 VCC Active Program-While-Erase-Suspended Current (2,5) I CC8 A CC Accelerated Program Current I ACC Output Low Voltage V OL I OL = 5.8 mA, V CC = 3.0 Output High Voltage V OH1 I OH = -2.0 mA, V CC = 3.0 Low V CC Lock-Out Voltage (4) V LKO Input Leakage Current Output Leakage Current VCC Active Current for Read (1) Symbol Conditions Min Typ CE = V IL, OE = V IH Word 85 180 mA CE = V IL, OE = V IH Word 85 180 mA CE = V IL, OE = V IH 70 140 mA ACC Pin VCC Pin 20 60 40 120 mA 0.45 V 2.5 V CE = V IL, OE = V IH 0.85 2.3 X V CC V NOTES: 1.The I CC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The frequency component typically is less than 8 mA/MHz, with OE at V IH . 2.I CC active while Embedded Algorithm (program or erase) is in progress. 3.DC test conditions: V IL = 0.3V, V IH = V CC - 0.3V 4.Guaranteed by design, but not tested. 3 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WEDPF2M64-XBX3 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS,CS CONTROLLED (VCC = 3.3V, VSS = 0V, TA = -55C to +125C) Parameter Symbol -70 Min -100 -120 -150 Max Min Max Min Max Min Unit Max Write Cycle Time t AVAV t WC 70 100 120 150 ns Write Enable Setup Time t WLEL t WS 0 0 0 0 ns Chip Select Pulse Width t ELEH t CP 35 45 50 50 ns Address Setup Time tAVEL t AS 0 0 0 0 ns Data Setup Time t DVEH t DS 45 45 50 50 ns Data Hold Time tEHDX t DH 0 0 0 0 ns Address Hold Time tELAX t AH 45 45 50 50 ns Chip Select Pulse Width High t EHEL t CPH 30 30 30 30 ns Duration of Byte Programming Operation (1) t WHWH1 300 300 300 300 s Sector Erase Time t WHWH2 15 15 15 15 sec Read Recovery Time (2) tGHEL 50 sec 0 Chip Programming Time 0 50 0 50 0 50 s 1. Typical value for tWHWH1 is 9s. 2. Guaranteed by design, but not tested. AC TEST CONDITIONS FIG 2: AC TEST CIRCUIT Parameter Typ VIL = 0, VIH = 2.5 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V NOTES: V Z is programmable from -2V to +7V. I OL & I OH programmable from 0 to 16mA. Tester Impedance Z 0 = 75W. V Z is typically the midpoint of V OH and V OL . I OL & I OH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com 4 Unit Input Pulse Levels WEDPF2M64-XBX3 AC CHARACTERISTICS WRITE/ERASE/PROGRAM OPERATIONS - WE CONTROLLED (VCC = 3.3V, TA = -55C to +125C) Parameter Symbol -70 Min Write Cycle Time tAVAV tWC 70 Chip Select Setup Time tELWL tCS 0 Write Enable Pulse Width tWLWH tWP 35 Address Setup Time tAVWL tAS 0 Data Setup Time tDVWH tDS 45 Data Hold Time tWHDX tDH 0 Address Hold Time tWLAX tAH 45 tWHWL tWPH 30 Write Enable Pulse Width High Duration of Byte Programming Operation (1) tWHWH1 Sector Erase tWHWH2 Read Recovery Time before Write (3) tGHWL VCC Setup Time -100 Max Min Output Enable Hold Time (2) tOEH Address Setup Time to OE low during toggle bit polling tASO Unit Max 100 120 150 ns 0 0 0 ns 50 50 65 ns 0 0 0 ns 50 50 65 ns 0 0 0 ns 50 50 65 ns 35 30 300 15 15 15 0 0 0 s 50 50 50 s 50 0 Min 30 Chip Programming Time tOES -150 Max 300 50 Output Enable Setup Time Min 300 0 tVCS -120 Max 50 50 ns 300 s 15 sec 50 sec 0 0 0 ns 10 10 10 10 ns 15 15 15 15 ns ns Address Hold Time From CS or OE high during toggle 0 tAHT Output Enable High during toggle bit polling tOEPH 20 Latency Between Read and Write Operations tsr/W 0 Write Recovery Time from RY/BY tRB 0 Program/Erase Valis to RY/BY tBUSY 90 0 0 0 20 20 20 ns 0 0 0 ns 0 0 0 ns 90 90 90 ns 1.Typical value for t WHWH1 is 9s. 2.For Toggle and Data Polling. 3.Guaranteed by design, but not tested. AC CHARACTERISTICS READ-ONLY OPERATIONS (VCC = 3.3V, TA = -55C to +125C) Parameter Symbol -70 Min Read Cycle Time tAVAV tRC Address Access Time tAVQV tACC Chip Select Access Time tELQV Output Enable to Output Valid tGLQV -100 Max 70 Min -120 Max 100 Min -150 Max 120 Min Unit Max 150 ns 70 100 120 150 ns tCE 70 100 120 150 ns tOE 40 40 50 55 ns Chip Select High to Output High Z (1) tEHQZ tDF 30 30 30 40 ns Output Enable High to Output High Z (1) tGHQZ tDF 30 30 30 40 ns Output Hold from Addresses, CS or OE Change, tAXQX tOH 0 0 0 tOEH 0 ns Whichever is first Read Output Enable Hold Time (1) 0 0 0 10 10 10 Toggle and Data Polling 10 1. Guaranteed by design, not tested. 5 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WEDPF2M64-XBX3 FIG 3: AC WAVEFORMS FOR READ OPERATIONS tRC Addresses Addresses Stable tACC CS tDF tOE OE WE tCE tOH High Z Outputs Output Valid High Z RESET RY/BY OV fig3/waveforms.eps White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com 6 WEDPF2M64-XBX3 AC CHARACTERISTICS HARDWARE RESET (RESET) Parameter Symbol -100 Min RESET Pin Low (During Embedded Algorithms) to Read Mode (See Note) -120 Max t ready Min 20 -150 Max Min 20 Unit Max 20 s RESET Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) t ready RESET Pulse Width t RP 500 500 500 ns RESET High Time Before Read (See Note) tRH 50 50 50 ns RESET Low to Standby Mode t RPD 20 20 20 s RY/BY Recovery Time t RB 0 0 0 ns 500 500 500 ns Note: Not 100% tested. FIG 4: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS RY/BY CS, OE tRH RESET tRP tReady FIG 5: RESET TIMINGS DURING EMBEDDED ALGORITHMS tReady RY/BY tRB CS, OE RESET tRP newresetchart.eps 7 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com A0H 8 Data tDS tCS WE OE RY/BY tWP White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com tGHWL CS tWC AAAH Addresses NOTES: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the output of the complement of the data written to each chip. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. tDH tWPH tAS PA PD tAH t BUSY tWHWH1 Data Polling D7 PA DOUT t RB tOE tRC tDF FIG 6: WRITE/ERASE/PROGRAM OPERATION, WE CONTROLLED tOH WEDPF2M64-XBX3 WEDPF2M64-XBX3 FIG 7: ACCELERATED PROGRAM TIMING DIAGRAM VHH WP/ACC VIL or VIH VIL or VIH tVHH tVHH wedpf2m64fig18.eps FIG 8: CHIP/SECTOR ERASE OPERATION TIMINGS tAS tWC 2AAh Addresses VA SA VA 555h for chip erase tH tAH CS# OE# tCH tWP WE# tWPH tCS tDS Data 55h tDH In Progress 30h Complete 10 for chip erase tBUSY RY/BY# tRB tVCS Vcc WEDPF2M64FIG8.EPS NOTES: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"). 9 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WEDPF2M64-XBX3 FIG 9: BACK TO BACK READ/WRITE CYCLE TIMINGS tWC Valid PA Addresses Valid PA Valid RA tAH tACC CS CE tWC tWC tRC Valid PA tCPH tCE tCP tOE OE tWP tOEH tGHWL WE tDF tWPH tDS tOH tDH Valid In Valid In Valid Out Valid In Data tSW/W WE Controlled Write Cycle Read Cycle CE CS Controlled Write Cycle wedpf2m64fig20.eps FIG. 10: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS) tRC VA VA VA Addresses tACC tCE CS tCH tOE OE tDF tOEH WE tOH DQ0-DQ6 Complement Complement True Valid Data Status Data Status Data True Valid Data High Z High Z tBUSY RY/BY wedpf2m64fig10.eps NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com 10 WEDPF2M64-XBX3 FIG 11: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS) tAS tAHT VA Addresses tAHT tASO CS tCEPH tASO WE tOEPH OE tDH tOE DQ6/DQ2 Valid Data Valid Status Valid Status (First Read) (Second Read) Valid Status Valid Data (Stops Toggling) RY/BY wedpf2m64fig11.eps NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after comand sequence, last status read cycle, and array data read cycle. FIG 12: DQ2 VS. DQ6 Enter Embedded Erasing WE Erase Enter Erase Erasing Resume Suspend Program Suspend Erase Erase Erase Erase Suspend Erase Suspend Suspend Read Read Program Erase Complete DQ6 wedpf2m64fig12.eps NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE or CS. 11 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com WEDPF2M64-XBX3 FIG 13: ALTERNATE CS CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS PA for Program 555 for Program SA for Sector Erase 2AA for Erase 555 for Chip Erase Data Polling PA Addresses tWC tAS tAH tWH WE tGHEL OE tWHWH1 OR 2 CS tCPH tWS tDS tBUSY tDH In Progress Data tHR RESET A0 for Program 55 for Erase Complete PD for Program 30 for Sector Erase 10 for Chip Erase RB/RY WEDPF2M64FIG13.EPS NOTES: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7 is the complement of the data written to the device. D OUT is the data written to the device. White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com 12 WEDPF2M64-XBX3 PACKAGE: 119 STACKED TSOP BGA TOP VIEW 24.00 (0.944) MAX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H G F 14.00 E (0.551) D MAX C B A 1.27/2 8.89 (0.35) typ 1.27/2 119 x 0.76 17.78 (0.700) typ 0.76 (0.030) typ 7.56 (0.298) MAX ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION WED P F 2M64 B - XXX X B 3 PROGRAMMING VOLTAGE 3 = 3.3V DEVICE GRADE: M = Military Screened I = Industrial C = Commercial -55C to +125C -40C to +85C 0C to +70C PACKAGE TYPE: B = 119 Stacked TSOP BGA ACCESS TIME (ns) IMPROVEMENT MARK B = Boot Block (Bottom Sector) ORGANIZATION, 2M x 64 User configurable as 4M x 32, 8M x 16 or 16M x 8 Flash Plastic WHITE ELECTRONIC DESIGNS CORP. 13 White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com