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FEATURES
10 years minimu m data retention in the
absence o f exter na l po wer
Dat a is aut omatical l y p r ot ected during power
loss
Unlim ited write cycles
Low-pow er CMO S operation
Read and wr it e acces s times of 70 ns
L ithium energ y s ource is elect rically
d iscon nect ed to retain freshness until power is
applied for the first time
Full ±10% VCC operating r ange (DS1265Y)
Optional ±5% VCC oper at ing range
(DS1265AB)
Optional indust r ial temperatur e range of
-40°C to +85°C, des ignated I N D
PIN ASSIGNMENT
PIN DESCRIPTION
A0 - A19 - Address Inputs
DQ0 - DQ7 - Data I n/Dat a Out
CE
- Chip E na ble
WE
- Wr ite E nable
OE
- Output Enable
VCC - Po w er (+5V)
GND - Ground
NC - No Connect
DESCRIPTION
The DS1265 8M Nonvolatile SRAMs are 8,388,608-bit, fully static nonvolatile SRAMs organized as
1,048,576 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control
circuitry whi ch con stan tly monitors VCC for an out-of-t oleranc e c ondition. When such a c ondition occ urs ,
t he lithi u m e ne r g y so u r ce is a utomatica l l y s w it c he d o n a nd w r it e p r o te ct io n i s u nconditio n a ll y ena b l ed t o
prevent data corruption. There is no limit on the number of write cycles which can be executed and no
add it ional support circuitry is requ ired for micro pr ocessor interfacing.
DS1265Y/AB
8M Nonvolatile SRAM
19-5616; Rev 11/10
www.maxim-ic.com
13
1
2
3
4
5
6
7
8
9
10
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14
35
740-mil EXTENDED
A18
A14
A7
A6
A5
A4
A3
A2
A0
A1
VCC
A19
NC
A15
A17
WE
A13
A8
A9
A11
OE
A10
DQ7
CE
36
34
33
32
31
30
29
28
27
26
25
23
24
NC
A16
A12
NC
DQ0
DQ1
15
16
22
21
DQ6
DQ5
17
18
GND
DQ2
DQ3
DQ4
19
20
DS1265Y/AB
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READ MODE
The DS1265 devices execut e a read cyc le w he ne ver
WE
(Write Enable) is inact ive (hig h) and
CE
(Chip
Ena ble ) and
OE
(Output Enable) are active (low). The unique address specified by t he 20 address inputs
(A0 - A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the
e ig ht dat a o ut put dr iver s w it h in t ACC (Access T ime) aft er the la st address input sig na l is st able, pro viding
that
CE
and
OE
(Output Enable) access times are also satisfied. If
OE
and
CE
access times are not
sat is fied, t hen dat a acce ss must be measured fr o m the lat er -occurring signa l (
CE
or
OE
) and t he li mitin g
paramet er is either tCO for
CE
or tOE for
OE
r athe r than tACC.
WRITE MODE
The DS1265 devices execute a wr ite cycle whenever
WE
and
CE
signals are act ive (low) after address
input s are stab le. T he lat er -o ccurring falling edge of
CE
or
WE
w ill determine the start of the write c ycle .
The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must be kept
valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time (tWR)
before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during writ e
cyc les to avoid bus content io n. However, if the out put drivers are enabled (
CE
and
OE
ac tive) t hen
WE
will disab le the outp uts in tODW from it s fa lling edg e.
DATA RETENTION MODE
The DS1265AB provides full functional capabilit y for VCC greater than 4.75 vo lts and write protects by
4.5 volts. The DS1265Y provides full functional capability for VCC greater than 4.5 volts and write
prot ect s by 4. 25 vo lt s. Dat a is maint ained in the abse nce of VCC w itho u t a ny a d d ition a l s u p p or t circ uitry .
The nonvolatile static RAMs constantly mo nitor VCC. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become don’t care, and all outputs become high-
impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts,
the power switching circuit connects external VCC to RAM and disconnects the lithium energy source.
No rma l RAM oper at io n can re su me after VCC exceeds 4.75 vo lt s fo r the DS1265AB and 4. 5 volts fo r t he
DS1265Y.
FRESH NESS SEAL
Each DS1265 device is shipped fro m Dallas Semico nductor wit h it s lit hium energy source disco nnected,
guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium
energy so ur ce is ena bled for batt er y backup o per at io n.
DS1265Y/AB
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ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative to Ground -0.3V to +6. 0V
Operating T emperat ur e Range
Commercial: 0°C to +70°C
Industrial: -40° C to +85° C
Stor ag e T emperat ur e -40° C to +85°C
Lead Temperature ( soldering, 10s) +260°C
Note: EDIP i s wa ve or ha nd soldered o nly.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA: See Not e 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
DS1265AB Power S upply Voltage VCC 4.75 5.0 5.25 V
DS1265Y Power Supply Voltage VCC 4.5 5.0 5.5 V
Logic 1 Input Voltage VIH 2.2 VCC V
Logic 0 Input Voltage VIL 0 +0.8 V
DC ELECTRICAL C HAR AC TE R IS TIC S (VCC=5V ±5% for DS1265AB)
(TA: See Note 10) (VCC=5V ±10% for DS1265Y)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Cu r r ent IIL -2.0 +2.0 µA
I/O Leakage Cu r r ent IIO -2.0 +2.0 µA
Output Current @ 2.4V IOH -1.0 mA
Output Current @ 0.4V IOL 2.0 mA
St andby Curr ent
CE
=2.2V ICCS1 1.0 1.5 mA
St andby Curr ent
CE
=VCC-0.5V ICCS2 100 200 µA
Operating Cur r ent ICCO1 85 mA
Writ e Pr otection Voltage (DS1265AB) VTP 4.50 4.62 4.75 V
Writ e Pr otection Voltage (DS1265Y) VTP 4.25 4.37 4.5 V
CAPACITANCE (TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance CIN 10 20 pF
Output Capac itance CI/O 10 20 pF
DS1265Y/AB
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AC ELECTRICAL C HAR AC TE R IS TIC S (VCC=5V ±5% for DS1265AB)
(TA: See Note 10) (VCC=5V ±10% for DS1265Y)
PARAMETER SYMBOL DS1265AB-70
DS1265Y-70 UNITS NOTES
MIN MAX
Re a d Cycle Time tRC 70 ns
Access Time tACC 70 ns
OE
to O utput Va lid tOE 35 ns
CE
to O utput Va lid tCO 70 ns
OE
or
CE
to O utput Ac tive tCOE 5 ns 5
Output High Z from Deselection tOD 25 ns 5
Output Hold fro m Address Change tOH 5 ns
Write Cycle Time tWC 70 ns
Write Pulse Width tWP 55 ns 3
A ddress Setup Time tAW 0 ns
Write Reco ver y Ti me tWR1
tWR2
5
15
ns
ns
12
13
Output High Z from
WE
tODW 25 ns 5
Output Active from
WE
tOEW 5 ns 5
Data Setu p Time tDS 30 ns 4
Da ta Hold Time tDH1
tDH2
0
10 ns
ns 12
13
TIMING DIAGRAM: READ CYCLE
SEE NOTE 1
DS1265Y/AB
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TIMING DIAGRAM: WRITE CYCLE 1
TIMING DIAGRAM: WRITE CYCLE 2
SEE NOTES 2, 3, 4, 6, 7, 8 AND 13
DS1265Y/AB
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POWER-DOWN/POWER-UP CONDITION
SEE NOTE 11
POWER-DOWN/POWER-UP TIMING (TA: See Note 10)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
VCC Fail Detect to
CE
and
WE
Inactive tPD 1.5 µs 11
VCC sl ew f rom VTP t o 0V tF 150 µs
VCC slew from 0 V to VTP tR 150 µs
VCC Valid to
CE
and
WE
Inactive tPU 2 ms
VCC Valid to E nd of Write Pr otectio n tREC 125 ms
(TA= +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Expect ed Data Retent ion T ime tDR 10 years 9
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mo de.
NOTES:
1.
WE
is high for a Read Cycle.
2.
OE
= VIH o r V IL. If
OE
= VIH d uring write cyc le, the outpu t buff ers remain in a h ig h-imped ance state.
3. tWP is specified as the logical AND of
CE
or
WE
. tWP is measur ed fr o m t he lat t er o f
CE
or
WE
going
low to the earlier of
CE
or
WE
going hig h.
4. tDS is measur ed from the ear lier o f
CE
or
WE
going high.
5. T hese para met er s ar e sampled with a 5 pF load an d ar e not 100 % tested .
6. I f the
CE
lo w tr ans it ion o ccurs simultaneo usly w it h o r lat ter than t he
WE
low t ransit io n, t he output
buff e rs rema in in a high-impedance stat e during this period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
bu ffe r s r e ma in in h ig h-impeda nce st ate during this period.
DS1265Y/AB
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8. If
WE
is low or th e
WE
lo w t ra ns ition o c c ur s p rio r t o o r s imu lta n eou s l y w ith t h e
CE
lo w t ra ns ition,
the output bu f f e rs remain in a high-impedance state during this period.
9. Each DS1265 has a bu ilt -in sw it c h that d isco nnect s the lithiu m source u nt il the user fir st app lies VCC.
The expect ed tDR is de fined as accu mu lat ive t ime in t he a bse nce of VCC starting fro m the t ime power
is first applied by the user. This parameter is assured by component selection, process control, and
design. It is not measured directly during production test ing.
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
co mmer cia l pr od uct s, this r ang e is 0°C t o 70°C. For indust ria l pro ducts (IND), this range is -40°C t o
+85°C.
11. I n a po wer-dow n conditio n the volt age on an y pin may no t exc ee d the volt age on VCC.
12. tWR1 and tDH1 are mea sur ed fro m
WE
go ing h ig h.
13. tWR2 and tDH2 are mea sur ed from
CE
go ing h ig h.
14. DS1265 modules are recognized by Underwriters Laboratories (UL) under file E99151.
DC TEST CONDITIONS AC TEST CONDITIONS
Output s Open Output Load: 100 pF + 1TTL Gate
Cycle = 200ns for operating curr ent Input Pulse Le vels: 0V to 3.0V
All voltages ar e r eferenced to ground Timing Measur ement Referen ce Le vels
Input: 1.5V
Output : 1. 5V
Input puls e R ise and Fall Times: 5 ns
ORDERING INFORMATION
PART TEMP RANGE
SUPPLY
TOLERANCE
PIN-PACKAGE
SPEED GRADE
(ns)
DS1265AB-70+
0°C to +70°C
5V
±
5%
36 740 EDIP
70
DS1265AB-70IND+
-40°C to +85°C
5V
±
5%
36 740 EDIP
70
DS1265Y-70+
0°C to +70°C
5V ± 10%
36 740 EDIP
70
DS1265Y-70IND+
-40°C to +85°C
5V ± 10%
36 740 EDIP
70
+Denotes a lead(Pb)-free/RoHS-compliant package.
PACKAGE INFORMATION
For the latest package outline i nformation and land pa tterns, go t o www.maxim-ic.com/package . Note t hat a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix
character, b ut the dr aw ing pertains to the p ackag e regard less of RoHS s tatu s .
s
PACKAGE TYPE PACK AG E CODE OUTLINE NO. LAND PATTERN NO.
36 EDIP MDT36+1 —
21-0245
DS1265Y/AB
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REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
11/10
Updated the storag e information, soldering temperatu r e, and lead
t emperat ur e info rmation in t he Absolute Maximum Ratings section;
r emove d the -100 MIN/MA X inform ation from the AC Electrical
Characteristics table; updated the Ordering Inf ormation table
(removed -100 p arts and leaded -70 p art s) ; replaced the package
outli ne drawing with the Package Inf ormation table
1, 3, 4, 7