wer Lt - CMOS Logic ICs - CD4000B Series Features The Harris High-Reliability CD4000B Series of high-voltage CMOS integrated circuits consists of a b-oad range of SSI, MSI-1, and MSI-2 (LSI) functions from si nple gates to com- plex counters, registers, and arithmetic circuits. Specific design features for CMOS devices and the performance advantages of CMOS technology - low power consumption, high noise immunity, high speed, high fanout TTL and DTL logic compatibility, excellent temperature stability, and fully protected inputs and outputs - provide the logic system designer with a capability to achieve outstanding perfor- mance, high reliability and simplified circuitry in a wide vari- ety of equipment designs. * 100% Tested for Quiescent Current at 20V * Maximum input Current (Leakage of 1A at 18V Over Full Package-Temperature Range; 100nA at 18V at +25C Standardized Symmetrical Output Characteristics 5V, 10V, and 15V Parametric Ratings * Noise Margin (Over Full Package-Temperature Range) - WatVpp = 5V - 2Vat Vopb = 10V - 2.5V at Vop = 15V * Meets all requirements of JEDEC Standard No. 138, Standard Specifications for Description of B Series CMOS Devices Buffered vs Unbuffered Gates The new industry standard establishes a suffix UB for CMOS products that meet all B-Series specifications except that the logical outputs of the devices are not buffered and the Vi. and Vi, specifications are 20% and 80% of Vpp, respectively. See Application Note AN6558, Understanding Buffered and Unbuffered CMOS Characteristics. See Sec- tion 8, How to Use AnswerFAX, in this selection guide. The suffix B defines high voltage buffered output devices in which the output on impedance is independent of any and all valid input logic conditions, both preceding and present. Both buffered B and unbuffered UB versions of the popu- lar NOR and NAND gates are supplied to make available to designers the advantages of both. The following table briefly compares the features of the two versions. BUFFERED UNBUFFERED CHARACTERISTIC VERSION B | VERSION UB Propagation Delay (Speed) Moderate Fast Noise Immunity/Margin Excellent Good Output Impedance and Constant Variable Output Transition Time AC Gain High Low Output Oscillation for Yes No Slow Inputs Input Capacitance Low High Compliance to MIL-STD-883 Harris CD4000 Series parts are in full compliance with Para- graph 1.2.1 of MIL-STD-883. Product is provided to meet the requirements of Class B. SMD or DESC drawing parts are in full compliance with Paragraph 1.2.1 of MIL-STD-883 and meet the SMD or DESC drawings. Suffix 3A meets Class B requirements. Electrical tests are performed to parameters described in the Electrical Specifi- cations. Harris also provides CD4000 Series parts that meet the requirements of MIL-STD-883, Paragraph 1.2.2. This family of parts has the following designation. Suffix 3 meets most of the requirements of a Class B part as described in details presented in the Lot Screening and Product Flow tables. JAN M38535 CMOS ICs The Harris High-Reliability product line also provides devices that are manufactured and tested in accordance with the MIL-I-38535 (detailed and general) specification, which includes methods and procedures of the Military Standard MIL-STD-883. SCREENING LEVELS FOR STANDARD HARRIS HIGH-RELIABILITY CD4000B-SERIES INTEGRATED CIRCUITS SCREENING PACKAGE LEVELS APPLICATION] DESCRIPTION [| OPTIONS 3A| Class B (Full | Mil. and Ind. For devices intend- F Compliance) |For example, [ed for use where in Airbome maintenance and 3 } Class B, Electronics Teplacement can D,K Modified be performed but are difficult and expensive. File Number 7012 6-23CMOS Logic ICs - CD4000B Series Product Ordering Information HOW TO ORDER HARRIS CD4000B SERIES MIL-I-38510 JAN-QUALIFIED PRODUCT J | 0 T XX X X X JL A a SPECIFICATION DEVICE CLASS LEAD FINISH QUALIFIED DEVICE NUMBER B=CLASSB A= SOLDER C=GOLD RADIATION IDENTIFIER DEVICE TYPE WITHIN / = NO RADIATION TESTING DETAIL SPECIFICATION PACKAGE OUTLINE CASE LETTER = TERMINALS PACKAGE OUTLINE CONFIGURATION C=14 DIL D-1 1 - E=16 DIL D-2 1 EXAMPLE T 0 1 52 B Cc A a A me SPECIFICATION DEVICE CLASS SOLDER QUALIFIED DEVICE NUMBER LEAD FINISH RADIATION IDENTIFIER DEVICE TYPE WITHIN 14- TERMINAL DIL DETAIL SPECIFICATION (CD40018) Branding: JAN products are single branded with the MIL-I-38510 nomenclature. 6-24CMOS Logic ICs - CD4000B Series Product Ordering Information (continued) HOW TO ORDER SMD AND DESC DRAWING PRODUCT 5962 XXXXX XX X X SMD ID NUMBER DESC AND SMD DEVICE TYPE LEAD FINISH (DOES NOT CHANGE) = DRAWINGNUMBER (PARAGRAPH 1.2.1 OF SMD/DESC DRAWING) A= SOLDER PACKAGE OUTLINE CASE LETTER = TERMINALS OUTLINE CONFIGURATION =14 1 E = 16 D-2 J = 24 D-3 SMD EXAMPLE 5962 90640 01 Cc A i TS iT TS TS SMD ID NUMBER SMD DEVICE TYPE 14- TERMINAL DIL SOLDER DRAWING NUMBER 01 = 4016B LEAD FINISH FROM DRAWING DESC EXAMPLE 77023 01 E A DESC DEVICE TYPE 16 - TERMINAL DIL. SOLDER DRAWING NUMBER 01 = 45208 LEAD FINISH FROM DRAWING Branding: SMD/DESC products are double branded with both the Harris nomenclature and SMD/DESC nomenclature. HOW TO ORDER HARRIS STANDARD CD4000 SERIES /883 SCREENED PRODUCT CD4000B D 3 PART NUMBER PACKAGE DESIGNATOR RELIABILITY SCREENING LEVEL CD4000B D = DUAL-IN-LINE METAL SEAL CERAMIC 3A = CLASS B, MIL-STD-983 K = FLAT PACK 3 = CLASS B, MODIFIED F = DUAL-IN-LINE FRIT SEAL CERAMIC Description of Data Supplied Suffix 3A Harris /883 Full Compliant JAN or Class B Product Processing and Screening Compliance C of C * Processing and Screening Compliance C of C * Group A Attribute Summary Group A Attribute Summary Group B Attribute Summary Group C and D Attribute Summary Available Per Request at Added Cost Groups C and D Attribute Summary when tests are per- formed on product being supplied; or Date of Performance Suffix 3 Harris /883 Non Compliant when tests are covered by another type from the same . processing and Screening Compliance C of C microcircuit group. Group B Attribute Summary * Group A Attribute Summary 6-25CMOS Logic ICs - CD4000B Series Product Number Selection Guide GENERIC STANDARD NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 4000A CD4000A Dual 3-Input NOR Gate Pius Inverter F B 14 4000B CD4000B Dual 3-Input NOR Gate Plus Inverter D 3 14 4000UB CD4000UB Dual 3-Input NOR Gate Plus Inverter D 3 14 4001A CD4001A Quad 2-Input NOR Gate F B 14 D,K 3 4001B CD4001B Quad 2-Input NOR Gate F B 14 F 3A D,K 3 4001UB CD4001UB Quad 2-Input NOR Gate F B 14 D 3 4002A CD4002A Dual 4-input NOR Gate D 3 14 4002B CD4002B Dual 4-Input NOR Gate F B 14 F 3A D,K 3 4002UB CD4002UB Dual 4-Input NOR Gate F 3A 14 D,K 3 4006A CD4006A 18-Stage Static Shift Register D 3 14 4006B CD4006B 18-Stage Static Shift Register F 3A 14 D 4007A CD4007A Dual Complementary Pair Plus Inverter F B 14 D 4007UB C04007UB Dual Complementary Pair Plus Inverter F 3A 14 D 3 4008B CD4008B 4-Bit Full Adder with Parallel Carry-Out F 3A 16 D 3 4009UB CD4009UB Hex Buffer/Converter (Inverting) F 3A 16 D,K 3 4010B CD4010B Hex Buffer/Converter (Non-Inverting) F 3A 16 D,K 4011A CD4011A Quad 2-Input NAND Gate F B 14 D, K 4011B CD4011B Quad 2-Input NAND Gate F B 14 F 3A D, K 3 4011UB CD4011UB Quad 2-Input NAND Gate 3A 14 3 4012A CD4012A Dual 4-Input NAND Gate 14 6-26CMOS Logic ICs - CD4000B Series Product Number Selection Guide (Continued) GENERIC STANDARD NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 4012B CD4012B Dual 4-Input NAND Gate F B 14 F 3A D 4013A CD4013A Dual D Flip-Flop with Set/Reset Capability F 14 4013B CD4013B Dual D Flip-Flop with Set/Reset Capability F 14 F 3A D,K 3 4014A CD4014A 8-Stage Static Shift Register D 3 16 40148 CD4014B 8-Stage Static Shift Register F 3A 16 D 3 4015A CD4015A Dual 4-Stage Static Shift Register D 3 16 4015B CD4015B Dual 4-Stage Static Shift Register F 3A 16 D,K 3 4016A CD4016A Quad Bilateral Switch D 3 14 4016B CD4016B Quad Bilateral Switch F 3A 14 D,K 4017A CD4017A Decade Counter/Divider F B 16 D 4017B CD4017B Decade Counter/Divider F B 16 F 3A D 3 4018A CD4018A Presettable Divide-By N Counter D 16 4018B CD4018B Presettable Divide-By N Counter F B 16 F 3A D,K 4019A CD4019A Quad AND/OR Select Gate F 16 D 4019B CD4019B Quad AND/OR Select Gate F B 16 F 3A D,K 4020A CD4020A 14-Stage Binary Ripple Counter F B 16 D,K 4020B CD4020B 14-Stage Binary Ripple Counter F B 16 3A D 3 4021A CD4021A 8-Stage Static Shift Register D,K 3 16 4021B CD4021B 8-Stage Static Shift Register F B 16 F 3A D,K 3 6-27CMOS Logic ICs - CD4000B Series Product Number Selection Guide (Continued) GENERIC STANDARD | NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 4022A CD4022A Divide-by-8 Counter/Divider D 3 16 4022B CD4022B Divide-by-8 Counter/Divider F 3A 16 D 4023A CD4023A Triple 3-Input NAND Gate F B 14 D,K 4023B CD4023B Triple 3-Input NAND Gate F B 14 F 3A D,K 3 4023UB CD4023UB Triple 3-Input NAND Gate D 3 14 4024A CD4024A 7-Stage Binary Ripple Counter F B 14 D,K 3 4024B CD4024B 7-Stage Binary Ripple Counter F B 14 F 3A D,K 3 4025A CD4025A Triple 3-input NOR Gate F B 14 D 40258 CD4025B Triple 3-Input NOR Gate F B 14 F 3A D 3 4025UB CD4025UB Triple 3-Input NOR Gate D 3 14 4027A CD4027A Dual J-K Flip-Flop with Set/Reset Capability F B 16 D,K 3 4027B CD4027B Dual J-K Flip-Flop with Set/Reset Capability F B 16 F 3A D,K 3 4028A CD4028A BCD-to-Decimal Decoder D 3 16 4028B C04028B BCD-to-Decimal Decoder F 3A 16 D,K 3 4029A CO4029A Presettable Up/Down Counter D 3 16 4029B CD4029B Presettable Up/Down Counter F 3A 16 D,K 3 4030A CD4030A Quad Exclusive-OR Gate D 14 4030B CD4030B Quad Exclusive-OR Gate B 14 F 3A D,K 3 4031A CD4031A 64-Stage Static Shift Register D 3 16 4031B CD4031B 64-Stage Static Shift Register F 3A 16 D, K 3 6-28CMOS Logic ICs - CD4000B Series Product Number Selection Guide (Continued) GENERIC STANDARD | NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 4033B CD4033B Decade Counter/Divider D 3 16 4034B CD4034B 8-Stage Static Shift Register F 3A 24 D 3 4035B CD4035B 4-Stage Parallel-in/Parallel-Out Shift Register F 3A 24 D,K 3 4040A CD4040A 12-Stage Binary Ripple Counter D, K 3 16 4040B CD4040B 12-Stage Binary Ripple Counter F 3A 16 D 3 4041A CD4041A Quad True/Complement Butter D 3 14 4041UB CD4041UB Quad True/Complement Buffer F 3A 14 D,K 3 4042A CD4042A Quad Clocked D Latch D,K 3 16 4042B CD4042B Quad Clocked D Latch F 3A 16 D,K 3 4043A CD4043A Quad NOR A/S Latch (Three-State Outputs) D 3 16 4043B CD4043B Quad NOR R/S Latch (Three-State Outputs) F 3A 16 D 3 4044A CD4044A Quad NAND R/S Latch (Three-State Outputs) D 3 16 4044B C04044B Quad NAND R/S Latch (Three-State Outputs) F 3A 16 D 3 4046A CD4046A Micropower Phase-Locked Loop D 3 16 40468 CD40468 Micropower Phase-Locked Loop F 3A 16 D,K 3 4047B CD4047B Monostable/Astable Multivibrator F 3A 14 3 4048A CD4048A Multifunctional Expandable 8-Input Gate D 3 16 (Three-State Output) 4048B CD4048B Multifunctional Expandable 8-Input Gate F 3A 16 (Three-State Outputs) D 4049A CD4049A Hex Buffer/Converter (inverting) F B 16 D 4049UB CD4049UB Hex Buffer/Converter (inverting) F B 16 F 3A D,K 4050A CD4050A Hex Buffer/Converter (Non-Inverting) F B 16 D 4050B C04050B Hex Buffer/Converter (Non-Inverting) F B 16 F 3A D, K 3 6-29CMOS Logic ICs - CD4000B Series Product Number Selection Guide (Continued) GENERIC STANDARD NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 4051B CD4051B 8-Channel Analog Multiplexer/Demultiplexer F 3A 16 D,K 3 4052B CD4052B 4-Channel Analog Multiplexer/Demultiplexer F 3A 16 D, K 3 4053B CD4053B Analog Multiplexers/Demultiplexers F 3A 16 Triple 2-Channel D 3 4054B CD4054B 4-Segment Display Driver F 3A 16 4056B CD4056B BCD-to-7-Segment Decoder/Driver with F 3A 16 Strobed-Latch Function 4059A CD4059A Programmable Divide-by-N Counter D 3 24 4060A CD4060A 14-Stage Binary Ripple Counter/Divider and 3 16 Oscillator 4060B CD4060B 14-Stage Binary Ripple Counter/Divider and 3A 16 Oscillator D 3 4063B CD4063B 4-Bit Magnitude Comparator 3A 16 D,K 4066B CD40668 Quad Bilateral Switch F B 14 F 3A D,K 3 4067B CD4067B 16-Channel Analog Multiplexers/Demultiplexers F 3A 24 D 3 4068B CD4068B 8-Input NAND/AND Gate F 3A 14 D 4069UB CD4069UB Hex Inverter F B 14 F 3A D 4070B CD4070B Quad Exclusive-OR Gate F B 14 F 3A D 4071B CD4071B Quad 2-Input OR Gate F B 14 F 3A D, K 3 4072B CD4072B Dual 4-Input OR Gate F 3A 14 D 4073B CD4073B Triple 3-Input AND Gate F 14 F 3A D 3 6-30CMOS Logic ICs - CD4000B Series Product Number Selection Guide (Continued) GENERIC STANDARD NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 4075B CD4075B Triple 3-Input OR Gate F B 14 F 3A D, K 3 4076B CD4076B 4-Bit D Flip-Flop (Three-State Outputs) F 3A 16 D 3 4077B CD4077B Quad Exclusive-NOR Gate F 3A 14 D 3 40788 CD4078B 8-Bit NOT/OR Gate F 3A 14 D 4081B CD4081B Quad 2-Input AND Gate F B 14 F 3A D,K 4082B CD4082B Dual 4-Input AND Gate F B 14 F 3A D 3 4085B CD4085B Dual 2-Wide, 2-Input AND/OR/INVERT (AOl) F 3A 14 Gate D 3 4086B CD4086B Expandable 4-Wide, 2-Input AND/OR/INVERT F 3A 14 (AO!) Gate D 3 4089B CD4089B Binary Rate Multiplier F 3A 16 D 3 4093B CD4093B Quad 2-Input NAND Schmitt Trigger F 3A 14 D 3 40948 CD4094B 8-Stage Shift-and-Store Bus Register F 3A 16 D 3 4095B CD4095B Gated J-K Flip-Flop (Non-Inverting) F 3A 14 D 3 4096B CD4096B Gated J-K Flip-Flop (inverting and D 3 14 Non-Inverting) 4097B CD4097B 8-Channel Analog Multiplexer/Demultiplexer D 24 4098B CD4098B Dual Monostable Multivibrator F B 16 F 3A D,K 4099B CD4099B 8-Bit Addressable Latch F B 16 F 3A D,K 4502B CD4502B Strobed Hex Inverter/Buffer F B 16 F 3A D,K 3 6-31CMOS Logic ICs - CD4000B Series Product Number Selection Guide (Continued) GENERIC STANDARD | NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 4503B CD4503B Hex Buffer (Non-Inverting) F 3A 16 D 3 4504B CD4504B Hex Voltage-Level Shifter for TTL-to-CMOS F 3A 16 CMOS-to-CMOS Operation 4508B CD4508B Dual 4-Bit Latch F 3A 24 D,K 3 4510B CD4510B Presettable 4-Bit BCD Up/Down Counter 3A 16 D 3 4511B CD4511B BCD-to-7-Segment Latch Decoder/Driver F 3A 16 D,K 3 4512B CD4512B 8-Channel Data Selector (Three-State Output) F 3A 16 D 3 4514B CD4514B 4-Bit Latch/4-to-16 Line Decoder (Outputs Low) F 3A 24 D 3 4515B CD4515B 4-Bit Latch/4-to-16 Line Decoder (Outputs Low) F 3A 24 D 3 4516B CD4516B Presettable 4-Bit Binary Up/Down Counter F 3A 16 D 3 4517B CD4517B Dual 64-Bit Shift Register F 3A 16 D 3 4518B CD4518B Dual BCD Up Counter F 3A 16 D 3 4520B CD4520B Dual Binary Up Counter F 3A 16 D 3 4527B CD4527B BCD Rate Multiplier D 16 4532B CD4532B B-Input Priority Encoder F 3A 16 D 3 45368 CD4536B Programmable Timer F 3A 16 D 3 4541B CD4541B CMOS Programmable Timer F 3A 14 4555B CD4555B Dual 1 of 4 Decoder/Demultiplexer F 3A 16 (Outputs High) 4556B CD4556B Dual Binary to 1 of 4 Decoder/Demultiplexers F 3A 16 (Outputs Low) D 3 4585B CD4585B 4-Bit Magnitude Comparator F 3A 16 4724B CD4724B 8-Bit Addressable Latch F 3A 16 14538B CD14538B Dual Precision Monostable Multivibrator F 3A 16 40100B CD40100B 9-Bit Parity Generator/Checker D 3 16 6-32CMOS Logic ICs - CD4000B Series Product Number Selection Guide (Continued) GENERIC STANDARD NUMBER PART TYPE PACKAGE SCREENING OF NUMBER NUMBER CIRCUIT FUNCTION DESIGNATOR LEVELS PINS 40101B CD40101B 9-Bit Parity Generator/Checker F 3A 14 D 3 40102B CD40102B Presettable 2-Decade BCD Down Counter D 3 16 40103B CD40103B Presettable 8-Bit Binary Down Counter F 3A 16 D 3 401048 CD40104B8 4-Bit Bidirectional Universal Shift Register D 3 16 40105B CD40105B 4-Bit X 16 Word FiFo Buffer Register F 3A 16 D, K 3 40106B CD40106B Hex Schmitt Trigger F 3A 14 D,K 3 40107B CD40107B Dual 2-Input NAND Buffer/Driver F 3A 14 D 3 40108B CD40108B 4X 4 Multiport Register D 3 24 40109B CD40109B Quad Low-to-High Voltage Interface F 3A 16 D,K 3 40116 CD40116 CMOS High Speed 8-Bit Directional D 3 22 CMOS/TTL Interface Level Converter (GP11 is Rad-Hard Version) 40160B CD40160B Synchronous Programmable 4-Bit Counter F 3A 16 Decade with Asynchronous Clear 40161B CD40161B Synchronous Programmable 4-Bit Counter 3A 16 Binary with Asynchronous Clear 3 40163B CD40163B Synchronous Programmable 4-Bit Counter F 3A 16 Binary with Synchronous Clear 40174B CD40174B Hex D Type Flip-Flop F 3A 16 D 3 40175B CD40175B Quad D' Type Flip-Flop F 3A 16 40192B CD40192B CMOS Look-Ahead Carry Generator F 3A 16 D 3 40193B CD40193B CMOS Presettable Up/Down Counters F 3A 16 (Dual Clock with Reset) D 3 40194B CD40194B 4-Bit Bidirectional Universal Shift Register D,K 3 16 40257B CD40257B Quad 2-Line-to-1-Line Data Selector/Multiplexer F 3A 16 D 3CMOS Logic ICs - CD4000B Series MIL-I-38535 to Harris Hi-Rel Types Sorted by JAN Type MIL-I HARRIS MIL-I HARRIS MIL-I HARRIS DESIGNATION TYPE DESIGNATION TYPE DESIGNATION TYPE JM38510/05001BCA CD4011AFB JM38510/05301BCA CD4007AFB JM38510/05655BCA CD4024BFB JM38510/05003BCA CD4023AFB JM38510/05302BEA CD4019AFB JM38510/05754BEA CD4021BFB JM38510/05051BCA CD4011BFB JM38510/05352BEA CD4019BFB JM38510/05852BCA CD4066BFB JM38510/05052BCA CD4012BFB JM38510/05353BCA CD4030BFB JM38510/17001BCA CD4081BFB JM38510/05053BCA CD4023BFB JM38510/05503BEA CD4049AFB JM38510/17002BCA CD4082BFB JM38510/05101BCA CD4013AFB JM38510/05504BEA CD4050AFB JM38510/17003BCA CD4073BFB JM38510/05102BEA CD4027AFB JM38510/05553BEA CD4049UBFB JM38510/17101BCA CD4071BFB JM38510/05151BCA CD4013BFB JM38510/05554BEA CD4050BFB JM38510/17103BCA CD4075BFB JM38510/05152BEA CD4027BFB JM38510/05601BEA CD4017AFB JM38510/17203BCA CD4070BFB JM38510/05201BCA CD4000AFB JM38510/05603BEA CD4020AFB JM38510/17401BCA CD4069UBFB JM38510/05202BCA CD4001AFB JM38510/05605BCA CD4024AFB JM38510/17403BEA CD4502BFB JM38510/05204BCA CD4025AFB JM38510/05651BEA CD4017BFB JM38510/17504BEA CD4098BFB JM38510/05252BCA CD4001BFB JM38510/05652BEA CD4018BFB JM38510/17601BEA CD4099BFB JM38510/05254BCA CD4025BFB JM38510/05653BEA CD4020BFB SMD or DESC Parts List Lot Screening Tests SMD OR HARRIS The Total Lot Screening Table indicates the screening per- DESC NUMBER PART NUMBER formed on JAN 8, 3 and 3A devices. 3 and 3A are equivalent 7702002EA CD4502BF3A to MIL-STD-883 Class B screens to Method 5004. As shown in the Manufacturing and Conformance Testing table, the dif- 7702301EA CD4520BF3A ferences between a 3 and 3A is the lead finish and pellet 7702402CA CD4081BF3A mounting technique. It should be noted that all CD4XXXB- THOR CDaoHEFE Se ace ae a AN cones 7703201JA CD4515BF3A U.S. is completely assembled and tested on our JAN-certi- 7703702EA CD4585BF3A fied line. 7704402CA CD4078BF3A 7704403CA CD4002BF3A 7704701EA CD4555BF3A 7704801EA CD4556BF3A 7705102CA CD4073BF3A 7705902CA CD4082BF3A 7706002CA CD4072BF3A 8101602EA CD4029BF3A 8101801EA CD4053BF3A 8102001CA CD4047BF3A 5962-9064001CA CD4016BF3A 5962-S055701EA CD14538BF3A 7704602CA CD4093BF3A 7901502EA CD4052BF3A 8101701EA CD4035BF3A NOTE: 1. Product is dual branded with SMD/DESC and Harris part number.CMOS Logic ICs - CD4000B Series Total Lot Screening For High-Reliability CD4000B Series ICs PRODUCT JAN B, 3, 3A, SCREENING TESTS TEST CONDITIONS METHOD AND SMD NOTES Pre-Cap Visual at Assembly Condition B 2010 xX - PRECONDITIONING Stabilization Bake (Optional) Condition C 1008 X - Temperature Cycle Condition C 1010 xX - Centrifuge Condition E, 1 Only 2001 Xx - Fine Leak Condition B 1014 Xx - Gross Leak Condition C 1014 x - TEST AND BURN-IN Initial Test - x 1 Static Burn-in 2 +135C Inputs at Vop, 1015 x 1,2,3,4 120 Hours Outputs Open Final Elec DC +25C - x - Final Elec DC+125C - xX . Final Elec DC -55C - xX - Final Elec AC +25C : xX - FINAL INSPECTION Quality Conformance Inspection 5005 x - (Group A) 100% Visual Inspect 2009 x - NOTES: 1. See individual data bulletins for electrical testing of specific types or JAN Slash Sheets as applicable. 2. Alternate time/temp regression used per /883 Method 1015. 3. PDA for 3 and 3A is 5%, one reburn allowed at 3%. 4. PDA's are based on Group A subgroup 1. 6-35CMOS Logic ICs - CD4000B Series Product Flow Diagrams JAN CLASS B CMOS ICs PRECAP INTERNAL STABILITY BAKE TEMPERATURE CONSTANT VISUAL INSPECTION 1883 METHOD 1008 CYCLING >| = ACCELERATION 1883 METHOD 2010 (OPTIONAL) /883 METHOD 1010 1883 METHOD 2001 LEAK TEST 120HR AT +135C *] FINE AND GROSS ELECTRICALS STATIC BURN - IN >| ELECTRICALS #883 METHOD 1014 /883 METHOD 1015 ; METHOD 5005 EXTERNAL VISUAL > GROUP A METHOD 2009 CLASS + EVERY T EVERY + EVERY BY PURCHASE LOT 13 WEEKS 26 WEEKS ORDER GROUP B GROUP C GROUP D GROUP E Class B Screening Tests Precap Visual inspection * Stability Bake (Optional) * Temperature Cycling SMD, DESC, LEVEL 3, AND LEVEL 3A Constant Acceleration Fine and Gross Leak Tests * Preburn Electrical * 120 Hour Static Burn-in at +135C Final Electrical External Visual GROUP C METHOD 5005 GROUP B METHOD 5005 PRECAP COND. B STABILITY BAKE TEMPERATURE CONSTANT VISUAL INSPECTION > METHOD 1008 CYCLING > ACCELERATION METHOD 2010 (OPTIONAL) METHOD 1010 METHOD 2001 LEAK TEST PREGURN 120HR AT +135C FINAL ELECTRICALS > FINE & GROSS ELECTRICALS STATIC BURN - IN py OAT + 25C, - 55C METHOD 1014 | AT + 25C | 1883 METHOD 1015 AND + 125C GROUP A EXTERNAL VISUAL LEVEL METHOD 5005 METHOD 2009 " 3 pf LEVEL r EVERY tT EVERY r EVERY 3A LOT 13 WEEKS 26 WEEKS GROUP D METHOD 5005 6-36CMOS Logic ICs - CD4000B Series Absolute Maximum Ratings Reliability Information DC Supply-Voltage Range, Vop Thermal Resistance 8y4 85c (Voltages Referenced to Vgg Terminal) ......... -0.5V to +20V Package Types DandF................ 83.3CAW =. 28C/W Input Voltage Range, All Inputs ............. -0.5V to Vop +0.5V Package Type K........ 0.0 c cee eee 83.3C/W 22C /W DC Input Current, Any One Input...................0..0... +10mA Maximum Power Dissipation Per Package, Pp Operating Temperature Range, Ts For Ta = -55C to +100C, Package Types D,F,K .................05- -55C to +125C Package Types D,F,K. 0... cece eee 500mW Storage Temperature Range, Tstg ...---....-- -65C to +150C For Ta = +100C to +125C, Lead Temperature (During Soldering) Package Types D,F.K...... Derate Linearly at 12mWPC to 200mW At Distance 1/16in. + 1/32in. (1.59mm + 0.79mm) Device Dissipation Per Output Transistor From Case for 10s Maximum ............... 000005 +265C Ta = Full Package Temperature Range All Package Types ... 00... cee eee 100mWw CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the davice at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions For maximum reliability, normal operating conditions should be selected so that operation is always within the following ranges: Supply Voltage Range For T, = Full Package Temperature Range . .3V to 18V Device Classification for Leakage Current The table below classifies the levels of device leakage as SSI, MSI-1 and MSI-2. In order to determine the limits which apply to specific device type, consult the Standard DC Electrical Specifications table. Classification According To Circuit Complexity BUFFERS/FLIP-FLOPS/ LATCHES/MULTILEVEL GATES/ANVERTERS (SSI) GATES (MSI-1) COMPLEX LOGIC (MSI-2) CD4000B _CD4025B CD4009UB (Note 1) CD4085B CD4006B CD4056B (Note 1) CD4541B CD4000UB CD4025UB CD4010B (Note 1) CD4086B cD4008B CD4060B CD4555B CD4001B CD4048B CD4013B CD4093B (Note 1) [CD4014B CD4063B CD4556B CD4001UB CD4066B (Note 1)|CD40198 CD40958 CD4015B (Note 1) CD4067B (Note 1) CD4585B CD4002B CD4068B CD40278 cD4096B CD4017B CD4076B CD47248 CD4002UB CD4069UB CD4030B CD4098B CD4018B CD4089B CD14538B CD4007UB CD4071B CD4041UB (Note 1) CD4502B (Note 1) |cD40208 CD4094B CD40100B CD4011B CD4072B CD4042B CD4503B (Note 1) [CD4021B CD4097B (Note 1) CD40101B CD4011UB CD4073B CD40438 CD4504B (Note 1) 1CD40228 CD4099B CD40102B CD4012B CD4075B CD4044B CD40106B (Note 1)|CD4024B CD4508B CD40103B CD40168 CD4078B CD4047B CD40107B (Note 1)(CD4028B CD4510B CD40104B (Note 1) p4081B CD4049UB (Note 1) CD40109B (Note 1)|CD4029B CD4511B (Note 1) CD40105B CD4023B CD4082B CD4050B (Note 1) CD40174B CD4031B (Note 1) CD4512B CD40108B CD4023UB CD4070B CD40175B CD4033B CD4514B CD40116 (Note 1) CD4077B CD40257B CD4034B CD4515B CD40160B CD40358 CD4516B CD40161B CD4040B CD4517B CD40163B CD4046B (Note 1) CD4518B CD401928 CD4051B (Note 1) CD4520B CD40193B CD4052B (Note 1) CD4527B CD40194B CD4053B (Note 1) CD4532B CD4054B (Note 1) CD4536B NOTE: 1. Indicates type for which, because of design requirements, one or more DC Specifications differ from the standardized data. These differences are defined in separate DC Electrical Specifications table. 6-37CMOS Logic ICs - CD4000B Series DC Electrical Specifications - Standard B Series Devices For all CD4000B Series Standard Output CMOS Devices. Parameters are 100% Tested Unless Otherwise Specified. TEST CONDITIONS -55C +25C +125C PARAMETERS Vo Vin Vpp MIN MAX MIN MAX MIN MAX UNITS Functional Test (Notes 1 and 2) - - - - - - - - - Quiescent Device SSI Types - 0,5 5 - 0.25 - 0.25 - 75 HA Current Ipp (Note 3) (Note 2) (Note 2) (Note 2) See Classification Table - 0, 10 10 - 0.5 - 0.5 - 15 HA (Note 2) (Note 2) (Note 2) - 0, 15 15 - 1 - 1 - 30 pA (Note 2) (Note 2) (Note 2) : 0, 20 20 : 5 - 5 - 150 pA MSI-1 - 0,5 5 - 1 - 1 - 30 HA (Note 3 and (Note 2) (Note 2) (Note 2) Note 4) - 0, 10 10 - 2 - 2 - 60 pA (Note 2) (Note 2) (Note 2) - 0, 15 15 - 4 - 4 - 120 pA (Note 2) (Note 2) (Note 2) - 0, 20 20 - 20 - 20 - 600 pA MSI-2 - 0,5 5 - 5 - 5 - 150 pA (Note 3) (Note 2) (Note 2) (Note 2) - 0, 10 10 - 10 - 10 - 300 pA (Note 2) (Note 2) (Note 2) : 0, 15 15 - 20 - 20 - 600 pA (Note 2) (Note 2) (Note 2) - 0, 20 20 - 100 - 100 - 3000 HA Output Low Drive Current, lo. Min 0.4 0,5 5 0.64 - 0.51 - 0.36 - mA (Note 2) (Note 2) 0.5 0, 10 10 1.6 - 1.3 - 0.9 - mA (Note 2) (Note 2) 15 0, 15 15 4.2 - 3.4 : 2.4 : mA (Note 2) (Note 2) Output High Drive Current, Ioy Min 4.6 0,5 5 -0.64 : -0.51 . -0.36 - mA (Note 2) 2.5 0,5 5 -2.0 : -1.6 - -1.15 - mA (Note 2) 9.5 0, 10 10 1.6 - -1.3 - -0.9 - mA (Note 2) 13.5 0, 15 15 -4.2 - -3.4 - -2.4 - mA (Note 2) 6-38CMOS Logic ICs - CD4000B Series DC Electrical Specifications - Standard B Series Devices (Continued) For all CD4000B Series Standard Output CMOS Devices. Parameters are 100% Tested Unless Otherwise Specified. TEST CONDITIONS -55C +25C +125C PARAMETERS Vo Vin Vop MIN MAX MIN MAX MIN MAX [ UNITS Output Voltage Low-Level, Vo, Max : 0,5 5 - 0.05 - 0.05 - 0.05 Vv (Note 2) (Note 2) (Note 2) - 0, 10 10 - 0.05 - 0.05 - 0.05 v (Note 2) (Note 2) (Note 2) - 0, 15 15 - 0.05 - 0.05 - 0.05 Vv Output Voltage High-Level, Vqy Min - 0,5 5 4.95 - 4.95 - 4.95 - Vv (Note 2) (Note 2) - 0, 10 10 9.95 - 9.95 - 9.95 - Vv (Note 2) (Note 2) - 0, 15 15 14.95 : 14.95 : 14.95 - Vv Input Low Voltage Buffered (B) 45 - 5 - 1.5 - 1.5 - 1.5 Vv Vin Max 9 - 10 - 3 - 3 - 3 Vv (Note 2) 13.5 - 15 - 4 - 4 - 4 Vv Unbuffered 45 - 5 - 1 - 1 - 1 Vv (UB) (Note 2) 9 - 10 - 2 - 2 - 2 Vv 13.5 - 15 2.5 2.5 25 Vv Input High Voltage _ Buffered (B) 0.5, 4.5 - 5 3.5 - 3.5 - 3.5 - Vv Vin Min 1,9 - 10 7 - 7 - 7 : Vv 1.5, : 15 1 - 11 - 11 : Vv 13.5 Unbuffered | 0.5, 4.5 - 5 4 - 4 - 4 - Vv (UB) 1,9 - 10 8 - 8 : 8 - Vv 1.5, - 15 12.5 - 12.5 - 12.5 - Vv 13.5 Input Current lig - 0, 20 20 - +0.1 - +0.1 - +1 pA (Note 3) Three-State Output Leakage 0, 20 0, 20 20 - +0.4 - +0.4 - +12 pA Current, Ioy7 (Note 3 and Note 5) NOTES: 1. At 425C Viy = 0 - 20V, Vpp = 20V; +125C Viy = 0 -18V, Vpp = 18V; and at -55C Vix = 0 - 3V, Vpp = 3V. 2. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 3. At-55C, test is performed with Vpp of 18V. 4. CD4047B - Maximum DC supply voltage Vpp is 13V for radiation hardened version of this type when operating with RC network. 5. For applicable devices only. 6-39CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications The table below indicates all devices which are considered to be non-standard. Non-standard devices are types such as bilateral switches (CD4066B), multiplexers (CD4051B), spe- cial sink or source currents (CD4049UB, CD4050B) and open drain buffer/drivers (CD40107B) which exhibit non- standard outputs or special parameters. This table shows the 100% electrical tests that are performed on these spe- cialized devices. These tests take the place of corresponding parameters in the Standard Electrical Specifications table. For the types listed with Roy tests, drive current and output voltage tests should be deleted from the Standard Electrical Specifications table. Non-Standard DC Electrical Specifications B Series Devices TEST CONDITIONS -55C +25C +125C MIN/ MIN/ PARAMETERS Vo Vin Vop MAX MIN MAX MAX UNITS CD4009UB, CD4010B Output Low Drive Current, Io, Min 0.4 0,5 45 3.2 2.6 - 1.8 mA (Note 2) 0.4 0,5 5 3.75 3 - 2.1 mA (Note 1) 0.5 0, 10 10 10.0 8 - 5.6 mA (Note 1) 15 0, 15 15 30.0 24 - 16.0 mA (Note 1) Output High Drive Current, lo, Min 4.6 0,5 5 -0.25 -0.2 - -0.15 mA (Note 2) (Note 1) 2.5 0,5 5 -1.0 -0.8 - -0.58 mA (Note 1) 9.5 0, 10 10 -0.55 -0.45 : -0.33 mA (Note 1) 13.5 0, 15 15 1.65 1.5 - 11 mA (Note 1) CD4016B Control Input Voltage Low, Vit Max Vis = Vss, Vos = Vop 5 0.9 - 0.7 0.4 Vv (Note 2) Vis = Vop. Vos = Vss (Note 1) (Note 1) (Note 1) Hist < 1OHA 10 0.9 - 0.7 0.4 Vv 15 0.9 - 0.7 0.4 Vv (Note 1) (Note 1) | (Note 1) Control Input Voltage High, Vi, Min - 5 3.5 3.5 : 3.6 Vv (Note 2) (Note 1) (Note 1) (Note 1) 10 7.0 7.0 - 7.0 15 11.0 11.0 : 11.0 (Note 1) (Note 1) (Note 1) On-State Resistance, Roy Max Vis = Vpp OF Vsg 10 600 - 660 960 Q R, = 10K Returned to Vpp - Vss/2 Vig = 4.75 or 5.75 (Note 1) (Note 1) | (Note 1) = V. (Note 2) vis = Yoo oF ss. 10 1870 - 2000 2600 | a ise (Note 1) (Note 1) ff (Note 1) 15 360 - 400 600 Q (Note 1) (Note 1) (Note 1) 15 775 - 850 1230 Q (Note 1) (Note 1) (Note 1) 6-40CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -55C +25C +125C MIN/ MIN/ PARAMETERS Vo Vin Vop MAX MIN MAX MAX UNITS CD4031B Output Low Drive Current, Ip, Min 0.4 0,5 5 2.56 2.04 - 1.44 mA Q (Note 1) (Note 2) 0.5 0, 10 10 6.4 5.2 : 3.6 mA (Note 1) 1.5 0, 15 15 16.8 13.6 - 9.6 mA (Note 1) Ga,c 0.4 0, 5 5 0.64 0.51 - 0.36 mA (Note 2) (Note 1) 0.5 0, 10 10 1.6 1.3 - 0.9 mA (Note 1) 1.5 0, 15 15 4.2 3.4 - 2.4 mA (Note 1) Output High Drive Current, lo, Min 4.6 0,5 5 -0.64 -0.51 - -0.36 mA Q,,Q',Cip (Note 1) Note 2 (Note 2) 25 0,5 5 20 | -16 - 1.15 | mA (Note 1) 9.5 0, 10 10 -1.6 -1.3 - -0.9 mA (Note 1) 13.5 0,15 15 -4.2 -3.4 - -2.4 mA (Note 1) CD4041UB Output Low Drive Current, lo, Min 0.4 0,5 5 2.1 1.6 - 1.2 mA (Note 2) (Note 1) 0.5 0, 10 10 6.25 5 - 3.5 mA (Note 1) 1.5 0, 15 15 24 19 - 13 mA (Note 1) Output High Drive Current, lo, Min 4.6 0,5 5 -2.1 -1.6 - -1.2 mA (Note 2) (Note 1) 25 0,5 5 -8.4 -6.4 - -4.6 mA (Note 1) 9.5 0, 10 10 -6.25 5 - -3.5 mA (Note 1) 13.5 0, 15 15 -24 -19 - -13 mA (Note 1) CD4046B Zener Diode Voltage (Vz) lz = 50nA - 4.45 6.5 - Vv (Note 3) (Note 1) | (Note 1) Quiescent Leakage, Phase Comparator : 0,5 5 0.2 - 0.2 - mA Pin 14 Open, Pin 5 = Vpp : (Note 3) - 0, 10 10 1.0 - 1.0 mA - 0,15 15 1.5 - 1.5 - mA - 0, 20 20 4.0 - 4.0 - mA (Note 1) (Note 1) 6-41CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -55C +25C +125C MIN/ MIN/ PARAMETERS Vo Vin Vpp MAX MIN MAX MAX UNITS CD4046B (Continued) Quiescent Leakage, Phase Comparator - 0,5 5 20 - 20 - pA Pin 14 = Vgs or Vop: Pin5= Vop (Note 3) - 0, 10 10 40 - 40 . pA - 0, 15 15 80 - 80 - pA - 0, 20 20 160 - 160 - pA (Note 1) (Note 1) CD4049UB, CD4050B Output Low Drive Current, Io, Min 0.4 0,5 45 3.3 2.6 - 1.8 mA (Note 2) (Note 1) 0.4 0,5 5 4.0 3.2 - 2.4 mA (Note 1) 0.5 0, 10 10 10 8.0 - 5.6 mA (Note 1) 1.5 0, 15 15 26 24 - 18 mA (Note 1) Output High Drive Current, loy Min 4.6 0,5 5 -0.81 -0.8 - -0.48 mA (Note 2) (Note 1) 2.5 0,5 5 -2.6 -3.2 - -1.55 mA (Note 1} 9.5 0, 10 10 -2.0 -1.8 - -1.18 mA (Note 1) 13.5 0, 15 15 -5.2 -6.0 - 3.1 mA (Note 1) CD4051B, CD4052B, CD4053B, CD4067B, CD4097B ON-State Resistance, Roy Max R, = 10K Returned to 5 800 - 1050 1300 Q (Note 3) Vop - Vss/2 (Note 1) (Note 1) | (Note 1) Vis = Vss t Yop 10 310 - 400 500 Q (Note 1) (Note 1) (Note 1) 16 200 - 240 320 Q (Note 1) (Note 1) (Note 1) Input Voltage Low, Vj, Max Vee = Vss 5 1.5 . 1.5 1.5 Vv (Note 2) R, = 1K to Vgg (Note 1) (Note 1) ff (Note 1) Isl < 2HA 10 3.0 - 3.0 3.0 15 4.0 - 4.0 4.0 (Note 1) (Note 1) (Note 1) Input Voltage High, V4 Min Vee=Vss 5 3.5 3.5 - 3.5 Vv (Note 2) Ry = 1K to Vsg (Note 1) (Note 1) (Note 1) list < 2H 10 7.0 7.0 - 7.0 15 11.0 11.0 - 11.0 (Note 1) ff (Note 1) (Note 1) Off Channel Leakage Current Vgg = 0 Vee =0 18 +100 : +100 +1000 nA Any Channel! Off Max (Note 1) (Note 1) (Note 1) (Note 3) Off Channel Leakage Current Vgg = 0 Veg =0 18 +100 - +100 +1000 nA All Channels (Common Out/In) Off Max (Note 1) (Note 1) (Note 1) (Note 3) 6-42CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -55C +25C +125C MIN/ MIN/ PARAMETERS Vo Vin Vop MAX MIN MAX MAX UNITS CD4054B, CD4056B Vee | Vss Output Low (Sink) 5 0 -4.5 - 5 0.98 0.8 - 0.55 mA Current, lo. (Note 1) Note 2 ( ) 0 0 0.5 - 10 0.98 0.8 - 0.55 mA (Note 1) 0 0 1.5 - 15 3.6 2.9 - 2 mA (Note 1) Output High (Source) -5 0 45 - 5 -0.6 -0.45 - -0.3 mA Current, low (Note 1) Note 2 (Note 2) 0 | 0 95 : 10 06 | -045 ; 03 | mA (Note 1) 0 0 13.5 - 15 -1.9 -1.5 - -1.1 mA (Note 1) CD4066B On-State Resistance, Roy Max R, = 10K Returned to 5 800 - 1050 1300 Q (Note 3) Vop - Vss/2 (Note 1) (Note 1) (Note 1) Vis = Vgs to V; is = ss 10 Yoo 10 310 , 400 550 a (Note 1) (Note 1) (Note 1) 15 200 - 240 320 Q (Note 1) (Note 1) f (Note 1) Control Input Voltage Low, Viic Max Vis = Vss, Vos = Von, 5 1.0 : 1.0 1.0 Vv (Note 2) Vis = Vop, Vos = Vss (Note 1) (Note 1) (Note 1) | 1 isl < TOA 10 2.0 - 2.0 2.0 15 2.0 - 2.0 2.0 (Note 1) (Note 1) (Note 1) Control Input Voltage High, Vince Min - 5 3.5 3.5 - 3.5 Vv (Note 2) (Note 1) (Note 1) (Note 1) 10 7.0 7.0 : 7.0 15 11.0 11.0 - 11.0 (Note 1) | (Note 1) (Note 1) Input/Output Leakage Current (Switch Off) 0 0 18 +100 - +100 +1000 nA Effective Off Resistance Vc = Vss (Note 3) CD4093B Positive Trigger Vp Min - (Note 4) 5 2.2 2.2 - 2.2 Vv Threshold Voltage (Note 1) (Note 1) (Note 1) (Note 3) . (Note 4) 10 4.6 46 : 46 V - (Note 4) 15 6.8 6.8 - 6.8 Vv (Note 1) (Note 1) (Note 1) - (Note 5) 5 2.6 2.6 - 2.6 Vv (Note 1) (Note 1) (Note 1) - (Note 5) 10 5.6 5.6 - 5.6 - (Note 5) 15 6.3 6.3 - 6.3 6-43CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -55C +25C +#125C MIN/ MIN/ PARAMETERS Vo Vin Vop MAX MIN MAX MAX UNITS CD4093B (Continued) Positive Trigger Vp Max - (Note 4) 5 3.6 - 3.6 3.6 Vv Threshold Voltage (Note 1) (Note 1) ff (Note 1) (Note 3) - (Note 4) 10 7.1 - 7.1 7.1 - (Note 4) 15 10.8 - 10.8 10.8 (Note 1) (Note 1) J (Note 1) : (Note 5) 5 4 - 4 4 V (Note 1) (Note 1) (Note 1) - (Note 5) 10 8.2 - 8.2 8.2 : (Note 5) 15 12.7 - 12.7 12.7 Negative Trigger Vy Min - (Note 4) 5 0.9 0.9 : 0.9 Vv Threshold Voltage (Note 1) (Note 1) (Note 1) (Note 3) : (Note 4) 10 2.5 2.5 - 2.5 - (Note 4) 15 4 4 - 4 (Note 1) (Note 1) (Note 1) - (Note 5) 5 1.4 1.4 - 1.4 Vv (Note 1) (Note 1) (Note 1) - (Note 5) 10 3.4 3.4 - 3.4 - (Note 5) 15 4.8 4.8 - 4.8 Vn Max - (Note 4) 5 2.8 - 2.8 2.8 Vv (Note 1) (Note 1) | (Note 1) - (Note 4) 10 5.2 - 5.2 5.2 Vv - (Note 4) 15 7.4 - 7.4 7.4 Vv (Note 1) (Note 1) ff (Note 1) - (Note 5) 5 3.2 - 3.2 3.2 Vv (Note 1) (Note 1) f (Note 1) - (Note 5) 10 6.6 - 6.6 6.6 - (Note 5) 15 9.6 - 9.6 9.6 Hysteresis Voltage Vy Min - (Note 4) 5 0.3 0.3 - 0.3 (Note 3) (Note 1) (Note 1) (Note 1) - (Note 4) 10 1.2 1.2 - 1.2 - (Note 4) 15 1.6 1.6 - 1.6 (Note 1) (Note 1) (Note 1) - (Note 5) 5 0.3 0.3 - 0.3 Vv (Note 1) (Note 1) (Note 1) - (Note 5) 10 1.2 1.2 - 1.2 - (Note 5) 15 1.6 1.6 - 1.6 6-44CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -55C +25C +125C MIN/ MIN/ PARAMETERS Vo Vin Vpop MAX MIN MAX MAX UNITS CD4093B (Continued) Hysteresis Voltage Vi Max - (Note 4) 5 1.6 . 1.6 1.6 Vv (Note 3) (Note 1) (Note 1) (Note 1) - (Note 4) 10 3.4 - 3.4 3.4 - (Note 4) 15 5 - 5 5 (Note 1) (Note 1) (Note 1) - (Note 5) 5 1.6 - 1.6 1.6 Vv (Note 1) (Note 1) (Note 1) - (Note 5) 10 3.4 - 3.4 3.4 - (Note 5) 15 5 - 5 5 CD4502B Output Low Drive Current, Ig, Min 0.4 0,5 5 3.84 3.06 - 2.16 mA (Note 2) (Note 1) 0.5 0, 10 10 9.6 7.8 : 5.4 mA (Note 1) 1.5 0, 15 15 25.2 20.4 . 14.4 mA (Note 1) CD4503B Output Low Drive Current, Io, Min 0.4 0 5 2.6 2.1 - 1.3 mA (Note 2) (Note 1) 0.5 0 10 6.5 5.5 - 3.8 mA (Note 1) 1.5 0 15 19.2 16.1 - 11.2 mA (Note 1) Output High Drive Current, lo} Min 4.6 5 5 -1.2 -1.02 - -0.7 mA (Note 2) (Note 1) 2.5 5 5 -5.8 -4.8 - -3.0 mA (Note 1) 9.5 10 10 3.1 -2.6 - -1.8 mA (Note 1) 13.5 15 15 -8.2 -6.8 - -4.8 mA (Note 1) CD4504B Vec Input Low Voltage TTL-CMOS 5 1 - 10 0.8 - 0.8 0.8 Chote 2) TTL-CMOS | 5 1 : 15 0.8 - 08 0.8 (Note 1) (Note 1) (Note 1) CMOS-CMOST|T 5 1 - 10 1.5 - 1.5 1.5 Vv (Note 1) (Note 1) | (Note 1) CMOS-CMOS] 5 1.5 - 15 1.5 - 1.5 1.5 v CMOS-CMOS] 10 1.5 15 3 - 3 3 Vv (Note 1) (Note 1) J (Note 1) 6-45CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) PARAMETERS CD4504B (Continued) TTL-CMOS TTL-CMOS Input High Voltage Vin Min (Note 2) CMOS-CMOS CMOS-CMOS CMOS-CMOS CD4511B Output Voltage High-Level, Vo, Min (Note 3) Output Drive Voltage High Level, Voy Min (Note 3) Output Drive Voltage High Level, Voy Min (Note 3) Output Drive Voltage High Level, Voy Min (Note 3) Vo TEST CONDITIONS Vin Vpp 55C MIN/ MAX 2 (Note 1) 3.5 (Note 1) 3.5 7 (Note 1) 4 9 14 (Note 1) 13.90 13.75 13.65 +25C MIN MAX 2 2 (Note 1) 3.5 (Note 1) 3.5 7 (Note 1) 41 9.1 14.1 (Note 1) 41 3.9 3.4 (Note 1) 3.1 9.1 9.0 8.6 (Note 1) 8.3 14.10 14.0 13.70 (Note 1) 13.50 2 2 (Note 1) 3.5 (Note 1) 3.6 7 (Note 1) 4.2 9.2 14.2 (Note 1) 6-46CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -55C +25C +125C MIN/ MIN/ PARAMETERS Vo Vin Vppo MAX MIN MAX MAX UNITS CD4541B Output Low Drive Current, lo, Min 0.4 0,5 5 1.9 1.55 - 1.08 mA (Note 2) (Note 1) 0.5 0, 10 10 5.0 4.0 - 2.8 mA (Note 1) 1.5 0, 15 15 12.6 10.0 - 7.2 mA (Note 1) Output High Drive Current, loy Min 46 0,5 5 -1.9 -1.55 : -1.08 mA (Note 2) (Note 1) 2.5 0,5 5 -6.2 -5.0 - -3.0 mA (Note 1) 9.5 0, 10 10 -5.0 -4.0 - 2.8 mA (Note 1) 13.5 0, 15 15 -12.6 -10.0 - -7.2 mA (Note 1) CD40106B Positive Trigger Threshoid Vp Min - - 5 2.2 2.2 - 2.2 Vv Voltage (Note 1) (Note 1) (Note 1) (Note 3) . - 10 4.6 4.6 , 4.6 V (Note 1) (Note 1) (Note 1) - - 15 6.8 6.8 : 6.8 Vv (Note 1) (Note 1) (Note 1) Vp Max - - 5 3.6 - 3.6 3.6 Vv (Note 1) (Note 1) (Note 1) - - 10 7.1 - 7.1 7.1 Vv (Note 1) (Note 1) ff (Note 1) - - 15 10.8 - 10.8 10.8 Vv (Note 1) (Note 1) (Note 1) Negative Trigger Vy Min - - 5 0.9 0.9 - 0.9 Vv Threshold Voltage (Note 1) ff (Note 1) (Note 1) (Note 3) , - 10 25 2.5 - 2.5 V (Note 1) (Note 1) (Note 1) . - 15 4 4 - 4 Vv (Note 1) (Note 1) (Note 1) Vy Max - - 5 2.8 - 2.8 2.8 Vv (Note 1) (Note 1) (Note t) - - 10 5.2 - 5.2 5.2 Vv (Note 1) (Note 1) (Note 1) - - 15 7.4 - 7.4 7.4 Vv (Note 1) (Note 1) (Note 1) Hysteresis Voltage Vy Min - - 5 0.3 0.3 - 0.3 Vv (Note 3) (Note 1) (Note 1) (Note 1) - - 10 1.2 1.2 - 1.2 Vv (Note 1) J (Note 1) (Note 1) - - 15 1.6 1.6 - 1.6 v (Note 1) | (Note 1) (Note 1) 6-47CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -5C +25C +#125C MIN/ MIN/ PARAMETERS Vo Vin Vop MAX MIN MAX MAX UNITS CD40106B (Continued) Hysteresis Voltage Vi Max : - 5 1.6 - 1.6 1.6 Vv (Note 3) (Note 1) (Note 1) J (Note 1) - - 10 3.4 - 3.4 3.4 Vv (Note 1) (Note 1) (Note 1) - - 15 5 - 5 5 Vv (Note 1) (Note 1) (Note 1) CD40107B Output Low Current, lo, Min 0.4 0,5 5 21 16 - 12 mA (Note 2) (Note 1) 1 0,5 5 44 34 - 25 mA (Note 1) 0.5 0, 10 10 49 37 - 28 mA (Note 1) 1 0,10 10 89 68 - 51 mA (Note 1) 0.5 0, 15 15 66 50 - 38 mA (Note 1) Output High Current, lo, Min NO INTERNAL PULL-UP DEVICE (Note 2) Input Low Voltage, Vit Max Vo Vin Vpp (Note 2 and Note 6) 4.5 - 5 1.5 - 1.5 1.5 Vv (Note 1) (Note 1) (Note 1) 9 - 10 3.0 : 3.0 3.0 13.5 - 15 4.0 - 4.0 4.0 (Note 1) (Note 1) (Note 1) Input High Voltage V),, Max 0.5,4.5 - 5 3.5 3.5 : 3.5 Vv (Notes 2 and 6) (Note 1) 7 (Note 1) (Note 1) 1,9 - 10 7.0 7.0 - 7.0 1.5, 13.5 - 15 11 11 - 11 (Note 1) (Note 1) (Note 1) CD40109B Input Low Voltage, Vi, Max Vo Vec Vop (Note 2) 1,9 5 10 15 - 15 15 V (Note 1) (Note 1) (Note 1) 1.5, 13.5 10 15 3 - 3 3 Vv (Note 1) (Note 1) ff (Note 1) Input High Voltage, Vi, Max 1,9 5 10 3.5 3.5 - 3.5 Vv (Note 2) (Note 1) J (Note 1) (Note 1) 1.5, 13.5 10 15 7 7 - 7 Vv (Note 1) | (Note 1) (Note 1) 6-48CMOS Logic ICs - CD4000B Series Non-Standard DC Electrical Specifications B Series Devices (Continued) TEST CONDITIONS -55C +25C +125C MIN/ MIN/ PARAMETERS Vo Vin Vop MAX MIN MAX MAX UNITS CD40116 Quiescent Current (Note 3) Enable = 1 6.5 - 5 5 mA From Vop Supply lpp Max Enable = 0 (Note 1) (Note 1) J (Note 1) From Vcc Supply loc Max cc SUPPIY lec 65 : 5 5 mA (Note 1) (Note 1) | (Note 1) 100 - 100 200 pA (Note 1) (Note 1) J (Note 1) DATA FLOW - CMOS INPUTS TO TTL OUTPUTS Input Current, liq (Note 2) Vin = 0, 12V +60 - +60 +60 pA (Note 1) (Note 1) (Note 1) Output Current (Note 2) lon Min Von = 3V, Vit = 2V -7.5 6 - -4.2 mA (Note 1) ff (Note 1) (Note 1) lo. Min FVo_ = 0.4V, Viy = 10V 75 6 - 4.2 mA (Note 1) J (Note 1) (Note 1) TTL Three-State Leakage Current, Ioy7 Max J Enable = 0 +100 - +100 100 pA (Note 2) (Note 1) (Note 1) (Note 1) DATA FLOW - TTL INPUTS TO CMOS OUTPUTS Input Current (Note 2) I, Max =f Any TTL Input -600 - -500 -500 pA Vit = 0 to 0.7V (Note 1) (Note 1) (Note 1) Viq = 2.3V ly Max J -450 - -350 -350 pA (Note 1) (Note 1) (Note 1) Output Current (Note 2) lon Min PVoy = 11.5V, Vip = 0.7V -43 3.5 - -2.5 mA (Note 1) (Note 1) (Note 1) lo Min FVo, = 0.5V, Viq = 2.3V 43 3.5 - 2.5 mA (Note 1) (Note 1) (Note 1) CMOS Three-State Output Leakage Current I Vo = 0, 12V, Vix, = 0, SV +60 - +60 +60 pA (Note 2 and Note 8) ENABLE AND DISABLE INPUTS Input Current (Note 2) lit Vi_ = 0 to 0.7V -600 - -500 -500 pA (Note 1) (Note 1) (Note 1) lig Vin = 2.3V (TTL) -450 - -350 -350 pA (Note 1) (Note 1) J (Note 1) lin Vin = 12V (CMOS) 60 - 60 60 pA NOTES: 1. These limits are tested 100%. . Replaces a STD parameter. . An Additive parameter. . Input on terminals 1, 5, 8, 12, or 2, 6, 9, 13; other inputs to Vpp. . Input on terminals 1 and 2, 5 and 6, 8 and 9, or 12 and 13; other inputs to Vpp. . Measured with external pull-up resistor, Rp = 10kQ to Vop. . At-55C, test is performed with Vpp of 18V. on Oo & WwW P . CMOS Three-State output leakage test is functionally identical to CMOS-to-TTL input current tests. 6-49CMOS Logic ICs - CD4000B Series Switching Characteristics The table below lists all Harris High-Reliability CD4000B Series devices and shows which switching parameters are 100% tested at final electrical and Group A. In general, Harris tests propagation delay, transition time, and maximum Switching Characteristics at +25C clock frequency at 5V where applicable. Harris warrants all other switching parameters shown in the commercial data sheet. Harris High-Reliability switching tests are performed on a one-input to one-output basis only. MAX MAX CLK CLK (NOTE 1) PROP | TRANS | INPUT (NOTE 1) PROP | TRANS | INPUT CONDITIONS DELAY | TIME | FREQ CONDITIONS DELAY | TIME | FREQ TYPE Vop= 5V, C, = SOpF (ns) (ns) | (MHz) TYPE Vpp= 5V, C_ = SOpF (ns) (ns) | (MHz) CD4000B - 250 200 - CD4015B Clock to Q 320 200 3 CD4000UB - 120 200 - Reset to Q 400 - - (Note 2) CD4001B - 250 200 - CD4016B Sig. Input to Sig. 100 - - CD4001UB : 120 200 : Output CD4002B : 250 200 - Turn On 70 - - CD4002UB - 120 200 - CD4017B Clock to Out 650 200 2.5 CD4006B - 400 200 25 Clock to Carry Out 600 - - CD4007UB - 110 200 - Reset to Out 530 - - CD4008B Sum In to Sum Out 800 200 - CD4018B Clock to Q 400 200 3 Carry In to Sum Out 740 - - Preset/Reset to Q 550 - - Sum In to Carry Out 400 - - CD4019B - 300 200 - Carry In to Carry Out 200 - - CD4020B to Q1 360 200 3.5 CD4009UB - 140 350 - Qn to Qn + 1 330 - - (Note 1)#(Note 1) Reset to Q 280 : - - 60 70 - (Note 2) (Note 2)] (Note 2 CD4021B - 320 200 3 CD4010B - 200 350 - (Note 1)} (Note 1) CD4022B Clock to Carry Out 600 200 2.5 - 130 70 : Clock to Decode Out 650 - - (Note 2)] (Note 2) Reset to Output 530 - - CD4011B - 250 200 - CD4023B - 250 200 - CD4011UB - 120 200 - CD4024B oto Q1 360 200 3.5 CD4012B - 250 200 - Qn to Qn +1 330 - - CD4013B Clock to Q or 300 200 3.5 Reset to Q 280 - - Set to Q or Reset to 300 - - (Note 2) (Note 1) CD4025B8 - 250 200 - Set toGor ResettoQ | 400 : : (Note 2) CD4025UB - 120 200 - CD4014B8 - 320 200 3 6-50CMOS Logic ICs - CD4000B Series Switching Characteristics at +25C (Continued) MAX MAX CLK CLK (NOTE 1) PROP | TRANS J INPUT (NOTE 1) PROP | TRANS | INPUT CONDITIONS DELAY | TIME | FREQ CONDITIONS DELAY | TIME | FREQ TYPE Vpp= 5V, C, = 50pF (ns) {ns) | (MHz) TYPE Vop= 5V, C, = 50pF (ns) (ns) | (MHz) CD4027B Clock to Q or O 300 200 3.5 CD4040B $ to Q1 360 200 3.5 Set to Q or Reset 300 - - Qn to Qn + 1 330 - - toQ (Note 1) Reset to Q 280 - - Set to (or Reset 400 - - (Note 2) toQ (Note 2) CD4041UB - 120 80 - CD4028B - 350 200 - CD4042B Data In toQ 220 200 - CD4029B Q Output 500 200 2 Data In to 300 - - Carry Output 560 - - Clock to Q 450 - - Preset Enable to Q 470 - - Clock to Q 500 - - Preset Enable to 640 - - Carry Out CD4043B, Set or Reset to Q 300 200 - CD4044B Carry Input to Carry Out}, +9340 - - Enable to Q; tpyz, tpzy 230 : : CD4030B - 280 200 - Enable to Q; teyz, tpzi 180 - - CD4031B Clock to 500 200 2 CD4046B AC Coupled Signal In- 360mV Max put Voltage Sensitivity Clock toQ 500 - - (Peak to Peak) fy = (Note 1) 100Hz Sine Wave Clock to Q 380 - - CD4047B ta toa, a 1000 200 - (Note 2) Astable to Q, 700 - - Clock to Q' 380 - - Retrigger to Q,Q 600 : : Clock to Cip 200 - - Astable to Oscillator 400 - : CD4033B Clock to Carry Out 500 200 2.5 Reset to Q, 500 - - Clock to Decode Out 700 - - CD4048B Ka to Output 600 200 - Reset to Carry Out 550 - - (Note 1) CD4049UB : 120 160 - (Note 1)] (Note 1) Reset to Decode Out 600 - - - 65 60 - CD4034B Parallel In to Parallel 700 200 2 (Note 2) | (Note 2) Out CD4050B - 140 160 - AE to A Out terz, tpz_, | 400 - - (Note 1)} (Note 1) tenz: tpzH - 110 60 - CD4035B Clock to Q 500 200 2 (Note 2)] (Note 2) Reset to Q 460 - - CD4051B Add to Signa! Out 720 - - 6-51CMOS Logic ICs - CD4000B Series Switching Characteristics at +25C (Continued) MAX MAX CLK CLK (NOTE 1) PROP | TRANS | INPUT (NOTE 1) PROP | TRANS | INPUT CONDITIONS DELAY | TIME | FREQ CONDITIONS DELAY | TIME | FREQ TYPE Vpp= 5V, C, = 50pF (ns) (ns) | (MHz) TYPE Vpp= 5V, C, = 50pF (ns) (ns) | (MHz) CD4052B, Inhibit to Signal 720 - - CD4085B, Data 450 200 - CD4053B Out - Channel On CD4086B (Note 2) Inhibit to Signal 450 - - 620 - - Out - Channel Ott (Note 1 CD4054B Vee = -5V 800 200 - Inhibit 300 - - (Note 2) CD4056B Vee = -5V 1300 200 - 500 - - CD4060B Input Pulse Operation 740 200 3.5 (Note 1) gl to Q4 CD4089B Clock to Out 300 200 1.2 Qn to Qn + 1 200 - - Clear to Out 760 - - Reset Operation 360 - - (Note 2) Cascade to Out 180 - - CD4063B Comparator Input to 1250 200 - CD4093B - 380 200 - Output CD4094B Clock to Serial Out Qs 600 200 1.25 Cascade Input to 1000 - - Output Clock to Serial Out Q's 460 - - CD4066B Signal Input to Signal 40 - - Clock to Parallel Out 840 - - Output R, = 200k, Vo = Vpp; Vsg = GND, Strobe to Parallel Out 580 - - Vis = Square Wave = 5V and tp, te = 20ns Out Enable to Parallel 280 - - Out, tpyz. tpzH tpoc: tro tec = 20ns, 70 - - RAL = 1K and Vis <5V Out Enable to Parallel 200 - - CD4067B Add or inhibit to Signal | 650 - - Out, teiz, tez. Out Channel On CD4095B, Clock to Output 500 200 3.5 Signal In to Out 60 - - CD4096B Set or Reset 300 - - CD4068B - 300 200 - CD4097B Address or Inhibit to Sig} 650 - - CD4069UB - 110 200 - Out - Channel On CD4070B - 280 200 - Signal In to Out 60 - - CD4071B, - 250 200 - CD4098B Trigger to Q, O 500 200 - CD4072B, CD4073B, cD4089B Data to Output 400 200 - CD4075B CD4502B Data or Inhibit Delay 380 200 - CD4076B Clock to Q 600 200 - Time (Note 1)](Note 1) CD4077B - 280 200 - 270 120 - (Note 2) } (Note 2) CD4078B - 300 200 3 Disable Delay Time, 120 - - CD4081B, - 250 200 - tpyz CD4082B Disable Delay Time, 220 - - tezH 6-52CMOS Logic ICs - CD4000B Series Switching Characteristics at +25C (Continued) MAX MAX CLK CLK (NOTE 1) PROP | TRANS | INPUT (NOTE 1) PROP | TRANS | INPUT CONDITIONS DELAY | TIME | FREQ CONDITIONS DELAY | TIME | FREQ TYPE Vop= 5V, C, = S50pF (ns) (ns) | (MHz) TYPE Vpp= 5V, C, = 50pF (ns) (ns) | (MHz) CD4502B Disable Delay Time, 250 - - CD4511B Data to Output 1040 310 - (Continued) [tp_z, tez. (Note 2) ] (Note 2) CD4503B - 150 90 - - 1320 80 - (Note 1) (Note 1) (Note 1) (Note 1) - 110 70 - CD4512B Inhibit to Output 280 200 - (Note 2) | (Note 2) A Select to Output 400 - - tenz. tpzH 140 : : Data to Output 360 - - teiz. tpzi 180 - - teyz: tpzH 120 - - CD4504B SHIFT Voc] Vpp MODE CD4514B, Strobe or Data 970 200 - CD4515B TTLtoCMOS] 5 | 10] 280 - - Inhibit 500 - - Vop > Voc (Note 2) CD4516B Clock to Q Output 400 200 2 CMOS to 5 [10] 240 - - CMOS (Note 2) Preset or Reset to Q 420 : : Vpp > Veco Clock to Carry Out 480 - - CMOS to 10] 5 550 - - CMOS (Note 2) Carry In to Carry Out 250 - - Vec > Vop Preset or Reset to 640 - - TTLtoCMOS] 5 | 10] 280 - - Carry Out Vpp > Veco (Note 1) CD4517B Clock to Q16 400 200 3 CMOS to 5 [10] 240 - - CMOS (Note 1) CD4518B, Clock to Output 560 200 1.5 Vop > Veco CD4520B Reset to Output 650 : - CMOS to 107 5 400 : : (Note 2) CMOS Vec > Vop CD4527B Clock to Out 300 200 1.2 All Modes - | 5 200 - - Clear to Out 760 - - tHe trLH - | 10 100 - - Cascade to Out 180 - - CD4508B Strobe In to Data Out 260 200 - CD4532B E, to Eo, E, to Gs 220 200 - CD4510B Clock to Q Output 400 200 2 Dn to Qm 440 - - Preset or Reset to Q 420 - - Dn to Gs, E, to Qm 340 - - Clock to Carry Out 480 - - CD4536B Clock to Q1 8 Bypass 2000 200 0.5 High Carry In to Carry Out 250 - - Clock to Q1 8 Bypass 5000 - - Preset or Reset to 640 - : Low Carry Out Clock to Q16 8000 - - Reset to Qn 6000 - - (Note 2) 6-53CMOS Logic ICs - CD4000B Series Switching Characteristics at +25C (Continued) Data Out tezH MAX MAX CLK CLK (NOTE 1) PROP | TRANS | INPUT (NOTE 1) PROP | TRANS | INPUT CONDITIONS DELAY | TIME } FREQ CONDITIONS DELAY | TIME | FREQ TYPE Vpp= 5V,C, =50pF | (ns) | (ms) | (MHz) TYPE Vop= 5V,C_=50pF | (ns) | (ns) | (MHz) CD4541B [Clock to Q(28) 10500 | 200 | 0.75 CD40105B = JRipple Thru Delay 4000 : - (Note 2) (Continued) | Input to Out tp. 4 (Note 1) Clock to Q(2") 18000 | 360 - CD40106B - 280 200 - (Note 1) CD40107B Ry, = 120Q 200 100 - CD4555B, Select to Any Output 440 200 - CD4556B CD40108B = J Clock or Write 720 200 15 Enable to Any Output 400 - - Enable to Q CD4585B Comparator Inputs to 600 200 - Read or Write 600 . - Outputs Address to Q Cascade Inputs to 400 - - Disable Delay Time, 200 - - Outputs tezH, teHz CD4724B Data to Outputs 400 200 - Disable Delay Time, 260 - - tpzi, tpiz Write Disable to Output | 400 - - CD40109B DATA INPUT TO OUTPUT Reset to Output 350 - - (Note 2) SHIFT MODE VeclV; Address to Output 450 - - ceyep L-H 5V H10V} 600 100 - CD14538B [Trigger to, Q 600 200 - (Note 2) Reset to Q or O 500 - - L-H 5V Hiov] 260 . . D401008 - 720 | 200 | 1 (Note 1) H-L 10V [5V 500 200 - CD40101B = J Data In to Output 700 200 - (Note 2) Inhibit In to Output 280 - - H-L 10V 15V 460 . . CD40102B, [Clock to Output 600 | 200 | 07 (Note 1) CD40103B Carry In/Counter 400 : : THREE-STATE DISABLE DELAY R, = 1kQ Enable to Output SHIFT Asynchronous Preset | 1300 - - MODE [Vcc] Vpp Enable to Output (Note 1) teyz]| LH [5Vv Jovy 120 : - Clear to Output 750 - - (Note 2) tpyzy H-L J10VI5V 400 - - CD40104B = [Clock toQ 440 | 200 3 terz] LH j5V [10Vy 740 tezu: tpuz, tezi 160 - - tp_z] H-L J10VI5V 500 - - tpuz 90 . . tpzy] L-H [5V iOVE 640 - - CD40105B [Shift Out or Reset to 370 | 200 | 15 tpzu} H-L pIovisv | 600 - Data Out Ready (Note 2) tex.| L-H [sv [tov] 200 " . Shift In to Data In Ready (Note 2) - - ter) H-L |tov|5v 400 " Three-State Control to 280 - - 6-54CMOS Logic ICs - CD4000B Series Switching Characteristics at +25C (Continued) MAX MAX CLK CLK (NOTE 1) PROP | TRANS | INPUT (NOTE 1) PROP | TRANS | INPUT CONDITIONS DELAY | TIME | FREQ CONDITIONS DELAY | TIME | FREQ TYPE Vpp= 5V, C, = 50pF (ns) (ns) | (MHz) TYPE Vpp= 5V, C,_ = 50pF (ns) (ns) | (MHz) CD40116 Data In to Data Out, 35 40 - C040192B, [Clock UporClock Down] 500 200 2 CMOS In, TTL Out CD40193B_s [to Q,, Reset Q Data In to Data Out, 45 - - PE toQ 400 - - TTL In, CMOS Out Clock Up to Carry, Clock} +320 - - Disable to TTL Out, 45 - - Down to Borrow toyz: teiz Reset or PE to Borrow 600 - - Disable to TTL Out, 50 - - or Carry tezH: tpze CD40194B Clock to Q 440 200 3 Enable to CMOS Out, 30 - - teyz:, teiz Reset to Q 460 - - (Note 2) Enable to CMOS Out, 60 - - tpzH, tpzi CD40257B sf Data input to Output 300 200 - CD40160B, [Clock toQ 400 200 2 Select to Output 380 - - CD40161B, CD40163B = [Clock to Coyr 450 - - Output Disable to - - - Output Te to Cout 250 - - tezH: tpHz 190 - - Clear to Q (CD40160B 500 - - and CD40161B Only) (Note 2) tezL. teLz 190 - - CD40174B = [Clock to Output 300 200 3.5 NOTES: Clear to Output 200 - - 1 TH OF PL (Note 2) 2. try OF teHe 6-55CMOS Logic ICs - CD4000B Series Gate Count TYPE NUMBER GATE COUNT TYPE NUMBER GATE COUNT TYPE NUMBER GATE COUNT CD4000B 12 CD4044B 23 CD4510B 65 CD4000UB 4 CD4046B 35 CD4511B 55 CD4001B 10 CD4047B 46 CD4512B 20 CD4001UB 4 CD40488 28 CD4514B 59 CD4002B 9 CD4049UB 3 CD4515B 67 CD4002UB 4 CD40508 6 CD4516B 58 CD4006B 83 CD4051B 58 CD4517B 280 CD4007UB 2 CD4052B 40 CD4518B 72 CD4008B 34 CD4053B 46 CD4520B 71 CD4009UB 8 CD4054B 28 CD4527B 63 CD4010B 8 CD4056B 70 CD4532B 28 CD4011B 10 CD4060B 83 CD4536B 195 CD4011UB 4 CD4063B 56 CD4541B 119 CD4012B 9 CD4066B 9 CD4555B8 21 CD4013B 20 CD4067B 75 CD4556B 25 CD4014B 57 CD4068B 11 CD4585B 40 CD40158 54 CD4069UB 3 CD47248 62 CD4016B 6 CD4070B 11 CD14538B 58 CD4017B 50 CD4071B 12 CD40100B 173 CD40188 40 CD4072B 1 CD40101B 27 CD4019B 10 CD4073B 12 CD40102B 141 CD4020B 85 CD4075B 12 CD40103B 139 CD4021B 57 CD4076B 54 CD40104B 52 CD4022B 40 C04077B 11 CD40105B 242 CD4023B 1 CD4078B 11 CD40106B 18 CD4023UB 5 CD4081B 12 CD40107B 4 CD4024B 45 CD4082B 11 CD40108B 137 CD4025B 11 CD40858 10 CD40109B 72 CD4025UB 5 CD4086B 9 CD40116 76 CD4027B 25 CD4089B 67 CD40160B 66 CD4028B 26 CD4093B 14 CD40161B 66 CD4029B 64 CD40948 88 CD40163B 66 CD4030B 11 CD4095B 19 CD40174B 37 CD4031B 271 CD4096B 19 CD40175B 28 CD4033B 72 CD4097B 74 CD40192B 80 CD4034B 106 CD4098B 37 CD40193B 87 CD4035B 45 CD4099B 62 CD40194B 52 CD4040B 75 CD4502B 26 CD40257B 35 CD4041UB 8 CD4503B 17 NOTE: CD4042B 16 CD4504B 20 1. Gate Count is based on four transistors per gate rounded off to nearest CD4043B 23 CD4508B 48 nondecimal integer. 6-56CMOS Logic ICs - CD4000B Series Static Life Test and Burn-in Test Circuit Connections (Note 1 and Note 2) STATIC BURN-IN STATIC BURN-IN TYPE OPEN GND Vpo TYPE OPEN GND Vop cp4000-=s i, 2, 6, 9, 10 7 3-5, 8, 11-14 CD4041 1, 2, 4, 5, 8, 9, 7 3, 6, 10, 13, 14 11, 12 cp4001_ 4/3, 4, 10, 11 7 1, 2,5, 6, 8, 9, 12-14 cp4042 41-3, 9-12, 15 8 4-7, 13, 14, 16 cp4002.s44, 6, 8, 13 7 2-5, 9-12, 14 cp4043 sit, 2, 9, 10, 13 8 3-7, 11, 12, 14-16 cp4006 = 2, 8-13 7 1, 3-6, 14 cp4044s it, 2, 9, 10, 13 8 3-7, 11, 12, 14-16 cp4007.s44, 5, 8, 12, 13 4,7,9 |2,3,6,10, 11, 14 cp4046 = 1, 2, 4, 6, 7, 10, 8 3, 5, 9, 12, 14, 16 cD4008 410-14 8 1-7, 9, 15, 16 11, 13, 15 CD4009 2, 4, 6, 10, 12, 8 1 (Note 4), 3, 5, 7, 9, CD4047 1,2, 10,11, 13 7 3-6, 8, 9, 12, 14 (Note 3) 13, 15 11, 14, 16 (Note 4) cp4o48 si 8 2-7, 9-16 CD4010 = 2, 4, 6, 10, 12, 8 1 (Note 4), 3, 5, 7, 9, (Note 3) 113, 15 11, 14, 16 (Note 4) cD4049 42-4, 6, 10, 12, 8 1 (Note 4), 3, 5, 7, 9, (Note 3) (13, 15 11, 14, 16 (Note 4) CD4011 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9, 12-14 CD4050 2, 4, 6, 10, 12, 8 1 (Note 4), 3, 5, 7, 9, cp40i2 1, 6,8, 13 7 = (42-5, 9-12, 14 (Note 3) 113, 15 11, 14, 16 (Note 4) CD4013 1,2, 12,13 7 3-6, 8-11, 14 CD4051 3 7 (Note 4), | 1, 2, 4-6, 9-16 Note 3 8 (Note 4 cp4014 =: 2, 3, 12 8 1, 4-7, 9-11, 13-16 ( ) ( cp4052 3, 13 7 (Note 4), | 1, 2, 4-6, 9-12, 14-16 CD4015 2-5, 10-13 8 1, 6, 7, 9, 14-16 (Note 3) 8 (Note 4) CD4016 = 2, 3, 9, 10 7 1, 4-6, 8, 11-14 cp4053.s 4, 14, 15 7 (Note 4), | 1-3, 5, 6, 9-13, 16 cp4017 1-7, 9-12 8,14 113, 15, 16 (Note 3) 8 (Note 4) cp4oig (4-6, 11, 13 8 |1-3,7, 9, 10, 12, fe TINoKe 4), J 2, 9-18 14-16 (Note 3) cpaoia Vio13 3 17,9, 1416 cb4056 9-15 7 (Note 4), 1-6, 16 (Note 3) 8 CD4020 (1-7, 9, 12-15 8 10, 11, 16 cpaoe0 417.9, 10. 3 112,16 cp4021 2,3, 12 8 1, 4-7, 9-11, 13-16 13-15 cD4022 1-7, 9-12 8,14 13, 15, 16 CD4063 5-7 3,8 71,2, 4,9-16 cb4023 6, 9, 10 7 1-5, 8, 11-14 CD4066 2,3, 9, 10 7 1, 4-6, 8, 11-14 CD4024 (3-6, 8-13 7 44,2, 14 cD4067 1 120 211, 13-23 CD4025 6,9, 10 7 1-5, 8, 11-14 CD4068 1,6, 8,13 7 2-5, 9-12, 14 Cb4027. 11,2, 14,15 8 3-7, 9-13, 16 cp4c69 = 2, 4, 6, 8, 10, 12 7 1, 3,5, 9, 11, 13, 14 CD4028 1-7, 9, 14, 15 8 10-13, 16 CD4070 3, 4, 10, 11 7 1,2, 5, 6, 8, 9, 12-14 cp4029. I2,6.7, 11.14 8 1, 3-5, 9,10, 12, cp4071 3, 4, 10, 11 7 1, 2,5, 6, 8, 9, 12-14 13, 15, 16 cp4072 4,6, 8, 13 7 2-5, 9-12, 14 CD4030 =43, 4, 10, 11 7 1, 2,5, 6, 8, 9, 12-14 cpaova leo 10 7 18 ida CD4031 3-7, 9, 11-14 8 1, 2, 10, 15, 16 cpao7s Ne310 TSB 1il4 cp4033 4-7, 9-13 8 1-3, 14-16 re 3 127 916 Cp4034 18 2 pstt. 13-24 cp4077_ 3, 4, 10, 11 7 11,2,5,6,8,9, 12-14 CD4035 ft, 13-15 8 | 2-7, 9-12, 16 cb4078 11,6, 8, 13 7 |2-5,9-12, 14 cb4040 1-7, 9, 12-15 8 10, 11, 16 6-57CMOS Logic ICs - CD4000B Series Static Life Test and Burn-In Test Circuit Connections (Continued) STATIC BURN-IN STATIC BURN-IN TYPE OPEN GND Vop TYPE OPEN GND Vop CD4081 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9, 12-14 CD4585 3, 12,13 8 1, 2, 4-7, 9-11, 14-16 cD4082 1, 6, 8, 13 7 2-5, 9-12, 14 CD4724 4-7, 9-12 8 1, 3, 13-16 CD4085 3,4 7 1, 2, 5, 6, 8-14 CD14538 92,6, 7,9,10,14]7 1,8,15 [3-5, 11-13, 16 CD4086 3,4 7 1, 2, 5, 6, 8-14 CD40100 1, 4, 5, 7, 10, 8 2,3, 6,9, 11, 13, 16 12, 14, 15 CcD4089 1, 5-7 8 2-4, 9-16 CD40101 6,9 7 1-5, 8, 10-14 CD4093 3, 4, 10, 11 7 1, 2, 5, 6, 8, 9, 12-14 CD40102 14 8 1-7, 9-13, 15, 16 CD4094 4-7, 9-14 8 1-3, 15, 16 CD40103 14 8 1-7, 9-13, 15, 16 CD4095 1,6,8 7 2-5, 9-14 CD40104 12-15 8 1-7, 9-11, 16 CD4096 1,6,8 7 2-5, 9-14 CD40105 ff2, 10-14 8 1, 3-7, 9, 15, 16 CD4097 1,17 12 2-11, 13-24 CD40106 2, 4, 6, 8, 10, 12 7 1, 3, 5,9, 11, 13, 14 CD4098 2,6,7,9,10,14]7 1,8,15 [3-5, 11-13, 16 CD40107 1, 2, 5, 6, 8, 9, 7 3, 4, 10, 11, 14 CD4099 1, 9-15 8 2-7, 16 12,13 CD4502 72, 5, 7, 9, 11, 14 8 1, 3, 4, 6, 10, 12, 13, Cb40108 41, 2, 4-7, 22, 23 12 3, 8-11, 13-21, 24 15, 16 CD40109 4,5, 11-13 8 16, (1 [Note 4], 2,3, 6, CD4503 3,5, 7,9, 11, 13 8 1, 2, 4, 6, 10, 12, (Note 3) 7,9, 10, 14, 15), 14-16 Note 5 CD4504 2, 4, 6, 10, 12, 8 16, (1 [Note 4], 3, 5, 7, CD40116 92-9 11,12 1 (Note 4) 15 9, 11, 13, 14), Note 5 (Note 3) 10 = Vpp (Note 6) cp4508 5,7, 9, 11, 17, 12 11-4, 6,8, 10, 13-16, 13-22 (Note 4) = Voc 19, 21, 23 18, 20, 22, 24 CD40160 911-15 8 1-7, 9, 10, 16 CD4510 2,6, 7, 11, 14 8 1, 3-5, 9, 10, 12, 13, CD40161 11-15 8 1-7, 9, 10, 16 15, 16 CD40163 11-15 8 1-7, 9, 10, 16 CD4511 9-15 8 1-7, 16 CD40174 =f2, 5, 7, 10, 12, 8 1,3, 4, 6, 9, 11, 13, CD4512 14 8 1-7, 9-13, 15, 16 15 14, 16 CD4514 4-11, 13-20 12 1-3, 21-24 CD40175 2, 3, 6, 7, 10, 8 1, 4, 5, 9, 12, 13, 16 41, 14,1 CD4515 4-11, 13-20 12 1-3, 21-24 s 4 2,3, 6, 7,12, 1 8 1, 4, 5, 9-11, 14-16 CD4516 2,6, 7,11, 14 8 1, 3-5, 9, 10, 12, 13, C40193 3,6 8 15, 16 CD40194 912-15 8 1-7, 9-11, 16 CD4517 1, 2, 5, 6, 10, 8 3, 4,7, 9, 12, 13, 16 CD40257 9/4, 7,9, 12 8,15 | 1-3, 5, 6, 10, 11, 13, 11, 14, 15 14, 16 CD4518 3-6, 11-14 8 1, 2,7, 9, 10, 15, 16 NOTES: CD4520 3-6, 11-14 8 1, 2, 7,9, 10, 15, 16 1. For Type A devices, use Vop = 12.5V. For Type Band UB devices, use Vpp = 18V. CD4527 1, 5-7 8 2-4, 9-16 2. Each pin except Vpp and Vgg must have resistors of 2kQ to 47kQ. In most cases, Vgzg is at pin 7 (of a 14 pin IC), CD4532 6,7, 9, 14, 15 8 1-5, 10-13, 16 pin 8 (of a 16 pin IC) or pin 12 (of a 24 pin IC), while Vop is CD4536 4,5, 13 8 1-3, 6, 7, 9-12, 14-16 at the highest numbered pin; exceptions are noted. 3. Non-standard pin arrangement, or multiple supply pins. cD4541 1,2, 4,8, 11 7 3, 5, 6, 9, 10, 12-14 4. Connect pin(s) without using resistor. CD4555 4-7, 9-12 8 1-3, 13-16 5. Pin voltage is Vop/2 for pins inside parentheses. 6. Vpp = 11.5V; Voc = 6.5V; use 3000 resistors at pins 10, 13-21. CD4556 4-7, 9-12 8 1-3, 13-16 6-58MIL-STD-883, Notice 5 GROUP A ELECTRICAL TESTS FOR CLASS B (JAN) DEVICES (NOTE 1) Quality Assurance and Reliability 5. If any device in the sample fails any parameter in the test, sub- group, or set of tests/subgroups being sampled, each and every additional device in the (sub)lot represented by the sample shalt be tested on the same test setup for all parameters in that test, subgroup, or set of tests/subgroups for which the sample was se- lected, and all failed devices shall be removed from the (sub)lot for final acceptance of that test, subgroup, or set of tasts/ subgroups. as applicable. For class S only, if this testing results in a percent defective greater than 5%, the (sub)lot shail be rejected, except that for (sub)lot previously unscreened to the tests that caused failure of this percent defective, the (sub)lot may be accepted by resubmission and passing the failed individual tests, subgroups, or set of test/subgroups, as applicable, using a 116/0 sample. Electrical Test Requirements for Non-JAN Lot Conformance Tests GROUP A ELECTRICAL TESTS FOR HARRIS 3, 3A AND SMD PRODUCT SUBGROUPS (NOTE 2) QUALITY/ACCEPT NO. = 116/0 (NOTES 3, 4 AND 5) Subgroup 1 DC Test at +25C Subgroup 2 DC Tests at Maximum Rated Operating Temperature Subgroup 3 DC Tests at Minimum Rated Operating Temperature Subgroup 4 AC Tests at +25C Subgroup 5 AC Tests at Maximum Rated Operating Temperature Subgroup 6 AC Tests at Minimum Rated Operating Temperature Subgroup 7 Functional Tests at +25C Subgroup 8A Functional Tests at Maximum Rated Operating Temperature Subgroup 8B Functional Tests at Minimum Rated Operating Temperature Subgroup 9 Switching Tests at +25C SUB GROUPS WHERE USED Subgroup 1.......... 0.0.00. e eee All Types When Required DC Tests at +25C Subgroup 2..............-.-000e- All Types When Required DC Tests at Maximum Rated Operating Temperature Subgroup 3.................--200- All Types When Required DC Tests at Minimum Rated Operating Temperature Subgroup 10 Switching Tests at Maximum Rated Operating Temperature Subgroup 7.............-...0-00- All Types When Required Functional Tests at +25C Subgroup 11 Switching Tests at Minimum Rated Operating Temperature Subgroup 8A................0000- All Types When Required Functional Tests at Maximum Rated Operating Temperatures NOTES: (Group A) 1. The specific parameters to be included for tests in each subgroup shall be as specified in the applicable acquisition document. Where no parameters have been identified in a particular sub- group or test within a subgroup, no group A testing is required for that subgroup or test to satisfy group A requirements. 2. At the manufacturer's option, the applicable test required for group A testing (see Note 1) may be conducted individually or combined into sets of tests, subgroups (as defined in the Group A Electrical Tests Table), or sets of subgroups. However, the manufacturer shall predesignate these groupings prior to group- ing a testing. Unless otherwise specified, the individual tests, subgroups, or sets of test/subgroups may be performed in any sequence. 3. The sample plan (quantity and accept number) for each test, sub- group, or set of tests/subgroups as predesignated in Note 2 above, shall be 116/0. 4. Agreater sample size may be used at the manufacturer's option; however, the accept number shall remain at zero. When the (sub)lot size is less than the required sample size, each and ev- ery device in the (sub)lot shall be inspected and all failed devices removed from the (sub)iot for final acceptance of that test, sub- group, or set of tests/subgroups, as applicable. Subgroup 8B.................0 0 ee All Types When Required Functional Test at Minimum Rated Operating Temperatures Subgroup 9................00. Digital Types When Required Switching Tests at +25C CD4000 3, 3A AND SMD SUBGROUPS (PER METHOD 5005, GROUP A MIL-STD-883 ELECTRICAL TEST REQUIREMENTS TESTS TABLE) Group A Test Requirements 1,2,3,7,8,9 (Method 5005) Groups B and C End-Point Electrical 1,2,3,7,8 Parameter (Method 5005) (Class S and B) Groups D End-Point Electrical 1,2,3 Parameters (Method 5005) 6-59Quality Assurance and Reliability Life Test Reliability Data Reliability can be defined as the probability of a device per- forming a function, under specific conditions for which designed, for a specific period of time. But because of the higher reliability levels required in today's integrated circuits, the extended time and high cost required to measure their reliability at application stress levels become prohibitive. A practical method of meeting these concerns is through the use of accelerated life testing, a method by which devices are operated at, or subjected to, higher stress levels than they normally experience in a typical application. Life tests are generally performed at elevated temperatures and maximum recommended operating voltage in order to accelerate time-dependent failure mechanisms related to conditions of temperature and electrical stress. Life testing is the principal method used in predicting the failure rates of components in actual field applications. Activation Energy The activation energy is defined as the minimum kinetic energy a molecule or atom in the initial state of a process must acquire before it can take part in a reaction. Failure mechanisms can differ markedly in terms of their reaction rates. A low activation energy implies that the reaction rate (failure rate) will not be accelerated as much by temperature as will a reaction with a high activation energy. The acceleration factor used in predicting the failure rate from the life test condition depends directly on the activation The activation energy estimates reported in the semiconduc- tor industry, as obtained from integrated circuit life test evalu- ations, fall in the range of approximately 0.3eV to 1.4eV. However, a value of 1.0eV has been shown to be fairly repre- sentative. This value has been demonstrated on Harris Logic CMOS integrated circuits using relatively large sample quan- tities and is the value used in Calculating Life Test Tempera- ture Acceleration Factors. Temperature Acceleration Factor A variety of failure mechanisms can be accelerated by life testing. The reaction rates of most of these mechanisms are highly dependent of temperature and are best expressed by the Arrhenius model: R(T) = A exp (-E/kT) where, R(T) = Reaction Rate A = Constant k = Boltzmann's Constant (8.63 x 10-5eV/K) E = Activation Energy (eV) T = Absolute Temperature (C +273) For electronic components, the reaction rate refers to the fail- ure rate. The acceleration factor, which relates the test failure rate to the end-use failure rate, can be determined from the Arrhenius equation for any activation energy, as follows: ao wfiet-y)| energy. use TEST Reliability Data FAILURE RATE AT 60% U.C.L. EQUIV. PRODUCT QUANTITY 1 ACTUAL TEST | TEST NO. DEVICE %/1000 HRS FITS CLASSIFICATION | TESTED | DEVICE HRS| TEMP. | VOLTS | REJECTS | HRS AT +55C AT+55C = |. AT +55C CD4000B-JAN B 4326 2,180,304 135 18 12 2.2 X 10 6.1X 104 6.1 CD4000A-JAN B 4209 2,121,336 135 12.5 14 2.2 X 109 7.2X 1074 7.2 CD4000B 3A 539 539,000 125 18 4) 1.1X 109 3.6 X 104 3.6 722 861,000 135 18 3 1.1X 109 3.6 X 104 3.6 CD4000B 3 4280 4,280,000 125 18 0 5.7 X 109 1.1X 104 11 7060 3,530,000 135 18 5 5.7 X 10 1.1xX 104 11 CD4000A 3 2387 2,387,000 125 12.5 0 4.2 X 109 0.73 X 104 0.7 5920 2,960,000 135 12.5 2 4.2 X 109 0.73 X 1074 0.7 6-60