FUJITSU MICROELECTRONICS Ve DER 3749?be 00043597 1 T-4 oT FUJITSU Aprit 1986 Edition 4.0 BIPOLAR CLOCK GENERATOR AND DRIVER FOR MBL 8086/8088/8089 @ Generates the System Clock for the @ Generates System Reset Output from MBL 8086/8088/8089 Schmitt Trigger Input Processors: Capable of Clock Synchronization with 5MHz and 8MHz with MBL 8284A @ Capable of Clock synchronization wi 10MHz with MBL 8284A-1 Other MBL 8284As Uses a Crystal or a TTL Signal for @ Single +5V Power Supply Frequency Source 18-Pin Cerdip (Suffix: -CZ) @ Provides Local READY and Multibus* READY Synchronization Fig.1 BLOCK DIAGRAM Fig. 2 PIN CONFIGURATION ~ RES TT D L G} RESET cKi x1 OSCILLATOR x2 | > osc csYNcC1 180 Vee F/C-_4 PCLK]2 1700x1 300 Ty 2 Pe PCLK AENICN3 jet x2 EFI sYNC_ f as Rovif|4 MBL 15(7 ASYNC csyne | READYCIS 14 er RDY2C16 13D F/C ROY1I AEN2 (7 127.) 0s _ pe cLKC}8 v1) RES AEN! cnoo 10 RESET RDY2 CKt Kt | AEN? D a |= READY FFI FF2 ASYNG *Trade Mark of Intel Corporation Portions Reprinted by permission of Intel Corporation Intel Corporation, 1983 4 AnnFUJITSU MICROELECTRONICS 97 DE) 37497b2 oOO4aNA 3 i PUNE | T-49-17-07 FUJITSU MBL 8284A HET MBL 8284A-1 PIN DESCRIPTION TABLE 1 PIN DISCRIPTION Symbol Type Name and Function . AEN1, i Address Enable: AEN is an active LOW signal, AEN serves to qualify its respective Bus Ready AEN2 Signal (RDY1 or RDY2}, AEN validates RDY1 while AEN? validates RDY2, Two AEN signal inputs are useful in system configurations which permit the processor to access two Multi-Master System Busses, In non Multi-Master configurations the AEN signal inputs are tied _true (LOW). RDY1, I Bus Ready: (Transfer Complete), RDY is an active HIGH signal which is an indication from RDY2 a device located on the system data bus that data has been received, or is available. RDY1 is qualified by AENT while RDY2 is quatified by AEN2. ASYNC t Ready Synchronization Select: ASYNC is an input which defines the synchronization mode of the READY fogic, When ASYNC is tow, two stages of READY synchronization are provided. When ASYNC is left open (internal pull-up resistor is provided,) or HIGH a single stage of READY synchronization is provided. READY oO Ready: READY is an active HIGH signal which Is the synchronized RDY signal input, READY is cleared after the guaranteed hold time to the. processor has been met. X11, X2 I Crystal In: X14 and X2 are the pins to which a crystal is attached. The crystal frequency is 3 times the desired processor clock frequency. F/C i Frequency/Crystal Select: F/C is a strapping option, When strapped LOW, F/T permits the processor's clock to be generated by the crystal. When F/C is strapped HIGH, CLK is generated from the EFI input. EFI I External Frequency: When F/T is strapped HIGH, CLK Is generated from the input frequency appearing on this pin, The input signal is a square wave 3 times the frequency of the desired CLK output, CLK oO Processor Clock: CLK is the clock output used by the processor and all devices which directly connect to the processor's local bus (i,e., the bipolar support chips and other MOS devices), CLK has an output frequency which is 1/3 of the crystal or EFI input frequency and a 1/3 duty cycle, An output HIGH of 4.5 volts (Voc = 5V} is provided on this pin to drive MOS devices, PCLK oO Peripheral Clock: PCLK is a TTL level peripheral clock signal whose output frequency is 1/2 that of CLK and has a 50% duty cycle. osc Oo Oscillator Output: OSC is the TTL level output of the internal oscillator circuitry, its frequency is equal to that of the erystal. : RES I Reset tn: RES is an active LOW signal which is used to generate RESET, The MBL 82844 provides a Schmitt trigger input so that an RC connection can be used to establish the power- up reset of proper duration, RESET oO Reset: RESET is an active HIGH signal which is used to reset the MBL 8086 family pro- cessors, its timing characteristics are determined by RES. CSYNC ! Clock Synchronization: CSYNC is an active HIGH signal which allows multiple MBL 82844 to be synchronized to provide clocks that are in phase. When CSYNG is HIGH the internal counters are reset, When CSYNC goes LOW the internal counters are allowed to resume count- ing, CSYNC needs to be externally synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to ground, GND Ground. Vee Power: +5V supply.FUJITSU MICROELECTRONICS 497 a 3749?be OO043599 5 Ll. FUNCTIONAL DESCRIPTION GENERAL The MBL 8284<A is a single chip clock generator/driver for the MBL 8086/MBL 8088/MBL 8089 processors. The chip contains a crystal-controiled oscillator, a divide- by-three counter, complete MULTIBUS* Ready syn- chronization and reset logic. Refer to Figure 71 for Block Diagram and Figure 2 for Pin Configuration. OSCILLATOR The oscillator circuit of the MBL 8284A is designed Primarily for use with an external series resonant, funda- mental mode, crystal. from which the basic operating fre- quency is derived, The crystal frequency should be selected at three times the required CPU clock. X1 and X2 are the two crystal input crystal connections, For the most stable operation of the oscillator (OSC) output circuit, two series resistors (Ry = Rz = 5102) as shown in the waveform figures are recommended, The output of the ascilfator is buffered and brought out on OSC so that other system timing signals can be derived from this stable, crystal-controlled source, For systems which have a Voc ramp time = 1V/ms and/or have inherent board capacitance between X14 or X2, ex- ceeding 10pF (not including MBL 8284A pin capacitance), the two 5100 resistors should be used. This circuit provides optimum stability for the oscillator in such extreme conditions. It is advisable to limit stray capaci- tances to less than 10pF on X1 and X2 to minimize deviation from operating at the fundamental frequency. For notes of using MBL 82844, see page 10. CLOCK GENERATOR The clock generator consists of a synchronous divide- by-three counter with a special clear input that inhibits the counting. This clear input (CSYNC) allows the out- put clock to be synchronized with an external event {such as another MBL 8284A clock). It is necessary to synchronize the CSYNC input to the EFI clock external to the MBL 8284A. This is accomplished with two Schot- tky flip-flops. The counter output is a 33% duty cycte clock at one-third the input frequency. The F/C input is a strapping pin that selects either the crystal oscillator or the EFI input as the clock for the +3 counter. If the EFI input is selected as the clock source, the oscillator section can be used independently for another clock source, Output is taken from OSC, CLOCK OUTPUTS The CLK output is a 33% duty cycle MOS clock driver designed to drive the MBL 8086/MBL 8088/MBL 8089 Processors directly. PCLK is a TTL tevel peripheral er | MBL 8284A FUJITSI MBL 8284A-1 [2 )q0 T-49-17~-07 clock signal whose output frequency is % that of CLK, PCLK has a 50% duty cycle. RESET LOGIC The reset logic provides a Schmitt trigger input (RES) and a synchronizing flip-flop to generate the reset timing. The reset signal is synchronized to the falling edge of CLK, A simple RC network can be used to provide power-on reset by utilizing this function of the MBL 8284A. READY SYNCHRONIZATION Two READY inputs (RDY1, RDY2) are provided to ac- commodate two Multi-Master ter system busses, Each input has a quatifier (AEN1 and AEN2Z, respectively). The AEN signats validate their respective ROY signals, If a Multi- Master systm is not being used the AEN pin should be tied LOW. Synchronization is required for all asynchronous active- going edges of either RDY input to guarantee that the RDY setup and hold times are met. Inactive-going edges of RDY in normally ready systems do not require syn- chrenization but must satisfy RDY setup and hold as a matter of proper system design. The ASYNC input defines two modes of READY syn- chronization operation, When ASYNC is LOW, two stages of synchronization are provided for active READY input signals. Positive-going asynchronous READY inputs will first be synchronized to flip-flop one at the rising edge of CLK and then syn- chronized to flip-flop two at the next falling edge of CLK, after which time the READY output will go active (HIGH). Negative-going asynchronous READY inputs will be synchronized directly to flip-flop two at the fal- ling edge of CLK, after which time the READY output will go inactive, This mode of operation is intended for use by asynchronous (normally not ready) devices in the system which cannot be guaranteed by design to meet the required RDY setup timing, tayyvc_, on each bus cycle. When ASYNC is high or left open, the first READY flip- flop is bypassed in the READY synchronization logic. READY inputs are synchronized by flip-flop two on the falling edge of CLK before they are presented to the Processor, This mode is available for synchronous devices that can be guaranteed to meet the required RDY setup time. ASYNC can be changed on every bus cycle to select the appropriate mode of synchronization for each device in the system.RESET FUJITSU MBL 8284A EOC FUJITSU MICROELECTRONICS 97 dE} azua7ee oooy4oo a al all i al MBL 8284A-1 T+49-17-07 Fig. 3 CSYNC SYNCHRONIZATION SYNCHRONIZE> D a D a EFI>e_PSo BCLKt Lot w- (TO OTHER MBL 8284As) ABSOLUTE MAXIMUM RATINGS* *NOTE: Permanent device damage may occur if ABSO- LUTE MAXIMUM RATINGS are exceeded. Temperature Under Bias .......... ..,0Cto 70C Functional operation should be restricted to the Storage Temperature ........ 0.005 ~65C to +150C conditions as detailed in the operational sections Supply Voltages... 0.0.0.0. 04a ee -0.5V to +7.0V of this data sheet, Exposure to absolute maxt- Ail Input and Output Voltages......... -0.5V to Veg mum rating conditions for extended periods may Power Dissipation. ............ Vee eu eece 1.0W affect device reliability, D.C. CHARACTERISTICS (Vcc = 5Vt10%, Tp = 0C to 70C) Symbol Parameter Min. Max. Units Test Conditions . ASYNC -1.3 mA Ve = 0.45V \- Forward Input Current Other Inputs 05 mA Vp = 0.45V ASYNG 50 HA Va =Vee lp Reverse Input Current Other Inputs 50 LA Va =5.26V Ve Input Forward Clamp Voltage -1.0 Vv Ig =-5mMA lec Power Supply Current 162 mA Vie Input LOW Voltage 0.8 Vv Vin Input HIGH Voltage 2.0 Vv Vinr Reset Input HIGH Voltage 2.6 Vv VoL Output LOW Voltage 0.45 Vv lo. =SmA CLK 4 Vv low =-1mMA Vou Output HIGH Voltage loner ueputs! 2.4 v lon =-tmA VinrVitr RES Input Hysteresis 0,25 V 1-303 iEFUJITSU MICROELECTRONICS 97 DE) 37497K2 oooy4o1 o ff eT MBL 8284A) 38 FUJITSU MBL 8284A0-1 BZGHu T-49-17-07 A.C. CHARACTERISTICS (Vcc = 5V110%, Ta = 0C to 70C) TIMING REQUIREMENTS Symbo! Parameter Min, Mex. Units Test Conditions tenee External Frequency HIGH Time 13 ns (90% - 90%) V,,, teLen External Frequency LOW Time 13 ns {10% ~ 10%) Vi, Tevet EFI Period (Note 1) 2 ns Foe aa ee XTAL Frequency 12 mB MHz ror ue a triver RDY1, RDY2 Active Setup to CLK 35 ns ASYNC = HIGH trivon RDY1, RDY2 Active Setup to CLK 35 ns ASYNC = LOW trivee RDY1, RDY2 Inactive Setup to CLK 35 ns teLRix RDY1, RDY2 Hold to CLK 0 ns tayvet ASYNC Setup to CLK 50 ns tocave ASYNC Hold to CLK 0 ns taivaiv | AEN, AEN2 Setup to RDY1, RDY2 15 ns teLaix AENT, AEN2 Hold to CLK 0 ns tyHEeH CSYNC Setup to EFI 20 ns teHvLe CSYNC Hold to EFI 10 ns tyHvL CSYNC Width 2" teLeL ns truer RES Setup to CLK 65 | ns {Note 1) totum | RES Hold to CLK 20 ns (Note 1)FUJITSU MICROELECTRONICS 497 DE 349 ?be OOO44Oe 1 , PECL T-49-17-07 FUJITSU MBL 8284A KE MBL 8284A-1 A.C. CHARACTERISTICS (Continued) TIMING RESPONSES Symbol Parameter MBr EZ84A MBL 8264A-1 Max. [| Units | Test Conditions teLcL CLK Cycle Period 125 100 ns teneL CLK HIGH Time (Ys tereL)+2 39 ns teen CLK LOW Time (7% tereL)-15 53 ns tenicH2 | CLK Rise Time 10 ns | From 1.0V to 3.5V tecocr2 | CLK Fall time 10 | ns | From3.5V to 1.0V | - tue. | PCLK HIGH Time tere. -20 tere -20 ns tpLey PCLK LOW Time tetcL-20 tetcL-20 ns tryicL Ready Inactive to CLK ~3 -8 ns_ | (Note 3) tavucy | Ready Active to CLK (74 teteL)-15 53 ns | (Note 2) teLiL CLK to Reset Dalay 40 ns tecen CLK to PCLK HIGH Delay 22 ns teLeL CLK to PCLK LOW Delay 22 ns toLcn OSC to CLK HIGH Delay ~5 -5 22 ns tore. | OSC to CLK LOW Delay 2 -2 35 | ns toon Output Rise Time (except CLK} 20 ns | From 0.8V to 2.0V toHor Output Fall Time {except CLK) 12 ns | From 2,0V to 0.8V NOTES: 1, Setup and hold necessary only to guarantee recognition at next clock. 2. Applies only to T3 and T,, states. 3. Applies only to T2 states, A.C, TESTING INPUT, OUTPUT WAVEFORM 2.4 Xs =TEST POINTSs we 0.45 A.C. TESTING: Inputs are driven at 2.4V for a logic 1 and 0.45V for e logic O'. timing measurements are made at 1.5V for both a jogic 1 and "0", Input rise and fall times imeasurad hetween 0 2 snd O OV ara Re9One A.C. TESTING LOAD CIRCUIT VL RL DEVICE UNDER TEST T Vilv) | ALA} CL(pF) _CLK 3.41V 590 100 BEARY 7 nove a3AF anFUJITSU NICROELECTRONICS 4? ve 37447b2 oooy4o3 3 i BN MBL 8284A - yuorrsu MBL 8284A-.-1 El Hs TE. ; T-49-17-07 WAVEFORMS CLOCKS AND RESET SIGNALS tEHEL tELE NAME I/O EFI i osc 0 teL2cL1 L teHcL CLK O tobev toc. teLec PCLK O HPL cSYNC | teLitH | tHHcL RES ! re RESET O _ / _ NOTE: All timing measurements are made at 1,5 volts, unless otherwise noted, READY SIGNALS (FOR ASYNCHRONOUS DEVICES) CLK FL Py fy J] _/| _ tRivcH+ z AIVCL as = RDY1, 2 f 4 taiveaiv te_Aaix AENT, 2 \ oe tayYVCL teLa1x ASYNC ' ft A ee tcLAYX se READY f tayice es] taYHCHFUJITSU MICROELECTRONICS 9? DEB) 37497b2 coou4Oy 5 i PLETE T-49-17-07 FUJITSU MBL 8284A RH | MBL 8284A-1 WAVEFORMS (Continued) READY SIGNALS (FOR SYNCHRONOUS DEVICES) CLK / / \ t \ . f , / \ petcoLAixe h=tRiVvCL = tatvee : RDY1, 2 t 4 tA1VAIV = tcLR1Ix AEN1, 2 , ft TtaAYVCL teLa1x . ASYNG f tcLayx READY t . i} tRYLCL ~ tRYHCH CLOCK HIGH AND LOW TIME (USING Xt, X2) LOAD x4 _ GLK (SEE NOTE 1) X2 FIC Xtal = 24 MHz for MBL 82844 = 30 MHz for MBL 8284A-1 CSYNC R, =R, =5109 I CLOCK HIGH AND LOW TIME (USING EFI) PULSE LOAD GENERATOR EFI elk (SEE NOTE 1) FIC CSYNC AFUJITSU MICROELECTRONICS 4? Deg J?49?be OOO4OS ? a MBL 82844 FUJITSU Wie Ue aE MBL 8284A-1 Fi 3 READY TO CLOCK (USING X1, X2) Vec LOAD AENT = CLK (SEE NOTE 1) ~e- xl LOAD Xtal CI) READY {SEE NOTE 2) - x2 PULSE GENERATOR RDY2 Osc R, R, TRIGGER FC Xtal = 24 MHz for MBL 8284A REND = 30 MHz for MBL 8284A-1 CSYNC = = = R, =A, = 5100 READY TO CLOCK (USING EFI) PULSE LOAD GENERATOR EFI CLK (SEE NOTE 4) Vee F/C TRIGGER AENT PULSE RDY2 GENERATOR REND LOAD CSYNG EADY (SEE NOTE 2) NOTES: 1, C, = 100 pF 2,C.= 30pFFUJITSU MICROELECTRONICS 497 DE 34u97be GOO44Ob 4 [ Ta T-49-17-07 FUJITSU MBL 8284A EMD MBL 8284A-1 NOTES FOR USING MBL 8284A For MBL 8284As stable operation, the following things should be noted: 1. The fundamental mode crystal should be used. 2. Stray capacitances between X1 and X2 should be limited to less than 10pF. : 3. External resistors for stable crystal oscillation should be connected as Configuration (I}-or (II) shown below. Especially, for Configuration (I) circuit, the minimum frequency of crystal is limitted to 15MHz. A low frequency crystal {less than 15MHz) with Configuration (I) circuit may cause an abnormal oscillation. For more stable osciallation over the specified frequency range (12MHz to 25MHz or 30MHz), Configuration (II) circuit is recommendable. 4. The rise time of the power supply voltage Voc should be more than 10ms, A steep Veg rising (with the rise time less than - 10ms) may cause an overtone oscillation, 5. In the power-on reset circuit shown below, the ground terminal of the external capacitor C should be grourided as near to the GND pin of MBL 82844 as possible. 6. When the crystal oscillator circuit is not used (i.e., an external clock source Is used), X1 should be pulled UP to Veg with an approx, 1kQ2 resistor and X2 should be left open. At this time, OSC output is clamped at high fevel. CRYSTAL OSCILLATOR CIRCUIT Configuration (1) Configuration {il} Xt --= OSC X1 = OSC xtal CLK Xtal CI zr |} ork X2 . X2 H~ PCLK -~ PCLK MBL 8284A MBL 82844 R R ' . F/T F/C CSYNC CSYNC a aT . Ry = Ro = 5102, Xtal = 15 MHz to 25MHz {MBL 8284A) Rp = 510M, Xtal = 12MHz to 25MHz (MBL 82844) = 16MHz to 30MHz (MBL 82844-1) = 12MHz to. 30MHz (MBL 82844-1) POWER-ON RESET CIRCUIT _ EXTERNAL CLOCK CONFIGURATION Vv R 2 ; J OSC|/-= Clamped High < X1 : CLK RES: }+ RESET Open | X2 External PCLK MBL 82844 Clock EFI Source 1 Vcc [mei a2e4a c T GND F/C ur R = 1kQ, EFI < 25MHz (MBL 8284A} : <30MHz (MBL 8284A4-1}FUJITSU MICROELECTRONICS 47 vel J?49?be OOO4407 O i ETERS MBL 8284A = FUMITS MBL 8284A-1 EDU T-49-17-07 PACKAGE ILLUSTRATION CERAMIC DIP {CERDIP) PACKAGE DIMENSIONS CERAMIC DIP (Suffix: -CZ) 18-LEAD CERAMIC (CERDIP} DUAL IN-LINE PACKAGE (CASE No. : DIP-18C-C01) XL | en ory ot. Ca). fF a) OO | j R.02610.64) .285(7,24) .302(7.67) 7 ee NS 3051.78) 300(7.62)TYP .325(8.26} TTT eo ds I L .882(22.40) .912(23.16) t .008{0,20) .014(0.36) -| t+.056(1.42)MAX = = | .200(5.08)MAX .120(3,05) .150(3.81} .090(2.29) ,03210.81) | | 0201061} 110(2,78) | re 050(1.27} .800(20.32)REF I .042(1.07) | -913(0.33} Dimenstons in 7062(1.87) (02310.58) inches (millimeters)