1999-2013 Microchip Technology Inc. DS39026D-page 1
PIC18CXX2
High Performance RISC CPU:
• C compiler optimized architecture/instruction set
- Source code compatible with the PIC16CXX
instr uction set
• Linear pr ogram memory addressing to 2 Mbytes
•Linear data memory addressing to 4 Kbytes
• Up to 10 MIPs operation:
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz o sc ./ cl oc k i npu t with PL L ac ti ve
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single Cycle Hardware Mult iplier
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time-base for PWM)
• Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules.
CCP pins that can be configured as:
- Capture input: capture is 16-bit,
max. resolution 6.25 ns (TCY/16)
- Comp are is 16-bit, max. resolution 100 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit.
Max. PWM freq. @: 8-bit resolution = 156 kHz
10-bit resolution = 39 kHz
• Master Synchronous Serial Port (MSSP) module.
Two modes of operation:
- 3-wire SPI (supports all 4 SPI modes)
-I
2C™ master and slave mode
• Addressable USART module:
- Supports interrupt on Address bit
• Parallel Slave Port (PSP) module
Pin Diagrams
Analog Features:
• Compatible 10-bit Analog-to-Digital Converter
module (A/D) with:
- Fast samplin g rate
- Conversion available during SLEEP
- DNL = ±1 LSb, INL = ±1 LSb
• Programmable Low Voltage Detection (LVD)
module
- Supports int errup t-on -low vol t ag e dete ction
• Programmable Brown-out Reset (BOR)
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming (ICSP™) via two pins
CMOS Technology:
• Low power, high speed EPROM technology
• Fully static design
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
Device
On-Chip Program Memory On-Chip
RAM
(bytes)
EPROM
(bytes) # Single Word
Instructions
PIC18C242 16K 8192 512
PIC18C252 32K 16384 1536
PIC18C442 16K 8192 512
PIC18C452 32K 16384 1536
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18C4X2
* RB3 is the al tern ate pin for the CCP2 pin multiplexing.
DIP, Windowed CERDIP
Note: Pin compatible with 40-pin PIC16C7X devices.
High Perfor mance Microcontrollers with 10-bit A/D
PIC18CXX2
DS39026D-page 2 1999-2013 Microchip Technology Inc.
Pin Diagrams
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
44
8
7
6
5
4
3
2
1
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
PIC18C4X2
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
OSC2/CLKO/RA6
NC
RE1/WR/AN6
RE2/CS/AN7
VDD
OSC1/CLKI
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
10
11
2
3
4
5
6
1
18
19
20
21
22
12
13
14
15
38
8
7
44
43
42
41
40
39
16
17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
PIC18C4X2
37
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*
NC
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
VSS
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2*
PLCC
TQFP
* RB3 is the alternate pin for the CCP2 pin multiplexing.
Note: Pin compatible with 44-pin PIC16C7X devices.
VSS
RC0/T1OSO/T1CKI
1999-2013 Microchip Technology Inc. DS39026D-page 3
PIC18CXX2
Pin Diagrams (Cont.’d)
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18C4X2
PIC18C2X2
10
11
2
3
4
5
6
1
8
7
9
12
13
14 15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/VREF-
RA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS/LVDIN
VSS
OSC1/CLKI
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2*
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
* RB3 is the alternate pin for the CCP2 pin multiplexing.
DIP, JW
DIP, SOIC, JW
Note: Pin compatible with 40-pin PIC16C7X devices.
Note: Pin compatible with 28-pin PIC16C7X devices.
PIC18CXX2
DS39026D-page 4 1999-2013 Microchip Technology Inc.
Table of Contents
1.0 Device Overview......................................................................................................................................................................... 7
2.0 Oscillator Configurations ........................................................................................................... .. ............ . .................. .. ........... .. 17
3.0 Reset......................................................................................................................................................................................... 25
4.0 Memory Organization................................................................................................................................................................ 35
5.0 Table Reads/Table Writes .................................................................................................................. .. ................. .. ................. 55
6.0 8 X 8 Hardware Multiplier.......................................................................................................................................................... 61
7.0 Interrupts................................................................................................................................................................................... 63
8.0 I/O Ports.................................................................................................................................................................................... 77
9.0 Timer0 Module....................................... .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. .. ....... .... .. .. .............................................................. 93
10.0 Timer1 Module............................ .. ....... .... .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. .............................................................. 97
11.0 Timer2 Module............................ .. ....... .... .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. ............................................................ 101
12.0 Timer3 Module............................ .. ....... .... .. .... .. .. ....... .... .. .. .... .. ....... .. .... .. .... .. ....... .. .... .. ............................................................ 103
13.0 Capture/Com pare/PW M (CCP ) Modules................................................................................................ . ............ .. ........... .. .... 107
14.0 Master Sync hronous Serial Port (MSSP) Module................................................................................................................... 115
15.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USA RT)........................................................ .. .. 149
16.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module................................... .... .... ........... ...... .... ................................. 165
17.0 Low Voltage Detect................. .. .... ..... .. .. .... .. .. .. .. ....... .. .. .. .. .... .. ..... .. .... .. .. .. .. ....... .. .. .. .... .. .......................................................... 173
18.0 Special Features of the CPU...................................................................................................... .. ...... .. ................. .. ........... .. .. 179
19.0 Instruction Se t Summary. ....................... ...... ...... ............. ...... ....... ...... ....................... ...... ........................................................ 187
20.0 Development Support........................................ ....... .... .... .. .... ......... .. .... .... .. ......... .. .... .... .. . ..................................................... 229
21.0 Electrical Characteristics... ............ ....... ............ ....... ............ ............................................ ............ .. ................. .. ............ . .......... 235
22.0 DC and AC Characteristics Graphs and Tables .. ................................................................................................................... 263
23.0 Packaging Information........................................................................................................ .................. .. ........... .. ................. .. 277
Appendix A: Revision History..................................................... .... ........... .... .... ........... ...... .... ... ..................................................... 287
Appendix B: Device Differences........................................... .. .... .. ....... .... .... .. .... .. ......... .. .... .. .... ...................................................... 287
Appendix C: Conversion Considerations................. ......... .... .. .... .... ....... .... .. .... .... ....... .... .... .. .... ...................................................... 288
Appendix D: Migration from Baseline to Enhanced Devices........................................................................... ...... .. ................. .. .... 288
Appendix E: Migration from Mid-Range to Enhanced Devices ...................................................................................................... 289
Appendix F: Migration from High-End to Enhanced Devices......................................................................................................... 289
Index .................................................................................................................................. .. ........... .. ............ .. ................. .. ........... .. .. 291
On-Line Support............................................... .... .... .... ......... .... .... .. ........... .. .... .... ......... .................................................................... 299
Reader Response............................................................................................................................................................................. 300
PIC18CXX2 Product Identification System ....................................................................................................................................... 301
1999-2013 Microchip Technology Inc. DS39026D-page 5
PIC18CXX2
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our pu blications to better s uit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or c omm ents regarding t his publication, please contact the Marketing Co mmunications Department via
E-mail at docerrors@mail.microchip.com or fax the R eader Response Form in the back of th is data sheet to (480) 792-4150.
We welcome your feedback.
Most Current Data Sheet
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the dat a sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microc hip.com
• Your local Microc hip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
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Customer No tific atio n Syst em
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
PIC18CXX2
DS39026D-page 6 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 7
PIC18CXX2
1.0 DEVICE OVERVIEW
This do cu me nt co nta i ns dev ic e spec if i c in for m at ion fo r
the following four devices:
1. PIC18C242
2. PIC18C252
3. PIC18C442
4. PIC18C452
These devices come in 28-pin and 40-pin packages.
The 28-pin devices do not have a Parallel Slave Port
(PSP) implemented and the number of Analog-to-
Digital (A/D) converter input channels is reduced to 5.
An overview of features is shown in Table 1-1.
The following two figures are device block diagrams
sorted by pin count: 28-pin for Figure 1-1 and 40-pin for
Figure 1-2. The 28-pin and 40-pin pinouts are listed in
Table 1-2 and Table 1-3, respectively.
TABLE 1-1: DEVICE FEATURES
Features PIC18C242 PIC18C252 PIC18C442 PIC18C452
Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz
Program Memo ry (Bytes ) 16K 32K 16K 32K
Program Memo ry (Instructions) 8192 16384 8192 16384
Data Memory (Bytes) 512 1536 512 1536
Interrupt Sources 16 16 17 17
I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4444
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
MSSP,
Addressable
USART
Parallel Communications — — PSP PSP
10-bit Analog-to-Digital Module 5 input channels 5 input channels 8 input channels 8 input channels
RESETS (and Delays) POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
POR, BOR,
RESET Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Programmab le Low Voltage
Detect Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions
Packages 28-pin DIP
28-pin SOIC
28-pin JW
28-pin DI P
28-pin SOIC
28-pin JW
40-pin DI P
44-pin PLCC
44-pin TQFP
40-pin JW
40-pin DI P
44-pin PLCC
44-pin TQ FP
40-pin JW
PIC18CXX2
DS39026D-page 8 1999-2013 Microchip Technology Inc.
FIGURE 1-1: PIC18C2X2 BLOCK DIAGRAM
Power-up
Timer
Oscillator
S tart-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RB0/INT0
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of th e g en era l purpose I/O pin s a re mu lti ple xed w ith on e o r more pe riph era l module fun cti on s. T he m ulti ple xing combinatio n s
are device dependent.
Addressable
CCP1 Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
4X PLL
A/D Converter
Precision
Reference
RB1/INT1
Data Latch
Data RAM
Address Latch
Address<12>
12(2)
BSR FSR0
FSR1
FSR2
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP 8
8
ALU<8>
8
Address Latch
Program Memory
(up to 2M Bytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21 8
Data Bus<8>
8
Instruction
12
3
ROM Latch
Timer3
CCP2
RB2/INT2
RB3/CCP2(1)
T1OSI
T1OSO
Bank0, F
PCLATU
PCU
RA6
Voltage
USART
Master
8
Register
Table Latch
Table Pointer <2>
inc/dec
logic
Decode
1999-2013 Microchip Technology Inc. DS39026D-page 9
PIC18CXX2
FIGURE 1-2: PIC18C4X2 BLOCK DIAGRAM
Power-up
Timer
Oscillator
S t art-up Ti mer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS/LVDIN
RB0/INT0
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
Note 1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations
are device dependent.
Addressable
CCP1 Master
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Parallel Slave Port
Timing
Generation
4X PLL
A/D Converter
RB1/INT1
Data Latch
Data RAM
(up to 4K
address reach)
Addr ess La tch
Address<12>
12(2)
Bank0, F
BSR FSR0
FSR1
FSR2
412 4
PCH PCL
PCLATH
8
31 Level Stack
Progr am Coun ter
PRODLPRODH
8 x 8 Multiply
WREG
8
BIT OP 8
8
ALU<8>
8
Address Latch
Prog ram Memo ry
(up to 2M Bytes)
Data Latch
20
21
21
16
8
8
8
inc/dec logic
21 8
Data Bus<8>
8
Instruction
12
3
ROM Latch
Timer3
PORTD
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
CCP2
RB2/INT2
RB3/CCP2(1)
T1OSI
T1OSO
PCLATU
PCU
RA6
Precision
Reference
Voltage
Synchronous USART
Register
8
Table Pointer <2>
inc/dec
logic
Decode
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Table Latch
PIC18CXX2
DS39026D-page 10 1999-2013 Microchip Technology Inc.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP SOIC
MCLR/VPP
MCLR
VPP
11I
P
ST Master clear (input) or programming voltage (input).
Master Clear (Reset) input. This pin is an active low
RESET to the device.
Programming voltage input.
NC — — — — These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
99I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins. )
OSC2/CLKO/RA6
OSC2
CLKO
RA6
10 10 O
O
I/O
—
—
TTL
Oscillator crystal or clock output.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
22
I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
33
I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
44
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
55
I/O
I
I
TTL
Analog
Analog
Digit al I/O .
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
T0CKI
66
I/O
IST/OD
ST Digital I/O. Open drain when configured as output.
Timer 0 external clock input.
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
77
I/O
I
I
I
TTL
Analog
ST
Analog
Digit al I/O .
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 11
PIC18CXX2
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
21 21 I/O
ITTL
ST Digital I/O.
External Interrupt 0.
RB1/INT1
RB1
INT1
22 22 I/O
ITTL
ST External Interrupt 1.
RB2/INT2
RB2
INT2
23 23 I/O
ITTL
ST Digital I/O.
External Interrupt 2.
RB3/CCP2
RB3
CCP2
24 24 I/O
I/O TTL
ST Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
RB4 25 25 I/O TTL Digital I/O.
Interrupt-on-change pin.
RB5 26 26 I/O TTL Digital I/O.
Interrupt-on-change pin.
RB6 27 27 I/O
I
TTL
ST
Digital I/O.
Interrupt-on-change pin.
ICSP programming clock.
RB7 28 28 I/O
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
ICSP programming data.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026D-page 12 1999-2013 Microchip Technology Inc.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
11 11 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
12 12 I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
13 13 I/O
I/O ST
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
14 14 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
15 15 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
SDO
16 16 I/O
OST
—Digital I/O.
SPI Data Out.
RC6/TX/CK
RC6
TX
CK
17 17 I/O
O
I/O
ST
—
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
18 18 I/O
I
I/O
ST
ST
ST
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data (see related TX/CK).
VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
VDD 20 20 P — Positive supply for logic and I/O pins.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP SOIC
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 13
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
MCLR/VPP
MCLR
VPP
1218
I
P
ST Master clear (input) or programming voltage (input).
Master Clear ( Reset) input. Thi s pin is an active
low RESET to the device.
Programming voltage input.
NC — — — These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
13 14 30 I
I
ST
CMOS
Oscillator crystal or external clock input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode, CMOS otherwise.
External clock source in put. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins.)
OSC2/CLKO/RA6
OSC2
CLKO
RA6
14 15 31 O
O
I/O
—
—
TTL
Oscillator crystal output.
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT, which has
1/4 the f requenc y of OS C1 and de notes the instruc tion
cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
2319
I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
3420
I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
4521
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
5622
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
RA4/T0CKI
RA4
T0CKI
6723
I/O
IST/OD
ST Digital I/O. Open drain when configured as output.
Timer0 external clock input.
RA5/AN4/SS/LVDIN
RA5
AN4
SS
LVDIN
7824
I/O
I
I
I
TTL
Analog
ST
Analog
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Inp ut.
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026D-page 14 1999-2013 Microchip Technology Inc.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
RB0/INT0
RB0
INT0
33 36 8 I/O
ITTL
ST Digital I/O.
External Interrupt 0.
RB1/INT1
RB1
INT1
34 37 9 I/O
ITTL
ST External Interrupt 1.
RB2/INT2
RB2
INT2
35 38 10 I/O
ITTL
ST Digital I/O.
External Interrupt 2.
RB3/CCP2
RB3
CCP2
36 39 11 I/O
I/O TTL
ST Digital I/O.
Capture2 input, Compare2 output, PWM2 output.
RB4 37 4 1 14 I/O TTL Digital I/O. Interrupt-on-change pin.
RB5 38 4 2 15 I/O TTL Digital I/O. Interrupt-on-change pin.
RB6 39 43 16 I/O
ITTL
ST Digital I/O. Interrupt-on-change pin.
ICSP programming clock.
RB7 40 44 17 I/O
I/O TTL
ST Digital I/O. Interrupt-on-change pin.
ICSP programming data.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 15
PIC18CXX2
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
15 16 32 I/O
O
I
ST
—
ST
Digital I/O.
Timer1 oscillator output.
Ti mer1/Timer3 external clock input.
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
16 18 35 I/O
I
I/O
ST
CMOS
ST
Digital I/O.
Ti mer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
RC2/CCP1
RC2
CCP1
17 19 36 I/O
I/O ST
ST Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3
SCK
SCL
18 20 37 I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
I2C mode.
RC4/SDI/SDA
RC4
SDI
SDA
23 25 42 I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI Data In.
I2C Data I/O.
RC5/SDO
RC5
SDO
24 26 43 I/O
OST
—Digital I/O.
SPI Data Out.
RC6/TX/CK
RC6
TX
CK
25 27 44 I/O
O
I/O
ST
—
ST
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock (see related RX/DT).
RC7/RX/DT
RC7
RX
DT
26 29 1 I/O
I
I/O
ST
ST
ST
Digital I/O.
USART Asyn chronous Receive.
USART Synchronous Data (see related TX/CK).
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
PIC18CXX2
DS39026D-page 16 1999-2013 Microchip Technology Inc.
PORTD is a b i-direc tional I/O port, or a Parallel Sl ave Po rt
(PSP) for interfaci ng to a micropro cessor por t. These pi ns
have TTL input buffers when PSP module is enabled.
RD0/PSP0 19 21 38 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD1/PSP1 20 22 39 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD2/PSP2 21 23 40 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD3/PSP3 22 24 41 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD4/PSP4 27 30 2 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD5/PSP5 28 31 3 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD6/PSP6 29 32 4 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
RD7/PSP7 30 33 5 I/O ST
TTL Digital I/O.
Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
RE0/RD/AN5
RE0
RD
AN5
8925I/O
ST
TTL
Analog
Digital I/O.
Read control for parallel slave port (see also WR
and CS pins).
Analog input 5.
RE1/WR/AN6
RE1
WR
AN6
91026I/OST
TTL
Analog
Digital I/O.
Write control for parallel slave port (see CS
and RD pins).
Analog input 6.
RE2/CS/AN7
RE2
CS
AN7
10 11 27 I/O ST
TTL
Analog
Digital I/O.
Chip Select control for parallel slave port (see related
RD and WR).
Analog input 7.
VSS 12, 31 13, 34 6, 29 P — Ground refer ence for logic and I/O pins.
VDD 11, 32 12, 35 7, 28 P — Positive supply for logic and I/O pins.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name Pin Number Pin
Type Buffer
Type Description
DIP PLCC TQFP
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels I = Input
O = Output P = Power
OD = Open Drain (no P diode to VDD)
1999-2013 Microchip Technology Inc. DS39026D-page 17
PIC18CXX2
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
The PIC18CXX2 can be operated in eight different
oscillator modes. The user can program three configu-
ration b its (FOSC2 , FOSC1, and FOSC0) t o sel ect on e
of these eight modes:
1. LP Low Power Crystal
2. XT Crystal/Resonator
3. HS High Speed Crystal/Resonator
4. HS + PLL High Speed Crystal/Resonator
with x 4 PLL enabled
5. RC External R esi st or/Capacitor
6. RCIO Extern al Resi stor/Cap ac ito r with
RA6 I /O pin enabled
7. EC Extern al Clock
8. ECIO External Cloc k with RA6 I/O pin
enabled
2.2 Crystal Oscillator/Ceramic
Resonators
In XT, LP, HS or HS-PLL oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The PIC1 8CXX2 osc illat or desi gn requ ires th e use o f a
parallel cut crystal.
FIGURE 2-1: CRY STAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
TABLE 2-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
Note 1: See Table 2-1 and Table 2-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for A T
strip cut crystals.
3: RF varies with the osc mode chosen.
C1(1)
C2(1)
XTAL
OSC2
OSC1
RF(3)
SLEEP
To
Logic
PIC18CXXX
RS(2)
Internal
Ranges Tested:
Mode Freq C1 C2
XT 455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS 8.0 MHz
16.0 MHz 10 - 68 pF
10 - 22 pF 10 - 68 pF
10 - 22 pF
These va lues are for design guid ance only.
See notes following this table.
Reson ators U sed :
455 kHz Panasonic EFO-A455K04B 0.3%
2.0 MHz Murata Erie CSA2.00MG 0.5%
4.0 MHz Murata Erie CSA4.00MG 0.5%
8.0 MHz Murat a Erie CSA 8.00 MT 0.5%
16.0 MHz Murata Erie CSA16.00MX 0.5%
All resonators used did not have built-in capacitor s.
Note 1: Higher cap acita nce increase s the st ability
of the oscillator, but also increases the
start-up time.
2: When operati ng bel ow 3V VDD, it may be
necessary to use high gain HS mode on
lower frequency ceramic resonators.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents or verify oscillator performance.
PIC18CXX2
DS39026D-page 18 1999-2013 Microchip Technology Inc.
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATORS
An externa l cloc k sourc e may also be conne cted to th e
OSC1 pin in these m odes, as shown in Figure 2-2.
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP CONFIGURATION)
2.3 RC Oscillator
For timing insensitive applications, the “RC” and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) val-
ues and the operating temperature. In addition to this,
the oscil lator frequen cy will vary from unit to unit due to
normal process parameter variation. Furthermore, the
difference in lead fram e c apacitance be tw ee n package
types will also affect the oscillation frequency, espe-
cially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 2-3 shows how the
R/C combination is connected.
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be us ed for t est pu r pos es or t o sy nc hr o niz e o t he r
logic.
FIGURE 2-3: RC OSCILLATOR MODE
The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
Ranges Tested:
Mode Freq C1 C2
LP 32.0 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
XT 200 kHz 47-68 pF 47-68 pF
1.0 MHz 15 pF 15 pF
4.0 MHz 15 pF 15 pF
HS 4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF
20.0
MHz 15-33 pF 15-33 pF
25.0
MHz 15-33 pF 15-33 pF
These va lues are for design guid ance only.
See notes following this table.
Crystals Used
32.0 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000kHz ± 20 PPM
1.0 MHz ECS ECS-10-13-1 ± 50 PPM
4.0 MHz ECS ECS-40-20-1 ± 50 PPM
8.0 MHz Epson CA-301 8.000M-C ± 30 PPM
20.0 MHz Epson CA-301 2 0.0 00M -C ± 30 PPM
Note 1: Highe r cap acita nce increase s the st ability
of the oscillator, but also increases the
start - up time.
2: Rs may be required in HS mode, as well
as XT mode, to av oid ov erdrivi ng crys tal s
with low drive level specification.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents or verify oscillator performance.
OSC1
OSC2
Open
Clock from
Ext. System PIC18CXXX
OSC2/CLKO
CEXT
REXT
PIC18CXXX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values:3 k REXT 100 k
CEXT > 20pF
1999-2013 Microchip Technology Inc. DS39026D-page 19
PIC18CXX2
2.4 External Clock Input
The EC a nd EC IO os c ill ato r m ode s require a n ext erna l
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is no oscilla-
tor start-up time required after a Power-on Reset or
after a recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be u s ed for t est pu r pos es or t o sy nc hr o niz e o t he r
logic. Figure 2-4 shows the pin connections for the EC
oscillator mode.
FIGURE 2-4: EXT ER NAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
The ECIO oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
FIGURE 2-5: EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
2.5 HS/PLL
A Phase L ocke d Loop circuit is pro vided as a program-
mable option for users that want to multiply the fre-
quency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator con-
figuratio n bits are p rogrammed for HS mode. If the y are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one o f the mod es of the FOSC<2:0> config-
uration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called TPLL.
FIGURE 2-6: PLL BLOCK DIAGRAM
OSC1
OSC2
FOSC/4
Clock from
Ext. System PIC18CXXX
OSC1
I/O (OSC2)
RA6
Clock from
Ext. System PIC18CXXX
MUX
VCO
Loop
Filter
Divide by 4
Crystal
Osc
OSC1
PLL Enable
FIN
FOUT SYSCLK
Phase
Comparator
(from Configuration HS Osc
bit Register)
OSC2
PIC18CXX2
DS39026D-page 20 1999-2013 Microchip Technology Inc.
2.6 Oscillator Switching Feature
The PIC18CXX2 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18CXX2 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crys-
tal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low power
execution mode. Figure 2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN) bi t in Configu r ati on Regi ster1H to a
’0’. Clock switching is disabled in an erased device.
See Secti on 9.0 for fu rther det ails of th e T imer1 os cilla-
tor . See Section 18.0 for Configuration Register details.
FIGURE 2-7: DEVICE CLOCK SOURCES
2.6.1 SYSTEM CLOCK SWITCH BIT
The system clock source sw it chi ng is performe d und er
software control. The system clock switch bit, SCS
(OSCCON<0>) controls the clock switching. When the
SCS bi t is ’0’, t he s ystem cloc k sou rce co mes fr om t he
main os ci lla tor t hat i s s el ec ted b y t he FO SC c onfigura-
tion bi ts in Co nfiguration R egister1H. W hen the SC S bit
is set, the system clock source will come from the
T i mer1 o scillato r. The SCS bit is clear ed on a ll form s of
RESET.
REGISTER 2-1: OSCCON REGISTER
PIC18CXXX
TOSC
4 x PLL
TT1P
TSCLK
Clock
Source
MUX
TOSC/4
Timer1 Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source option
for other modules
OSC1
OSC2
SLEEP
Main Oscillator
Note: The T im er1 osci llator must be enable d and
operating to switch the system clock
source. The T imer1 oscillator is enabled by
setting the T1OSCEN bit in the Timer1
control register (T1CON). If the Timer1
oscillator is not enabled, then any write to
the SCS bit wil l b e ig nore d (SCS bit fo rce d
cleared) and the main oscillator will con-
tinue to be the syste m clo ck sourc e.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
— — — — — — —SCS
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 SCS: System Clock Switch bit
When OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When OSCSEN and T1OSCEN are in other state s:
bit is forced clear
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 21
PIC18CXX2
2.6.2 OSCILLATOR TRANS ITIO NS
The PIC18CXX2 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the cloc k source that the pro cessor is swit ching to. This
ensu res that th e new cloc k sour ce is st able an d that it’ s
pulse width will not be less than the shortest pulse
width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in
Figur e 2-8. The T ime r1 oscilla tor is assu med to be run-
ning all the tim e. Afte r the SCS bit is set, the pro cessor
is froze n at the next occ urring Q1 cycle. Af ter eight sy n-
chronization cycles are counted from the Timer1 oscil-
lator, operation resumes. No additional delays are
required after the synchronization cycles.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crys-
tal (H S, XT, LP), then the tr ans it ion will take plac e af t er
an osc illator st art-up time (TOST) has occ urred. A timing
diagram indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3Q2Q1Q4Q3Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program PC + 2PC
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
Q1
T1OSI
Q4 Q1
PC + 4
Q1
Tscs
Clock
Counter
System
Q2 Q3 Q4 Q1
TDLY
TT1P
TOSC
21 34 5678
Q3
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
OSC2
TOST
Q1
PC + 6
TT1P
TOSC
TSCS
12345678
PIC18CXX2
DS39026D-page 22 1999-2013 Microchip Technology Inc.
If the ma in oscilla tor is config ured for HS-PLL m ode, an
oscillator start-up time (TOST) plus an additional PLL
time-out (TPLL) will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10 .
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
If the ma in o scillato r is c onfigur ed in th e RC, R CIO, EC
or ECIO mod es, there is no os cill ator st art-u p tim e-ou t.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
TOST
Q3
PC + 4
TPLL
TOSC
TT1P
TSCS
Q4
OSC2
PLL Clock
Input 1 234 5678
Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSC1
Internal System
SCS
(OSCCON<0>)
Program Counter PC PC + 2
Note 1: RC oscillator mode assumed.
PC + 4
T1OSI
Clock
OSC2
Q4
TT1P
TOSC
TSCS
123
45678
1999-2013 Microchip Technology Inc. DS39026D-page 23
PIC18CXX2
2.7 Effects of SLEEP Mode on the
On-chip Oscilla tor
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 st a te). W ith the os ci lla tor o f f, the OSC1 an d OS C2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will o perate duri ng SLEEP will incre ase the curre nt
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or th rough an interrupt.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
2.8 Power-up Delays
Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are st a-
ble. For additional information on RESET operation,
see the “RESET” section.
The first timer is the Power-up Timer (PWRT), which
optionally provid es a fix ed delay of 72 ms (nom inal) on
power-up only (POR and BOR). The second timer is
the Os cillator S ta rt-up T imer , OS T, intend ed to keep th e
chip in RESET until the crystal oscillator is stable.
With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other oscillator m odes. The time -out sequence
is as follows: First, the PWRT time-out is invoked after
a POR time delay has expired. Then, the Oscillator
Start-up Timer (OST) is invoked. However, this is still
not a sufficient amount of time to allow the PLL to lock
at high frequencies . The PWR T timer i s used to prov ide
an additional fixed 2ms (nominal) time-out to allow the
PLL ample time to lock to the incoming clock frequency .
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should
pull high At logic low
RCIO Floating, external r esistor should
pull high Configured as PORTA, bit 6
ECIO Floating Configured as PORTA, bit 6
EC Floating At logic low
LP, XT, and HS Feedback inverter disabled, at
quiescent voltage level Feedbac k inv erter disable d, at
quiesc ent vo ltage level
Note: See Table 3-1, in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
PIC18CXX2
DS39026D-page 24 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 25
PIC18CXX2
3.0 RESET
The PIC18CXX2 differentiates between various kinds
of RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset (during normal
operation)
e) Programmable Brown-out Reset (BOR)
f) RESET Inst ruction
g) Stack Full Reset
h) Stack Underflow Reset
Most regis ters are u naffe cted by a RESET. Thei r status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET
stat e” on Power- on Reset, MCL R, WDT Reset, Brown-
out Reset, MCLR Reset during SLEEP, and by the
RESET instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, R I, TO, PD,
POR and BOR , are set or cleared differently in different
RESET situa tions, as indicated in Table 3-2. These bit s
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
A simplif ied block diagra m of the On-Chip Re set Circuit
is sh own in Figur e 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
MCLR pin is not driven low by any internal RESETS,
inc ludin g WDT.
FIGURE 3-1: SI MPLI FI ED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
RQ
External Reset
MCLR
VDD
OSC1
WDT
Module
VDD Rise
Detect
OST/PWRT
On-chip
RC OSC
(1)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST(2)
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
Brown-out
Reset BOREN
RESET
Instruction
Stack
Pointer S tack Full/Underflow Reset
PIC18CXX2
DS39026D-page 26 1999-2013 Microchip Technology Inc.
3.1 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is d etected. To ta ke advant age of t he POR cir-
cuitry, just ti e t he MCLR pin d irectly (or th rough a resi s-
tor) to VDD. This will elim inate ex ternal RC component s
usually needed to create a Power-on Reset delay. A
minimum rise rate for VDD is specified (parameter
D004). For a slow rise time, see Figure 3-2.
When the device s t a r t s norm al ope rati on (i.e ., ex its the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in reset until the operating condi-
tions are met.
FIGURE 3-2: EXT ERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
3.2 Power-up T imer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in rese t as long as the PWRT is active.
The PWR T’s time de lay allows VDD to rise to an acce pt-
able level. A configuration bit is provided to enable/
disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to VDD, temperature and process variation. See DC
parameter #33 for details.
3.3 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWR T delay is over (para meter #32). Th is ensures th at
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4 PLL Lock Ti me-out
With the PLL e nabled , the time-ou t sequen ce foll owin g
a Power-on Reset is different from other oscillator
modes. A portio n of th e Powe r-up Timer is us ed to p ro-
vide a fi xed time-out th at is suf ficient for th e PLL to loc k
to the mai n osci llator fre quenc y. This PLL lock time-o ut
(TPLL) is typically 2 ms and follows the oscillator start-
up time-out (OST).
3.5 Brown-out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A RESET may not occur if VDD falls below
param ete r D005 for les s than p aram et er #35 . The chip
will remain in Brown-out Reset until VDD rises above
BVDD. The Power-up Timer will then be invoked and
will keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-ou t Reset and the Power-up T imer will be initia l-
ized. Once VDD rises above BVDD, the Power-up T im er
will execute the additional time delay.
3.6 Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the st a tus of the PWR T. For e xam pl e, in R C m ode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the PO R pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXXX device oper-
ating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditio ns for all the regist ers .
Note 1: External Power-on Reset circuit is required
only if the VDD power-up slope is too slow.
The diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k is recommended to make sure that
the voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR from external capacitor C in
the event of MCLR/VPP pin breakdown, due
to Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC18CXXX
1999-2013 Microchip Technology Inc. DS39026D-page 27
PIC18CXX2
TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS
REGISTER 3-1: RCON REGISTER BITS AND POSITIONS
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Oscillator
Configuration
Power-up(2)
Brown-out(2) Wake-up from
SLEEP or
Oscillator Switch
PWRTE = 0 PWRTE = 1
HS with PLL enabled(1) 72 ms + 1024TOSC
+ 2ms 1024TOSC
+ 2 ms 72 ms + 1024TOSC
+ 2ms 1024TOSC + 2 ms
HS, XT, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC
EC 72 ms — 72 ms —
External RC 72 ms — 72 ms —
Note 1: 2 ms is the nomin al tim e requi red for the 4x PLL to lock.
2: 72 ms is the nominal Power-up Timer delay.
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
Note: See Register 4-3 on page 53 for bit definitions.
Condition Program
Counter RCON
Register RI TO PD POR BOR STKFUL STKUNF
Power-on Reset 0000h 00-1 1100 1 1 1 0 0 u u
MCLR Reset during normal
operation 0000h 00-u uuuu u u u u u u u
Software Reset during normal
operation 0000h 0u-0 uuuu 0 u u u u u u
S tack Full Reset during normal
operation 0000h 0u-u uu11 u u u u u u 1
Stack Underflow Reset during
normal operation 0000h 0u-u uu11 u u u u u 1 u
MCLR Reset during SLEEP 0000h 00-u 10uu u 1 0 u u u u
WDT Reset 0000h 0u-u 01uu 1 0 1 u u u u
WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u
Brown-out Reset 0000h 0u-1 11u0 1 1 1 1 0 u u
Interrupt wake-up from SLEEP PC + 2(1) uu-u 00uu u 1 0 u u u u
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
PIC18CXX2
DS39026D-page 28 1999-2013 Microchip Technology Inc.
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register Appli cable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu(3)
TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3)
STKPTR 242 442 252 452 00-0 0000 00-0 0000 uu-u uuuu(3)
PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu
PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PCL 242 442 252 452 0000 0000 0000 0000 PC + 2(2)
TBLPTRU 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PRODH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 242 442 252 452 0000 000x 0000 000u uuuu uuuu(1)
INTCON2 242 442 252 452 1111 -1-1 1111 -1-1 uuuu -u-u(1)
INTCON3 242 442 252 452 11-0 0-00 11-0 0-00 uu-u u-uu(1)
INDF0 242 442 252 452 N/A N/A N/A
POSTINC0 242 442 252 452 N/A N/A N/A
POSTDEC0 242 442 252 452 N/A N/A N/A
PREINC0 242 442 252 452 N/A N/A N/A
PLUSW0 242 442 252 452 N/A N/A N/A
FSR0H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 242 442 252 452 N/A N/A N/A
POSTINC1 242 442 252 452 N/A N/A N/A
POSTDEC1 242 442 252 452 N/A N/A N/A
PREINC1 242 442 252 452 N/A N/A N/A
PLUSW1 242 442 252 452 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is d ue to an interru pt and the G IEL or G IEH bit i s set, the PC is load ed with the interrup t
vecto r (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of POR TA, LA TA and TRISA are not avail able on all devices . When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc. DS39026D-page 29
PIC18CXX2
FSR1H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
INDF2 242 442 252 452 N/A N/A N/A
POSTINC2 242 442 252 452 N/A N/A N/A
POSTDEC2 242 442 252 452 N/A N/A N/A
PREINC2 242 442 252 452 N/A N/A N/A
PLUSW2 242 442 252 452 N/A N/A N/A
FSR2H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu
TMR0H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
OSCCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
LVDCON 242 442 252 452 --00 0101 --00 0101 --uu uuuu
WDTCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
RCON(4, 6) 242 442 252 452 00-1 11q0 00-1 qquu uu-u qquu
TMR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu
TMR2 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PR2 242 442 252 452 1111 1111 1111 1111 1111 1111
T2CON 242 442 252 452 -000 0000 -000 0000 -uuu uuuu
SSPBUF 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Appli cable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is du e to an interru pt and the G IEL or G IEH bit i s set, the PC is load ed with the interrup t
vecto r (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of POR TA, LA TA and TRISA are not avail able on all devices . When unimplemented, they are read as ’0’.
PIC18CXX2
DS39026D-page 30 1999-2013 Microchip Technology Inc.
ADRESH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
ADCON1 242 442 252 452 --0- 0000 --0- 0000 --u- uuuu
CCPR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
CCPR2H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TMR3H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu
SPBRG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
RCREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA 242 442 252 452 0000 -01x 0000 -01u uuuu -uuu
RCSTA 242 442 252 452 0000 000x 0000 000u uuuu uuuu
IPR2 242 442 252 452 ---- 1111 ---- 1111 ---- uuuu
PIR2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu(1)
PIE2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
IPR1 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
242 442 252 452 -111 1111 -111 1111 -uuu uuuu
PIR1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(1)
242 442 252 452 -000 0000 -000 0000 -uuu uuuu(1)
PIE1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
242 442 252 452 -000 0000 -000 0000 -uuu uuuu
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Appli cable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is d ue to an interru pt and the G IEL or G IEH bit i s set, the PC is load ed with the interrup t
vecto r (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of POR TA, LA TA and TRISA are not avail able on all devices . When unimplemented, they are read as ’0’.
1999-2013 Microchip Technology Inc. DS39026D-page 31
PIC18CXX2
TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu
TRISD 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISA(5, 7) 242 442 252 452 -111 1111(5) -111 1111(5) -uuu uuuu(5)
LATE 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu
LATD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATA(5, 7) 242 442 252 452 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5)
PORTE 242 442 252 452 ---- -000 ---- -000 ---- -uuu
PORTD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA(5, 7) 242 442 252 452 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5)
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Appli cable Devices Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is du e to an interru pt and the G IEL or G IEH bit i s set, the PC is load ed with the interrup t
vecto r (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR Reset.
7: Bit 6 of POR TA, LA TA and TRISA are not avail able on all devices . When unimplemented, they are read as ’0’.
PIC18CXX2
DS39026D-page 32 1999-2013 Microchip Technology Inc.
FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-O UT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TPWRT
TOST
1999-2013 Microchip Technology Inc. DS39026D-page 33
PIC18CXX2
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD)
FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
0V 1V 5V
TPWRT
TOST
TPWRT
TOST
VDD
MCLR
IINTERNAL POR
PWRT TIME-OUT
OST TIME-O UT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note: TOST = 1024 clock cycles.
TPLL 2 ms max. First three stages of the PWRT timer.
PIC18CXX2
DS39026D-page 34 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 35
PIC18CXX2
4.0 MEMORY ORGANIZATION
There are two memory blocks in Enhanced MCU
dev ices. These memory blocks are:
• Program Memory
• Data Memory
Program a nd data memory use separate buses so th at
concurr ent acc es s ca n occ ur.
4.1 Program Memory Organization
A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all ’0’s (a NOP
instruction).
PIC18C252 and PIC18C452 have 32 Kbytes of
EPROM, while PIC18C242 and PIC18C442 have
16 Kbytes of EPROM. This means that PIC18CX52
devices can store up to 16K of single word instructions,
and PIC18CX42 devices can store up to 8K of single
word instructions.
The RESET vector address is at 0000h and the inter-
rupt vector addresses are at 0008h and 0018h.
Figure 4-1 shows the Program Memory Map for
PIC18C242/442 devices and Figure 4-2 shows the
Program Memory Map for PIC18C252/452 devices.
PIC18CXX2
DS39026D-page 36 1999-2013 Microchip Technology Inc.
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC18C442/242
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC18C452/252
PC<20:0>
Stack Level 1
S tack Level 31
RESET Vector
Low Priority Interrupt Vector
CALL,RCALL,RETURN
RETFIE,RETLW 21
0000h
0018h
On-chip
Program Memory
High Priority Interrupt Vector 0008h
User Memory Space
1FFFFFh
4000h
3FFFh
Read '0'
200000h
PC<20:0>
Stack Level 1
S tack Level 31
Low Priority Interrupt Vec tor
CALL,RCALL,RETURN
RETFIE,RETLW 21
0000h
0018h
8000h
7FFFh
On-chip
Program Memory
High Priority Interrupt Vector 0008h
User Memory Space
Read '0'
1FFFFFh
200000h
RESET Vector
1999-2013 Microchip Technology Inc. DS39026D-page 37
PIC18CXX2
4.2 Return Address S tack
The return addre ss s tack al low s a ny co mb in ation of u p
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL or RCALL instruction is executed, or an interrupt
is acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW or a RETFIE instruction.
PCLATU and PCLATH ar e not af fected by any of the call
or return instructions.
The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b af ter all RESETS. There is no RAM associated
with s tac k poi nter 00 000b. T his is only a RES ET v alue.
During a CALL type inst ruction ca using a pus h onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction causing a pop from the stack, the contents
of the RAM location p ointed to by the STKPTR i s trans-
ferred to the PC and then the stack pointer is
decremented.
The stack space is not part of either program or data
space . Th e s tac k p oi n ter i s r ead ab l e a n d wr i tabl e, a nd
the addre ss on the top of the stac k is readable a nd writ-
able through SFR registers. Data can also be pushed
to, or popped from, the stack, using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
bey ond the 31 levels provided.
4.2.1 TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
softw are s tack, if nece ssar y. Aft er a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be p laced on a use r d efined sof twa re st ack .
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack opera-
tions..
4.2.2 RETURN STACK POINTER
(STKPTR)
The STKPTR re gis ter con t ai ns the st ack pointer va lu e,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR regis ter . The value of the stack point er can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer v alue will be 0. The u ser may read and wri te the
stac k pointer v alue. This feature can b e used by a Rea l
Time Operating System for return stack maintenance.
Aft er the P C is pu shed ont o the st ack 31 tim es (wi thout
popping any values off the stack), the STKFUL bit is
set. The ST KFUL bi t can only be cle ared in sof tware or
by a POR.
The action that takes place when the stack becomes
full, depe nds on th e state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 18.0 for a description of the device configura-
tion bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stac k, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to 0.
If STVREN is clea red, the STKFUL bit will b e set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload th e stack, the ne xt pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software or a POR occurs.
Note: Returning a value of zero to the PC on an
underflow, has the effect of vectoring the
program to the RESET vector, where the
stac k condition s can be verifi ed and appro-
priate actions can be taken.
PIC18CXX2
DS39026D-page 38 1999-2013 Microchip Technology Inc.
REGISTER 4-1: STKPTR REGISTER
FIGURE 4-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
4.2.3 PUSH AND POP INSTRUCTIONS
Since the Top-of-Stack (T O S) is rea dab le a nd writable,
the abili ty to push v alues onto the stac k and pull values
off t he st ack, wit hout distu rbing norm al program ex ecu-
tion, is a d esirable optio n. To push the cu rrent PC value
onto the stack, a PUSH instruction can be executed.
This will increm ent t he sta ck point er and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction . The POP instruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.
4.2.4 STACK FULL/UNDERFLOW RESET S
These resets are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabl ed, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflo w will set the appropria te STKFU L or STKUNF
bit and then cause a device RESET. The STKFUL or
STKUNF bits are only cleared by the user software or
a POR Reset.
R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0
bit 7 bit 0
bit 7(1) STKFUL: S t a ck Full Fla g bit
1 = Stack became full or overflowed
0 = Stack has not become full or overflowed
bit 6(1) STKUNF: Stack Underflow Flag bit
1 = Stack underflow occurred
0 = Stack underflow did not occur
bit 5 Unimplemented: Read as '0'
bit 4-0 SP4:SP0: Stack Pointer Location bits
Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
00011
0x001A34
11111
11110
11101
00010
00001
00000
00010
Return Address Stack
Top-of-Stack 0x000D58
TOSLTOSHTOSU 0x340x1A0x00 STKPTR<4:0>
1999-2013 Microchip Technology Inc. DS39026D-page 39
PIC18CXX2
4.3 Fast Regist er Stack
A "fast interrupt return " option is a vailable fo r interrupts.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers and are only one in depth.
The st ack is n ot read able o r writ abl e and is lo aded w ith
the current value of the corresponding register when
the pr ocessor vecto rs for an in terrupt. The va lues in the
registers are then loaded back into the working regis-
ters , if the FAST RETURN instruction is used to return
from the interrupt.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the sta ck register values stor ed by the low priority int er-
rupt will be overwritten.
If high p riority int errupt s are not d isabled duri ng low p ri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR register s
at the end of a su bro utin e cal l. To use the fas t re giste r
stack for a subroutine call, a FAST CALL instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.
EXAMPLE 4-1: FAST REGISTER STACK
CODE EXAMPLE
4.4 PCL, PCLATH and PCLATU
The progra m c oun ter (PC) spe ci fie s the addre ss of th e
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable. Updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register c ont ains th e PC<20:16 > bit s an d is not direc tly
readable or writable. Updates to the PCU register may
be performed through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of PCL is fixed to a value of ’0’.
The PC increments by 2 to address se que nti al ins truc -
tions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).
4.5 Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is sh own in Figur e 4-4.
FIGURE 4-4: CLOCK/INSTRUCTION CYCLE
CALL SUB1, FAST ;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
SUB1
RETURN FAST ;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+2 PC+4
Execute INST (PC-2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC+2) Execute INST (PC+2)
Fetch INST (PC+4)
Internal
Phase
Clock
PIC18CXX2
DS39026D-page 40 1999-2013 Microchip Technology Inc.
4.6 Instr uction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4 ). The ins truc ti on fe tch and exec ute a r e
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then tw o cycles are re quired to comple te the instruc tion
(Example 4-2).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the ex ecution cycle , the fetched instruction i s latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW
4.7 Instr uctions in Program Memory
The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB =’0’). Figure 4-5 shows an
exampl e of how instruc tion word s are stored i n the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read ’0’ (see Section 4.4).
The CALL and GOTO instructi ons have an absolute p ro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-
aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-5 shows how the
instruction “GOTO 000006h” is encoded in the program
memory. Program b ranc h i ns truc tio ns , whic h e nc ode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single word instructions that the
PC will be offset by. Section 19.0 provides further
details of the instruction set.
FIGURE 4-5: INS TRUCTIONS IN PROGRAM MEM ORY
All instruc tions are single cycle , except for any prog ram branches. These t ake two cycles sin ce the fetch instruct ion
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
TCY0TCY1TCY2TCY3TCY4TCY5
1. MOVLW 55h Fetch 1 Execute 1
2. MOVWF PORTB Fetch 2 Execute 2
3. BRA SUB_1 Fetch 3 Ex ecute 3
4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)
5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1
Word Address
LSB = 1 LSB = 0
Program Memory
Byte Locations 000000h
000002h
000004h
000006h
Instruction 1: MOVLW 055h 0Fh 55h 000008h
Instruction 2: GOTO 000006h EFh 03h 00000Ah
F0h 00h 00000Ch
Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh
F4h 56h 000010h
000012h
000014h
1999-2013 Microchip Technology Inc. DS39026D-page 41
PIC18CXX2
4.7.1 TWO-WORD INSTRUCTIONS
The PIC18CXX2 devices have four two-word instruc-
tions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to 1’s
and is a special kind of NOP inst ruct ion. The l ower 12-
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the
second word of the instru ction is exe cuted by it self (first
word was skip ped), it will exec ute as a NOP. This actio n
is necessary when the two-word instruction is preceded
by a co nditional instruc tion that c hanges t he PC. A p ro-
gram ex ample tha t demonstrate s this conc ept is show n
in Example 4-3. Refer to Section 19. 0 for further detail s
of the instruction set.
EXAMPLE 4-3: TWO-WORD INSTRUCTIONS
4.8 Lookup Tables
Lookup tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1 COMPUTED GO TO
A comput ed GOTO is a ccom pli shed by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table, before
execut ing a c al l to tha t table . Th e fi rst ins tru cti on of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions that returns the value 0xnn to the calling
function.
The of fset value (va lue in WREG) specifie s the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
4.8.2 TABLE READS/TABLE WRITES
A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored 2 bytes per program
word by usin g ta ble read s and writes . The t abl e point er
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 5.0.
CASE 1:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; No, execute 2-word instruction
1111 0100 0101 0110 ; 2nd operand holds address of REG2
0010 0100 0000 0000 ADDWF REG3 ; continue code
CASE 2:
Object Code Source Code
0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?
1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes
1111 0100 0101 0110 ; 2nd operand becomes NOP
0010 0100 0000 0000 ADDWF REG3 ; continue code
PIC18CXX2
DS39026D-page 42 1999-2013 Microchip Technology Inc.
4.9 Data Memory Organiz ation
The data memory is impl eme nte d as st a tic RAM . Eac h
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
and Figure 4-7 show the data memory organ iz atio n for
the PIC18CXX2 devices.
The data memory map is divided into as many as 16
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed . The upper 4 bit s for the BSR are
not imple mente d.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and per ipheral functio ns, while GP Rs are used for dat a
storage an d sc ratc h p ad operatio ns in the us er’s appl i-
cation. The SFRs start at the last location of Bank 15
(0xFFF) and extend downwards. Any remaining space
beyond the SFRs in the Bank may be implemented as
GPRs. GPRs start at the first location of Bank 0 and
grow up w ards. An y re ad of a n un im pl em ente d l oc atio n
will read as ’0’s.
The entire data memory may be accessed directly, or
indirec tly. Direc t add res sing m ay requ ire th e us e of th e
BSR register. Indirect addressing requires the use of a
File Sel ect Regis ter (FSRn) and correspondi ng Indirec t
File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The instruction set and architecture allow operations
across all ba nks. This may be accom plished by ind irect
address in g or b y th e us e of t he MOVFF instruction. The
MOVFF instruction is a two-word/two-cycle instruction
that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is imp lemented. A segm ent of Bank 0 and a segm ent of
Bank 15 comprise the Access RAM. Section 4.10 pro-
vides a detailed description of the Access RAM.
4.9.1 GENERAL PURPOSE REGISTER
FILE
The registe r file can be accesse d eith er directly, or indi-
rectly. Indirect addressing operates using the File
Select Registers (FSRn) and corresponding Indirect
File Operand (INDFn). The operation of indirect
addressing is shown in Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as GPR registers by all
ins truct io ns. The top ha lf of bank 15 (0xF 80 t o 0xFFF )
cont ains S FRs. All oth er banks of data memo ry cont ain
GPR registers, starting with bank 0.
4.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-1 and Table 4-2.
The SFRs can be classified into two sets ; those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this sec tio n, w hil e tho se rel ate d
to the operation of the peripheral features are
describ ed in the se ction of that peripheral feature.
The SFR s are t ypic ally d istribute d amo ng the per ipher-
als whose functions they control.
The unused SFR locations will be unimplemented and
read as '0's. Se e Table 4-1 for address es fo r the SFRs .
1999-2013 Microchip Technology Inc. DS39026D-page 43
PIC18CXX2
FIGURE 4-6: DATA MEMORY MAP FOR PIC18C242/442
Bank 0
Bank 1
Bank 14
Bank 15
Data Me mo r y Map
BSR<3:0>
= 0000b
= 0001b
= 1111b
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
F7Fh
F00h
EFFh
1FFh
100h
0FFh
000h
Access RAM
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
SFR
Unused
Access RAM high
Access RAM low
Bank 2
to
200h
Unused
Read ’00h’
= 1110b
= 0010b (SFR’s)
PIC18CXX2
DS39026D-page 44 1999-2013 Microchip Technology Inc.
FIGURE 4-7: DATA MEMORY MAP FOR PIC18C252/452
Bank 0
Bank 1
Bank 14
Bank 15
Data Me mo r y Map
BSR<3:0>
= 0000b
= 0001b
= 1110b
= 1111b
080h
07Fh
F80h
FFFh
00h
7Fh
80h
FFh
Access Bank
When a = 0,
the BSR is ignored and the
Access Bank is used.
The first 128 bytes are General
Purpose RAM (from Bank 0).
The second 128 bytes are
Special Function Registers
(from Bank 15).
When a = 1,
the BSR is used to specify the
RAM location that the instruc-
tion uses.
Bank 4
Bank 3
Bank 2
F7Fh
F00h
EFFh
3FFh
300h
2FFh
200h
1FFh
100h
0FFh
000h
= 0110b
= 0101b
= 0011b
= 0010b
Access RAM
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
FFh
00h
GPR
GPR
GPR
GPR
SFR
Unused
Access RAM high
Access RAM low
Bank 5
GPR
GPR
Bank 6
to
4FFh
400h
5FFh
500h
600h
Unused
Read ’00h’
= 0100b
(SFR’s)
1999-2013 Microchip Technology Inc. DS39026D-page 45
PIC18CXX2
TABLE 4-1: SPECIAL FUNCTION REGISTER MAP
FFFh TOSU FDFh INDF2(3) FBFh CCPR1H F9Fh IPR1
FFEh TOSH FDEh POSTINC2(3) FBEh CCPR1L F9Eh PIR1
FFDh TOSL FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1
FFCh STKPTR FDCh PREINC2(3) FBCh CCPR2H F9Ch —
FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh —
FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah —
FF9h PCL FD9h FSR2L FB9h —F99h—
FF8h TBLPTRU FD8h STATUS FB8h —F98h—
FF7h TBLPTRH FD7h TMR0H FB7h —F97h—
FF6h TBLPTRL FD6h TMR0L FB6h —F96hTRISE
(2)
FF5h TABLAT FD5h T0CON FB5h —F95hTRISD
(2)
FF4h PRODH FD4h —FB4h—F94hTRISC
FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB
FF2h INTCON FD2h LVDCON FB2h TMR3L F92h TRISA
FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h —
FF0h INTCON3 FD0h RCON FB0h —F90h—
FEFh INDF0(3) FCFh TMR1H FAFh SPBRG F8Fh —
FEEh POSTINC0(3) FCEh TMR1L FAEh RCREG F8Eh —
FEDh POSTDEC0(3) FCDh T1CON FADh TXREG F8Dh LATE(2)
FECh PREINC0(3) FCCh TMR2 FACh TXSTA F8Ch LATD(2)
FEBh PLUSW0(3) FCBh PR2 FABh RCSTA F8Bh LATC
FEAh FSR0H FCAh T2CON FAAh —F8AhLATB
FE9h FSR0L FC9h SSPBUF FA9h —F89hLATA
FE8h WREG FC8h SSPADD FA8h —F88h—
FE7h INDF1(3) FC7h SSPSTAT FA7h —F87h—
FE6h POSTINC1(3) FC6h SSPCON1 FA6h —F86h—
FE5h POSTDEC1(3) FC5h SSPCON2 FA5h —F85h—
FE4h PREINC1(3) FC4h ADRESH FA4h —F84hPORTE
(2)
FE3h PLUSW1(3) FC3h ADRESL FA3h —F83hPORTD
(2)
FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC
FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB
FE0h BSR FC0h —FA0hPIE2F80hPORTA
Note 1: Unimplemented registers are read as ’0’.
2: This register is not available on PIC18C2X2 devices.
3: This is not a physical register.
PIC18CXX2
DS39026D-page 46 1999-2013 Microchip Technology Inc.
TABLE 4-2: REGISTER FILE SUMMARY
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR,
BOR
Details
on page:
TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>) ---0 0000 37
TO SH Top-of-Stack High Byte (T OS<15:8>) 0000 0000 37
TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 37
STKPTR STKFUL STKUNF — Return Stack Pointer 00-0 0000 38
PCLATU — — — Hold ing R egist er for PC< 20: 16> ---0 0000 39
PCLATH H old ing R egist er for PC< 15: 8> 0000 0000 39
PCL PC Low Byte (PC<7:0>) 0000 0000 39
TBLPTRU ——bit21
(2) Program Memory Table Pointer Upper Byte (TBLP TR<20:16>) ---0 0000 57
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 57
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 57
TABLAT P rogram Memory Table Latch 0000 0000 57
PRODH Product Register High Byte xxxx xxxx 61
PRODL Product Register Low Byte xxxx xxxx 61
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 65
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP1111 -1-1 66
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 67
INDF0 Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) N/A 50
POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical reg ister) N/A 50
POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) N/A 50
PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) N/A 50
PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) -
value of FSR0 offset by value in WREG N/A 50
FSR0H — — — — Indirect Data Memory Address Pointer 0 High Byte ---- 0000 50
FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx 50
WREG Wor ki ng Register xxxx xxxx
INDF1 Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) N/A 50
POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical reg ister) N/A 50
POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) N/A 50
PREINC1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) N/A 50
PLUSW1 Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) -
value of FSR1 offset by value in WREG N/A 50
FSR1H — — — — Indirect Data Memory Address Pointer 1 High Byte ---- 0000 50
FSR1L Indirect Data Memory Address Pointer 1 Low Byte xxxx xxxx 50
BSR — — — — Bank Select Register ---- 0000 49
INDF2 Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) N/A 50
POSTINC2 Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical reg ister) N/A 50
POSTDEC2 Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) N/A 50
PREINC2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) N/A 50
PLUSW2 Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) -
value of FSR2 offset by value in WREG N/A 50
FSR2H — — — — Indirect Data Memory Address Pointer 2 High Byte ---- 0000 50
FSR2L Indirect Data Memory Address Pointer 2 Low Byte xxxx xxxx 50
STATUS — — —NOVZDCC---x xxxx 52
TMR0H Timer0 Register High Byte 0000 0000 95
TMR0L Timer0 Register Low Byte xxxx xxxx 95
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 93
OSCCON — — — — — — —SCS---- ---0 20
LVDCON —— IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 175
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
1999-2013 Microchip Technology Inc. DS39026D-page 47
PIC18CXX2
WDTCON — — — — — — —SWDTE---- ---0 183
RCON IPEN LWRT —RITO PD POR BOR 0q-1 11qq 53, 56,
74
TMR1H Timer1 Register High Byte xxxx xxxx 97
TMR1L Timer1 Register Low Byte xxxx xxxx 97
T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 97
TMR2 Timer2 Register 0000 0000 101
PR2 Timer2 Period Register 1111 1111 102
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 101
SSPBUF SSP Receive Buffer/Transmit Register xxxx xxxx 121
SSPADD SSP Address Register in I2C Slave Mode. SSP Baud Rate Reload Register in I2C Master Mode. 0000 0000 128
SSPSTAT SMP CKE D/A PSR/WUA BF 0000 0000 116
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 118
SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 120
ADRESH A/D Result Register High Byte xxxx xxxx 171,172
ADRESL A/D Result Register Low Byte xxxx xxxx 171,172
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 165
ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 166
CCPR1H Capture/Compare/PWM Register1 High Byte xxxx xxxx 111, 113
CCPR1L Capture/Compare/PWM Register1 Low Byte xxxx xxxx 111, 113
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 107
CCPR2H Capture/Compare/PWM Register2 High Byte xxxx xxxx 111, 113
CCPR2L Capture/Compare/PWM Register2 Low Byte xxxx xxxx 111, 113
CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 107
TMR3H Timer3 Register High Byte xxxx xxxx 103
TMR3L Timer3 Register Low Byte xxxx xxxx 103
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 103
SPBRG USART1 Baud Rate Generator 0000 0000 151
RCREG USART1 Receive Register 0000 0000 158, 161,
163
TXREG USART1 Transmit Register 0000 0000 156, 159,
162
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 149
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 150
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR,
BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
PIC18CXX2
DS39026D-page 48 1999-2013 Microchip Technology Inc.
IPR2 — — — — BCLIP LVDIP TMR3IP CCP2IP ---- 1111 73
PIR2 — — — — BCLIF LVDIF TMR3IF CCP2IF ---- 0000 69
PIE2 — — — — BCLIE LVDIE TMR3IE CCP2IE ---- 0000 71
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 72
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 68
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 70
TRISE IBF OBF IBOV PSPMODE — Data Direction bits for PORTE 0000 -111 88
TRISD Data Direction Control Register for PORTD 1111 1111 85
TRISC Data Direction Control Register for PORTC 1111 1111 83
TRISB Data Direction Control Register for PORTB 1111 1111 80
TRISA — TRISA6(1) Data Direction Control Register for PORTA -111 1111 77
LATE — — — — — Read PORTE Data Latch ,
Write PORTE Data Latch ---- -xxx 87
LATD Read PORTD Data Latch, Write PORTD Data Latch xxxx xxxx 85
LATC Read PORTC Data Latch, Write PORTC Data Latch xxxx xxxx 83
LATB Read PORTB Data Latch, Write PORTB Data Latch xxxx xxxx 80
LATA —LATA6
(1) Read PORTA Data Latch, Write PORTA Data Latch(1) -xxx xxxx 77
PORTE Read PORTE pins, Write PORTE Data Latch ---- -000 87
PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 85
PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 83
PORTB Read PORTB pins, Write PORTB Data Latch xxxx xxxx 80
PORTA —RA6
(1) Read PORTA pins, Write PORTA Data Latch(1) -x0x 0000 77
TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED)
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR,
BOR
Details
on page:
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO oscillator mode only, and read '0' in all other oscillator modes.
2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
1999-2013 Microchip Technology Inc. DS39026D-page 49
PIC18CXX2
4.10 Access Bank
The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Comm on va riab les
• Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFRs) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-6
and Figure 4-7 indicate the Access RAM areas.
A bit in the instruc tio n w ord sp ec ifie s if the operation is
to occur i n the bank sp ec ifi ed by the BSR regis ter o r in
the Access Bank. This bit is denoted by the ’a’ bit (for
access bit).
When forced in the Access Bank (a = ’0’), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers, so that these registers
can be accessed without any software overhead. This
is useful for testing status flags and modifying control
bits.
4.11 Bank Select Register (BSR)
The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
A MOVLB instruction has been prov ided in the instruc-
tion set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits w il l be s et/c le ared as ap prop ria te
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF ins tructi on ig nores the BS R, sin ce th e 12-bi t
addresses are embedded into the instruction word.
Section 4.12 provi des a descriptio n of indirect a ddress-
ing, which allows linear addressing of the entire RAM
space.
FIGURE 4-8: DIRECT ADDRESSING
Note 1: For register file map detail, see Table 4-1.
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the reg-
isters of the Access Bank.
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
Data
Memory(1)
Direct Addres sing
Bank Select(2) Location Select(3)
BSR<3:0> 7 0
From Opcode(3)
00h 01h 0Eh 0Fh
Bank 0 Bank 1 Bank 14 Bank 15
1FFh
100h
0FFh
000h
EFFh
E00h
FFFh
F00h
PIC18CXX2
DS39026D-page 50 1999-2013 Microchip Technology Inc.
4.12 Indirect Addressing, INDF and
FSR Registers
Indir ect addressing is a mod e of addressing dat a mem-
ory, where the data memory address in the instruction
is not fi xe d. An FSR reg is ter i s u se d as a poi nte r to th e
data memory locat ion that is to b e read or written. Since
this poi nter i s in RAM, the con ten t s c an be mo difi ed by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the F SR register.
Indirect addressing is possible by using one of the
INDF regi sters. Any ins tru cti on u si ng the IN DF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirec tly (FSR = '0'), wi ll read 00 h. Writing to the IND F
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer) . This is indirect addressing.
Exampl e 4-4 shows a s imple use o f indirect add ressing
to clear the RAM in Bank1 (locations 100h-1FFh) in a
minimum number of instructions.
EXAMPLE 4-4: HOW TO CLEAR RAM
(BANK1) USING INDIRECT
ADDRESSING
There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bit wide. To store the 12-bits of
addressing information, two 8-bit registers are
required . These indire ct addressing regi ste rs are:
1. FSR0: composed of FSR0H:FSR0L
2. FSR1: composed of FSR1H:FSR1L
3. FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data.
If an instruction writes a value to INDF0, the value will
be wri tte n t o the address po int ed to by FSR0H:FSR0L.
A read from INDF1 reads the data from the address
pointed to by FSR1H:FSR1L. INDFn can be used in
code anywhere an operand can be used.
If INDF0, INDF1 or INDF2 are read indirectly via an
FSR, all '0's are read (zero bit is set). Similarly, if
INDF0, INDF1 or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
STATUS bits are not affected.
4.12.1 INDIRECT ADDRESSING
OPERATION
Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
• Do nothing to FSRn after an indirect access (no
change) - INDFn
• Auto-d ecrem ent FSRn after an indirect access
(post-decrement) - POSTDECn
• Auto-increm ent FSRn after an indirect access
(post-increment) - POSTINCn
• Auto-increment FSRn before an indirect access
(pre-increment) - PREINCn
• Use the value in the WREG register as an offset
to FSRn . Do not modif y the va lue of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn
When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stac k pointer, in addition to its uses for tab le operation s
in da ta memory.
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configu r ed to add th e s ig ned v alu e in the WREG re gis -
ter and th e v alu e i n F S R to f orm the add res s befo re a n
indirect access. The FSR value is not changed.
If an FSR regist er conta ins a value that poin ts to one of
the INDFn, an indirect read will read 00h (zero bit is
set) , wh ile an i ndir ect wri te w ill be eq uiv ale nt t o a NOP
(STATUS bits are not af fec ted ).
LFSR FSR0, 0x100 ;
NEXT CLRF POSTINC0 ; Clear INDF register
; & inc pointer
BTFSS FSR0H, 1 ; All done w/ Bank1?
GOTO NEXT ; NO, clear next
CONTINUE ; YES, continue
1999-2013 Microchip Technology Inc. DS39026D-page 51
PIC18CXX2
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or post-
increment/decrement functions.
FIGURE 4-9: INDIRECT ADDRESSING OPERATION
FIGURE 4-10: INDIRECT ADDRESSING
Opcode Address
File Address = access of an indirect addressing register
FSR
Instruction
Executed
Instruction
Fetched
RAM
Opcode File
12
12
12
BSR<3:0>
8
4
0h
FFFh
Note 1: For register file map detail, see Table 4-1.
Data
Memory(1)
Indirect Addressing
FSR Register11 0
0FFFh
0000h
Location Select
PIC18CXX2
DS39026D-page 52 1999-2013 Microchip Technology Inc.
4.13 STATUS Register
The STATUS register, shown in Register 4-2, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an ins truction that af fects the Z, DC, C, OV or N bit s,
then the write to these five bits is disabled. These bits
are set or cl eare d a ccording to th e d ev ice l ogi c. The r e-
fore, the resul t of a n ins tructi on with the STATUS regis-
ter as destination may be different than intended.
For example, CLRF STATUS will clear the upper three
bits and set t he Z bit. T his leav es the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alte r the STATU S regi ster, be cause t hese i nstruc tions
do not affect the Z, C, DC, OV or N bits from the
STATUS register. For other instructions not affecting
any status bits, see Table 19-2.
REGISTER 4-2: STATUS REGISTER
Note: The C and DC bits ope rate as a borrow and
digit borrow bit respectively, in subtraction.
U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x
— — —NOVZDCC
bit 7 bit 0
bit 7-5 Unimplemented: Read as '0'
bit 4 N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative, (ALU MSB = 1).
1 = Result was negative
0 = Result was positive
bit 3 OV: Overfl ow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude, which causes the sign bit (bit7) to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operatio n is zer o
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructi on s, thi s bit is
loaded with either the bit 4 or bit 3 of the source register.
bit 0 C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructi on s, thi s bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 53
PIC18CXX2
4.13.1 RCON REGISTER
The Reset Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bi ts. Thi s register is re adable an d writ able.
.
REGISTER 4-3: RCON REGISTER
Note 1: If the BOREN configuration bit is set
(Brown-out Res et enabled), the BOR bi t is
’1’ on a Power-on Reset. After a Brown-
out Reset has occurred, the BOR bit will
be clear and must be set by firmware to
indicat e the occurrence of the next Brown-
out Reset.
If the BOREN configuration bit is clear
(Brown-out Reset disabled), BOR is
unknown after Power-on Reset and
Brown-out Reset conditions.
2: It is re commended that the PO R bit be set
after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT : Long Wr ite Enable bit
1 = Enable TBLWT to internal program memory
Once this bit is set, it can only be cleared by a POR or MCLR Reset.
0 = Disable TBLWT to internal program memory; TBLWT only to external program memory
bit 5 Unimplemented: Read as '0'
bit 4 RI: RESET Instruction Flag bit
1 = The RESET instructi on wa s not ex ecu ted
0 = The RESET instruction was executed causing a device RESET
(must be set in software after a Brown-out Reset occurs)
bit 3 TO: Watchdog Time-out Flag bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 2 PD: Power -down Dete ction Flag bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = A Power-on Reset has not occurred
0 = A Power-on Reset occurred
(must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = A Brown-out Reset has not occurred
0 = A Brown-out Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 54 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 55
PIC18CXX2
5.0 TABLE READS/TABLE WRITES
Enhanced devices have two memory spaces: the pro-
gram memory space and the data memory space. The
program memory space is 16-bits wide, while the data
memory space is 8 bits wide. Table Reads and Table
Writes have been provided to move data between
these two memory spaces through an 8-bit register
(TABLAT).
The operations that allow the processor to move data
between the data and program memory spaces are:
• Table Read (TBLRD)
• Table Write (TBLWT)
Table Read operations retrieve data from program
memory and place it into the data memory space.
Figure 5-1 shows the operation of a Table Read with
program and data memory.
Table Write operations store data from the data mem-
ory space into program memory. Figure 5-2 shows the
operation of a Table Write with program and data
memory.
Table operations work with byte entities. A table block
cont aining dat a is not requ ired to be word a ligned , so a
table block can start and end at any byte address. If a
Table Write is being used to write an executable pro-
gram to program memory, program instructions will
need to be word aligned.
FIGURE 5-1: TABLE READ OPERATION
FIGURE 5-2: TABLE WRITE OPERATION
Table Pointer(1) Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL TABLAT
TBLPTRU
Instruction: TBLRD*
Note 1: Table Pointer point s to a byte in program memory.
Program Memory
(TBLPTR)
Table Pointer(1) Table Latch (8-bit)
Program Memory
TBLPTRH TBLPTRL TABLAT
Program Memory
(TBLPTR)
TBLPTRU
Instruction: TBLWT*
Note 1: Table Pointer points to a byte in program memory.
PIC18CXX2
DS39026D-page 56 1999-2013 Microchip Technology Inc.
5.1 Control Registers
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• TBLPTR registers
• TABLAT register
• RCON register
5.1.1 RCON REGISTER
The LWRT bit specifies the operation of Table Writ es to
internal me mory when the VPP v olt age i s app lied t o the
MCLR pin. When the LWRT bit is set, the controller
continues to execute user code, but long Table Writes
are allowed (for programming internal program mem-
ory) f rom user mo de. The LWRT bi t can be cl eared only
by performing either a POR or MCLR Reset.
REGISTER 5-1: RCON REGISTER (ADDRESS: FD0h)
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT: Long Write Enable bit
1 = Enable TBLWT to internal program memory
0 = Disable TBLWT to internal program memory.
Note: Only cleared on a POR or MCLR Reset.
This bit has no effect on TBLWTs to exter nal pr ogram mem ory.
bit 5 Unimplemented: Read as '0'
bit 4 RI: RESET Instruction Flag bit
1 = No RESET instruction occurred
0 = A RESET instruction occurred
bit 3 TO: Time-out bit
1 = After power-up, CLRWDT instructi on, or SLEEP in struction
0 = A WDT time-out occurred
bit 2 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset or POR Reset occurred
0 = A B rown-out Reset or POR Reset occurred
(must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is un known
1999-2013 Microchip Technology Inc. DS39026D-page 57
PIC18CXX2
5.1.2 TABLAT - TABLE LATCH REGISTER
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data memory.
5.1. 3 TBLPTR - TABLE POINTER
REGISTER
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper Byte, High
Byte and Low Byte). These three registers
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit
wide pointer. The lower 21-bits allow the device to
address up to 2 Mbytes of program memory sp ace. The
22nd bit allows access to the Device ID, the User ID
and the Configuration bits.
The Table Pointer, TBLPTR, is used by the TBLRD and
TBLWT instructions. These instructions can update the
TBLPTR in one of four ways, based on the table operation.
These operations are shown in Table 5-1. These opera-
tions on the TBLPTR only affec t the lower 21-bits.
TABLE 5-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
5.2 Internal Program Memory Read/
Writes
5.2.1 TABLE READ OVERVIEW (TBLRD)
The TBLRD instructions are used to read data from
program memory to data memory.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into TAB-
LAT. In addition, TBLPTR can be modified automati-
cally for the next Table Read operation.
Table Reads fr om pro gram m emory are perform ed on e
byte at a time. The instruction will load TABLA T with th e
one byte fro m program memory pointe d to by TBLPTR.
5.2.2 INTERNAL PROGRAM MEMORY
WRITE BLOCK SIZE
The internal program memory of PIC18CXXX devices
is wri tten in bl ocks . For PIC1 8CXX2 devi ces , the wr ite
block s ize is 2 bytes. Con seque ntly, Table Writ e opera-
tions to internal program memory are performed in
pairs, one byte at a time.
When a Table Write occurs to an even program mem-
ory ad dress (TBLPTR<0> = 0) , the content s of T ABLAT
are transferred to an internal holding register. This is
performed as a short write and the program memory
block i s not actual ly programmed a t this time. T he hold-
ing register is not accessible by the user.
When a Tabl e W rite oc curs to an od d p rogram memor y
address (TBLPTR<0>=1), a long write is started. Dur-
ing the long write, the contents of TABLAT are written
to the high byte of the program memory block and the
contents of the holding register are transferred to the
low byte of the program memory block.
Figure 5-3 shows the holding register and the program
memory write blo cks.
If a single byte is to be programmed, the low (even)
byte of the destination program word should be read
using TBLRD*, modified or changed, if required, and
written bac k to th e same add res s using TBLWT*+. The
high (odd ) byte should be read using TBLRD*, modi fied
or changed if required, and written back to the same
address using TBLWT. A write to the odd address will
cause a long write to begin. This process ensures that
existing data in either byte will not be changed unless
desired.
Example Operation on Table Pointer
TBLRD*
TBLWT* TBLPTR is not modified
TBLRD*+
TBLWT*+ TBLPTR is incremented after the read/write
TBLRD*-
TBLWT*- TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+* TBLPTR is incremented before the read/write
PIC18CXX2
DS39026D-page 58 1999-2013 Microchip Technology Inc.
FIGURE 5-3: HOLDING REGISTER AND THE WRITE BLOCK
5.2.2.1 Operation
The long w ri te is wh at a ctu all y pro gra ms words of da t a
into the i nternal me mory. When a TBLWT to th e MSB of
the write block occurs, instruction execution is halted.
During this time, programming voltage and the data
stored in internal latches is applied to program memory .
For a long write to occur:
1. MCLR/VPP pin must be at the programming
voltage
2. LWRT bit must be set
3. TBLWT to the address of the MSB of the write
block
If the LWRT bi t is c lear, a short wr ite will occu r and p ro-
gram memory will not be changed. If the TBLWT is not
to the MSB of the write block, then the programming
phase is not initiated.
Setting the LWRT bit enables long writes when the
MCLR pin is taken to VPP voltage. Once the LWRT bit
is set, it can be cleared only by performing a POR or
MCLR Reset.
To ensure that the mem ory lo ca tion has been w el l pro-
grammed, a minimum programming time is required.
The long write can be terminated after the program-
ming time has expired by a RESET or an interrupt.
Havi ng only one int errupt sourc e enabl ed to ter minat e
the long write ensures that no uninte nded interrupt s will
prematurely terminate the long write.
5.2.2.2 Sequence of Events
The sequence of events for programming an internal
program memory location should be:
1. Enable the interrupt that terminates the long
write. Disable all other interrupts.
2. Clear the source interrupt flag.
3. If Interrupt Service Routine execution is desired
when the device wakes, enable global
interrupts.
4. Set LWRT bit in the RCON register.
5. Raise MCLR/VPP pin to the programming
voltage, VPP.
6. Clear the WDT (if enabled).
7. Set the interrupt source to interrupt at the
required tim e.
8. Execute the Table Write for the lower (even)
byte. This will be a short write.
9. Execute the Table Write for the upper (odd) byte.
This w ill be a lon g w rit e. Th e m ic roc ontroller will
then halt internal operations. (This is not the
same as SLEEP mode, as the clocks and
peripherals will continue to run.) The interrupt
will cause the microcontroller to resume
operation.
10. If GIE was set, service the interrupt request.
11. Lower MCLR/VPP pin to VDD.
12. Verify the memory location (Table Read).
Block n
Block n + 1
Block n + 2
MSB
The write to the MSB of the Write Block
causes the entire block to be written to pro-
gram memory. The program memory block
that is written depends on the address that is
written to in the MSB of the Write Block.
Holding Register
Program Memory (x 2-bits)
Write Block
1999-2013 Microchip Technology Inc. DS39026D-page 59
PIC18CXX2
5.2.3 INTERRUPTS
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur, regardless of the
settings of interrupt priority bits, the GIE/GIEH bit, or
the PIE/GIEL bit.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
T ABLE 5-2: LONG WRITE EXECUTION, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
5.2.4 UNEXPECTED TERMINATION OF
WRITE OPERATIONS
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
GIE/
GIEH PIE/
GIEL Priority Interrupt
Enable Interrupt
Flag Action
XX X 0
(default) XLo ng w rite continues
even if interrupt flag becomes set.
XX X 1 0
Long write continues, will resume operations
when the interrupt flag is set.
0
(default) 0
(default) X11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default) 11
high priority
(default) 11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
10
(default) 0
low 11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default) 10
low 11
Terminates long write,
branches to low priority interrupt vector.
Interrupt flag can be cleared by ISR.
10
(default)
1
high priority
(default) 11
Terminates long write,
branches to high priority interrupt vector.
Interrupt flag can be cleared by ISR.
PIC18CXX2
DS39026D-page 60 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 61
PIC18CXX2
6.0 8 X 8 HARDWARE MULTIPLIER
6.1 Introduction
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18CXX2 devices. By making the multiply a
hardwa re o pera t io n, i t co mp letes in a single i ns truc tio n
cycle. This is an unsigned multiply that gives a 16-bit
result. Th e resul t is store d into th e 16-bit produ ct regi s-
ter pair (PRODH:PRODL). The multiplier does not
affect any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following adv antages:
• Higher computational throughput
• Reduc es code siz e requ irem en t s for multip ly
algorithms
The performance incre ase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 6-1 shows a performance comparison between
enhance d devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.
TABLE 6-1: PERFORMANCE COMPARISON
6.2 Operation
Example 6-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one arg um ent of the multiply is al rea dy lo ade d i n
the WREG register.
Exampl e 6-2 shows the sequence t o do an 8 x 8 signed
multi ply. To acco unt for t he si gn bits o f th e argu men ts,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 6-1: 8 x 8 UNSIGNED
MULTIPLY ROUTINE
EXAMPLE 6-2: 8 x 8 SIGNED MULTIPLY
ROUTINE
Example 6-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 6-1 shows the algorithm
that is us ed. The 32-b it result is stored in fo ur registers,
RES3:RES0.
EQUATION 6-1: 16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)
Routine Multiply Method Program
Memory
(Words)
Cycles
(Max)
Time
@ 40 MHz @ 10 MHz @ 4 MHz
8 x 8 unsigned Without hardware multiply 13 69 6.9 s27.6 s69 s
Hardware mu lti ply 1 1 100 ns 400 ns 1 s
8 x 8 signed Without hardware multiply 33 91 9.1 s36.4 s91 s
Hardware mu lti ply 6 6 600 ns 2.4 s6 s
16 x 16 unsigned Without hardware multiply 21 242 24.2 s96.8 s242 s
Hardware mu lti ply 24 24 2.4 s9.6 s24 s
16 x 16 signed Without hardware multiply 52 254 2 5.4 s 102.6 s254 s
Hardware mu lti ply 36 36 3.6 s14.4 s36 s
MOVF ARG1, W ;
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
MOVF ARG1, W
MULWF ARG2 ; ARG1 * ARG2 ->
; PRODH:PRODL
BTFSC ARG2, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG1
MOVF ARG2, W
BTFSC ARG1, SB ; Test Sign Bit
SUBWF PRODH, F ; PRODH = PRODH
; - ARG2
PIC18CXX2
DS39026D-page 62 1999-2013 Microchip Technology Inc.
EXAMPLE 6- 3: 16 x 16 UNSIGNED
MULTIPLY ROUTINE
Example 6-4 shows the sequence to do a 16 x 16
signed multiply. Equation 6-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ment s, each argum ent p ai rs’ M ost S ign ificant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 6-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
RES3:RES0
= ARG1H:ARG1L ARG2H:ARG2L
= (ARG1H ARG2H 216)+
(ARG1H ARG2L 28)+
(ARG1L ARG2H 28)+
(ARG1L ARG2L)+
(-1 ARG2H<7> ARG1H:ARG1L 216)+
(-1 ARG1H<7> ARG2H:ARG2L 216)
EXAMPLE 6-4: 16 x 16 SIGNED
MU LTIPLY ROUTINE
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
MOVF ARG1L, W
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVFF PRODH, RES1 ;
MOVFF PRODL, RES0 ;
;
MOVF ARG1H, W
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVFF PRODH, RES3 ;
MOVFF PRODL, RES2 ;
;
MOVF ARG1L, W
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVF ARG1H, W ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVF PRODL, W ;
ADDWF RES1, F ; Add cross
MOVF PRODH, W ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
BRA SIGN_ARG1 ; no, check ARG1
MOVF ARG1L, W ;
SUBWF RES2 ;
MOVF ARG1H, W ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
BRA CONT_CODE ; no, done
MOVF ARG2L, W ;
SUBWF RES2 ;
MOVF ARG2H, W ;
SUBWFB RES3
;
CONT_CODE
:
1999-2013 Microchip Technology Inc. DS39026D-page 63
PIC18CXX2
7.0 INTERRUPTS
The PIC18CXX2 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high priority
level, or a low priority level. The high priority interrupt
vector is at 000008h and the low priority interrupt vector
is at 000018h. High priority interrupt events will over-
ride any low priority interrupts that may be in progress.
There are ten registers which are used to control inter-
rupt operation. These registers are:
• RCON
•INTCON
• INTCON2
• INTCON3
• PIR1, PIR2
• PIE1, PIE2
• IPR1, IPR2
It is recommended that the Microchip header files sup-
plied with MPLAB® IDE be used for the symbolic bit
names in these registers. This allows the assembler/
compil er to automa tical ly ta ke care of the pla ceme nt of
these bits within the specified register.
Each interrupt source has three bits to control its oper-
ation. The functions of these bits are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled , th ere are two bit s w hich e nab le in terrupt s gl o-
bally. Setting the GIEH bit (INTCON<7>) enables all
interr upts tha t have the prior ity bit set. Sett ing the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
inter rupt will vec tor imm ediat ely to addre ss 00000 8h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are com-
patible with PIC® mid-range devices. In Compatibility
mode, th e interrupt priori ty bits fo r each source hav e no
effect. INTCON<6> is the PEIE bit, which enables/dis-
ables all peripheral interrupt sources. INTCON<7> is
the GIE bit, which enables/disables all interrupt
sources. All interrupts branch to address 000008h in
Compatibility mode.
When an i nte rrupt is responded to , t he G lob al In terru pt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is clear ed, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH, or GIEL bit.
High pr iori ty i nte rrupt so urc es c an int errupt a low pri or-
ity interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bit s must be cleared in softw are before re-e nabling
interrupts to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrup t routine and set s the GIE bit (GIEH or GI EL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the POR TB input chang e interrupt, the i nterrupt latenc y
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.
PIC18CXX2
DS39026D-page 64 1999-2013 Microchip Technology Inc.
FIGURE 7-1: INTE RRUP T LOGIC
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in SLEEP mode
Interrupt to CPU
Vector to location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
INT0IF
INT0IE
RBIF
RBIE
RBIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
INT0IF
INT0IE
GIEL\PEIE
Interrupt to CPU
Vector to Location
IPEN
IPE
0018h
Periphera l Inter rupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Peripheral Interrupt Flag bit
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
TMR1IF
TMR1IE
TMR1IP
XXXXIF
XXXXIE
XXXXIP
Additional Peripheral Interrupts
TMR1IF
TMR1IE
TMR1IP
High Priority Interrupt Generation
Low Priority Interrupt Generation
XXXXIF
XXXXIE
XXXXIP
Additional Peripheral Interrupts
1999-2013 Microchip Technology Inc. DS39026D-page 65
PIC18CXX2
7.1 INTCON Registers
The INTCON Registers are readable and writable reg-
isters, which contains various enable, priority, and flag
bits.
REGISTER 7-1: INTCON REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
bit 7 bit 0
bit 7 GIE/GIEH: Global Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked interrupts
0 = Disables all interru pts
When IPEN = 1:
1 = Enables all high priority interrupts
0 = Disables all high priority interrupts
bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN = 0:
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
When IPEN = 1:
1 = Enables all low priority peripheral interrupts
0 = Disables all low priority peripheral interrupts
bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overfl ow inte rrupt
bit 4 INT0IE: INT0 External Interrupt Enable bit
1 = Enables the INT0 external interrupt
0 = Disables the INT0 ext erna l inte rrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INT0IF: INT0 External Interrupt Flag bit
1 = The INT0 external interrupt occurred (must be cleared in software)
0 = The INT0 external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of it s correspondi ng enab le bit, or the glo bal enable bit. User sof tware sh ould ensu re
the approp riat e interru pt fla g bit s are clear prior to enabl ing an interru pt. This featu re
allows for software polling.
PIC18CXX2
DS39026D-page 66 1999-2013 Microchip Technology Inc.
REGISTER 7-2: INTCON2 REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1
RBPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP—RBIP
bit 7 bit 0
bit 7 RBPU: POR TB Pull -up Enab le bit
1 = All PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG0:External Interrupt0 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 5 INTEDG1: External Interrupt1 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 4 INTEDG2: External Interrupt2 Edge Select bit
1 = Interrupt on rising edge
0 = Interrupt on falling edge
bit 3 Unimplemented: Read as '0'
bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 Unimplemented: Read as '0'
bit 0 RBIP: RB Port Change Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of it s correspondi ng enab le bit, or the glo bal enable bit. User sof tware sh ould ensu re
the approp riat e interr upt fla g bit s are clear prior to enabl ing an interru pt. This featu re
allows for software polling.
1999-2013 Microchip Technology Inc. DS39026D-page 67
PIC18CXX2
REGISTER 7-3: INTCON3 REGISTER
R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF
bit 7 bit 0
bit 7 INT2IP: INT2 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 INT1IP: INT1 External Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 Unimplemented: Read as '0'
bit 4 INT2IE: INT2 External Interrupt Enable bit
1 = Enables the INT2 external interrupt
0 = Disables the INT2 external interrupt
bit 3 INT1IE: INT1 External Interrupt Enable bit
1 = Enables the INT1 external interrupt
0 = Disables the INT1 external interrupt
bit 2 Unimplemented: Read as '0'
bit 1 INT2IF: INT2 External Interrupt Flag bit
1 = The INT2 external interrupt occurred
(must be cleared in software)
0 = The INT2 external interrupt did not occur
bit 0 INT1IF: INT1 External Interrupt Flag bit
1 = The INT1 external interrupt occurred
(must be cleared in software)
0 = The INT1 external interrupt did not occur
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of it s correspondi ng enab le bit, or the glo bal enable bit. User sof tware sh ould ensu re
the approp riat e interru pt fla g bit s are clear prior to enabl ing an interru pt. This featu re
allows for software polling.
PIC18CXX2
DS39026D-page 68 1999-2013 Microchip Technology Inc.
7.2 PIR Registers
The PIR regi sters c onta in the ind ividu al flag bit s for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are two Peripheral Interrupt
Flag Registers (PIR1, PIR2).
REGISTER 7-4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (PIR1)
Note 1: Interrupt flag bits get s et when an interrupt
conditi on occurs, rega rdless of the s tate of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>).
2: User software s hould ensure the approp ri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or wri te has occurred
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART receive bu ffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART transmit buffer is full
bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mo de:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register cap ture occurred
Compare mode:
1 = A TMR1 r egist er compare match occurred (must be cleare d in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = MR1 register did not overflow
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 69
PIC18CXX2
REGISTER 7-5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (PIR2)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — BCLIF LVDIF TMR3IF CCP2IF
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision occurred (must be cleared in software)
0 = No bus collision occurred
bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit
1 = A low voltage condition occurr ed (mus t be cl eared in software)
0 = The device voltage is above the Low Voltage Detect trip point
bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit
1 = TMR3 register overflowed (must be clea red in software)
0 = TMR3 register did not overflow
bit 0 CCP2IF: CCPx Interru pt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurre d
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 70 1999-2013 Microchip Technology Inc.
7.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Enable Registers (PIE1, PIE2). When IPEN = 0,
the PEIE bit mus t be set to enab le any of the se perip h-
eral interrupts.
REGISTER 7-6: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 PSPIE: Parall el Slav e Port Read/Wri te Interru pt Enab le bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6 ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A /D interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Ov erfl ow Interr upt Enab le bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 71
PIC18CXX2
REGISTER 7-7: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — BCLIE LVDIE TMR3IE CCP2IE
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 BCLIE: Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1 TMR3IE: TMR3 Ov erfl ow Interr upt Enab le bit
1 = Enables the TMR3 overflow interrupt
0 = Disables the TMR3 overflow interrupt
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 72 1999-2013 Microchip Technology Inc.
7.4 IPR Registers
The IPR registers contain the individual priority bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Priority Registers (IPR1, IPR2). The operation of
the priority bits requires that the Interrupt Priority
Enable (IPEN) bit be set.
REGISTER 7-8: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (IPR1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP
bit 7 bit 0
bit 7 PSPIP: Parall el Slav e Port Read/ Write Interrupt Priority bit
1 = High priority
0 = Low priority
bit 6 ADIP: A/D Converter Interrupt Priority bit
1 = High priority
0 = Low priority
bit 5 RCIP: USART Receive Interrupt Priority bit
1 = High priority
0 = Low priority
bit 4 TXIP: USART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 CCP1IP: CCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 73
PIC18CXX2
REGISTER 7-9: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (IPR2)
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
— — — — BCLIP LVDIP TMR3IP CCP2IP
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 BCLIP: Bus Collision Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0 CCP2IP: CCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 74 1999-2013 Microchip Technology Inc.
7.5 RCON Register
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
REGISTER 7-10: RCON REGISTER
R/W-0 R/W-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0
IPEN LWRT —RITO PD POR BOR
bit 7 bit 0
bit 7 IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
bit 6 LWRT : Long Write Enab le bit
For details of bit operation, see Register 4-3
bit 5 Unimplemented: Read as '0'
bit 4 RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-3
bit 3 TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-3
bit 2 PD: Power- down D etection Flag bit
For details of bit operation, see Register 4-3
bit 1 POR: Power-on Reset Status bit
For details of bit operation, see Register 4-3
bit 0 BOR: Brown-out Reset Status bit
For details of bit operation, see Register 4-3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 75
PIC18CXX2
7.6 INT0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and
RB2/INT2 pins are edge triggered: either rising, if the
corresp onding INTEDGx b it is set in the INTCON2 re g-
ister, or falling , if the INTEDGx bit is clear. When a v alid
edge appears on the RBx/INTx pin, the corresponding
flag bit INTxF is set. This interrupt can be disabled by
clearing the corresponding enable bit INTxE. Flag bit
INTxF must be c lea red in sof tware in th e Inte rrupt Ser-
vice Routine before re-enabling the interrupt. All exter-
nal interrupts (INT0, INT1 and INT2) can wake-up the
processor from SLEEP, if bit INTxE was set prior to
going into SLEEP. If the global interrupt enable bit GIE
set, the processor will branch to the interrupt vector
following wake-up.
Interrupt priority for INT1 and INT2 is determined by the
value contained in the interrupt priority bits, INT1IP
(INTCON3<6>) and INT2IP (INTCON3<7>). There is
no priority bit associated with INT0. It is always a high
priority interrupt source.
7.7 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow (FFh
00h) in the TMR0 register will set flag bit TMR0IF. In
16-bit mode, an overflow (FFFFh 0000h) in the
TMR0H:TMR0L registers will set flag bit TMR0IF. The
interrupt can be enabled/disabled by setting/clearing
enable bit T0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit TMR0IP (INTCON2<2>). See Sec-
tion 8.0 for further details on the Timer0 module.
7.8 PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB Interrupt-on-change is
determined by the value contained in the interrupt pri-
ority bit, RBIP (INTCON2<0>).
7.9 Context Saving During Interrupts
During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR regis-
ters are saved on the fast return stack. If a fast return
from interrupt is not used (see Section 4.3), the user
may need to save the WREG, STATU S and BSR regis-
ters in software. Depending on the user’s application,
other registers may also need to be s aved. Example 7-1
saves and restores the WREG, STA TUS an d BSR regis-
ters during an Interrupt Service Routine.
EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF W_TEMP ; W_TEMP is in virtual bank
MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere
MOVFF BSR, BSR_TEMP ; BSR located anywhere
;
; USER ISR CODE
;
MOVFF BSR_TEMP, BSR ; Restore BSR
MOVF W_TEMP, W ; Restore WREG
MOVFF STATUS_TEMP, STATUS ; Restore STATUS
PIC18CXX2
DS39026D-page 76 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 77
PIC18CXX2
8.0 I/O P ORTS
Depen ding on the de vice s elec ted, the re ar e eithe r five
ports, or three ports available. Some pins of the I/O
ports are multiplexed with an alternate function from
the peri pheral features o n t he de vic e. In gene ral, whe n
a peripheral is enabled, that pin may not be used as a
general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
• TRIS register (data direction register)
• POR T register (rea ds the lev els on the pin s of the
device)
• LAT register (output latch)
The da ta l a tc h ( L AT r e gi ste r ) is usef u l f or re a d-modi fy -
write operations on the value that the I/O pins are
driving.
8.1 PORTA, TRISA and LATA
Registers
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA b it (= 1) will make the correspondin g PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the correspon ding POR TA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register reads and writes the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The RA4/
T0CKI pin is a Sch mitt Trigger input and an ope n drain
output. All othe r RA port pins have TTL input lev els and
full CMOS output drivers.
The other PORTA pins are multiplexed with analog
inputs and the analog VREF+ and VREF- inputs. The
operat ion of eac h pin is selected by clear ing/settin g the
control bits in the ADCON1 register (A/D Control
Register1).
The TRISA register controls the direction of the RA
pins, ev en w h en th ey are be ing us ed as ana log inputs.
The user mu st ensure the bit s in the TRISA regi ster are
maintained set whe n using them as anal og inputs.
EXAMPLE 8-1: INITIALI ZING PORTA
FIGURE 8-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Note: On a Pow er-on Reset, these pins are con-
figured as digital inputs.
Note: On a Pow er-on Reset, these pins are con-
figured as analog inputs and read as '0'.
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
CLRF LATA ; Alternate method
; to clear output
; data latches
MOVLW 0x07 ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR LATA
WR TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter and LVD Modules
RD LATA
or
PORTA
SS Input (RA5 only)
PIC18CXX2
DS39026D-page 78 1999-2013 Microchip Technology Inc.
FIGURE 8-2: BLO CK DIAGRAM OF
RA4/T0CKI PIN FIGURE 8-3: BLOCK DIAGRAM OF RA6
Data
Bus
WR TRISA
RD PORTA
Data Latch
TRIS Latch
RD TRISA
Schmitt
Trigger
Input
Buffer
N
VSS
I/O pin(1)
TMR0 Clock Input
QD
Q
CK
QD
Q
CK
EN
QD
EN
RD LATA
WR LATA
or
PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR LATA
WR
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
or
PORTA
RD LATA
ECRA6 or
Data Bus
ECRA6 or
Enable
Data Bus
TTL
Input
Buffer
RCRA6
RCRA6 Enable
TRISA
1999-2013 Microchip Technology Inc. DS39026D-page 79
PIC18CXX2
TABLE 8-1: PORTA FUNCTIONS
TABLE 8-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input.
RA1/AN1 bit1 TTL Input/output or analog input.
RA2/AN2/VREF- bit2 TTL Input/output or analog input or VREF-.
RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+.
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0.
Output is open drain type.
RA5/SS/AN4/LVDIN bit5 TTL Input/output or slave select input for synchronous serial port or analog
input, or low voltage detect input.
OSC2/CLKO/RA6 bit6 TTL OSC2 or clock output or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 V a lue on
POR,
BOR
Value on all
other
RESETS
PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
LATA — Latch A Data Output Register --xx xxxx --uu uuuu
TRISA — PORTA Data Direction Register --11 1111 --11 1111
ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cell s are not us ed by PORTA.
PIC18CXX2
DS39026D-page 80 1999-2013 Microchip Technology Inc.
8.2 PORTB, TRISB and LATB
Registers
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the co rresponding POR TB pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register reads and writes the latched output value for
PORTB.
EXAMPLE 8-2: INITIALIZING PORTB
Each of th e POR TB pins has a we ak inte rnal pul l-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
Four of the PORTB pins, RB7:RB4, have an interrupt-
on-change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
inter rupt in the following manner :
a) Any read or write of PORTB (except with the
MOVFF instruction). This will end the mismatch
condition.
b) Clear flag bit RBIF.
A mism at c h c ond it i on wi ll cont i n ue to s et f lag bi t RB IF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB3 can be configured by the configuration bit
CCP2MX as the alternate peripheral pin for the CCP2
module (CCP2MX = ‘0’).
FIGURE 8-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
Note: On a Pow er-on Reset, these pins are con-
figured as digital inputs.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Data Latch
From other
RBPU(2)
P
VDD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data Bus
WR LATB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PORTB
RB7:RB4 pi ns
Weak
Pull-up
RD PORTB
Latch
TTL
Input
Buffer
pin(1)
ST
Buffer
RBx/INTx Q3
Q1
RD LATB
or
PORTB
Note 1: I/O pins have diode protec tion to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (INTCON2<7>).
1999-2013 Microchip Technology Inc. DS39026D-page 81
PIC18CXX2
FIGURE 8-5: BLOCK DIAGRAM OF RB2:RB0 PINS
FIGURE 8-6: BLOCK DIAGRAM OF RB3
Data Latch
RBPU(2) P
VDD
QD
CK
QD
CK
QD
EN
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
Weak
Pull-up
RD Port
RB0/INT
I/O pin(1)
TTL
Input
Buffer
Schmitt Trigger Buffer
TRIS Latch
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
Data Latch
P
VDD
QD
CK
QD
EN
Data Bus
WR LATB or
WR TRISB
RD TRISB
RD PORTB
Weak
Pull-up
CCP2 Input(3)
TTL
Input
Buffer
Schmitt Trigger
Buffer
TRIS Latch
RD LAT B
WR PORTB
RBPU(2)
CK
D
Enable
CCP Output(3)
RD PORTB
CCP Output(3) 1
0P
N
VDD
VSS
I/O pin(1)
Q
CCP2MX
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3, if the CCP2MX bit is enabled (=’0’) in the configuration register.
PIC18CXX2
DS39026D-page 82 1999-2013 Microchip Technology Inc.
TABLE 8-3: PORTB FUNCTIONS
TABLE 8-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT0 bit0 TTL/ST(1) Input/output pin or external interrupt input1. Internal software
programmable weak pull-up.
RB1/INT1 bit1 TTL/ST(1) Input/output pin or external interrupt input2. Internal software
programmable weak pull-up.
RB2/INT2 bit2 TTL/ST(1) Input/output pin or external interrupt input3. Internal software
programmable weak pull-up.
RB3/CCP2(3) bit3 TTL/ST(4) Input/output pin. Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled. Internal software
programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up.
RB6 bit6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software
programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigge r input when configure d as th e exte rnal interrupt.
2: This buffe r is a Schmitt Trig ger input when used in Se rial Programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
RESETS
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
LAT B LATB Data Output Register
TRISB PORTB Dat a Direction Register 1111 1111 1111 1111
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 1111 -1-1
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 11-0 0-00
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
1999-2013 Microchip Technology Inc. DS39026D-page 83
PIC18CXX2
8.3 PORTC, TRISC and LATC
Registers
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction Register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will
make th e corresponding PO RTC pin an output (i.e., p ut
the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register reads and writes the latched output value for
PORTC.
PORT C is multip lexed with s everal periphe ral function s
(Table 8-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to make
a pin an input. The user should refer to the correspond-
ing periphe ral s ecti on fo r the c orrec t TR IS bit setti ngs .
The pin override value is not loaded into the TRIS reg-
ister . This allows read-modify-write of the TRIS register ,
without concern due to peripheral overrides.
RC1 is normally configured by the configuration bit
CCP2MX as the default peripheral pin for the CCP2
module (default/erased state, CCP2MX = ‘1’).
EXAMPLE 8-3: INITIALIZING PORTC
FIGURE 8-7: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Note: On a Pow er-on Reset, these pins are con-
figured as digital inputs.
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
CLRF LATC ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
Data Bus
WR LATC or
WR TRISC
RD TRISC
QD
Q
CK
QD
EN
Peripheral Data Out
0
1
QD
Q
CK
RD PORTC
Peripheral Data In
WR PORTC
RD LATC
Peripheral Output
Schmitt
Port/Peripheral Select(2)
Enable(3)
P
N
VSS
VDD
I/O pin(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port data (input) and peripheral output.
3: Peripheral Output Enable is only active if peripheral select is active.
Data Latch
DDR Latch
Trigger
PIC18CXX2
DS39026D-page 84 1999-2013 Microchip Technology Inc.
TABLE 8-5: PORTC FUNCTIONS
TABLE 8-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0 /T1OSO/T1CKI bit0 ST I nput/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 bit1 ST Input/output port pin, Timer1 oscillator input, or Capture2 input/
Compare2 output/PWM output when CCP2MX configuration bit is
disabled.
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and
I2C modes.
RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port Data output.
RC6/TX/CK bit6 ST Input/outp ut port p in, Addres sable USAR T A synchronous Transmi t, or
Addressable USART Synchronous Clock.
RC7/RX/D T bit7 ST Input/outp ut port pi n, Ad dre ssabl e U SART Asynchronous R ecei ve, or
Addressable USART Synchronous Data.
Legend: ST = Schmitt Trigger input
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
V al ue on all
other
RESETS
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
LATC LATC Data Out put Regis ter xxxx xxxx uuuu uuuu
TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged
1999-2013 Microchip Technology Inc. DS39026D-page 85
PIC18CXX2
8.4 PORTD, TRISD and LATD
Registers
This section is only applicable to the PIC18C4X2
devices.
PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISD bit (= 0) will
make th e corresponding PO RTD pin an output (i.e., p ut
the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register reads and writes the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is indivi du all y co nfig urable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mod e, the input buffe rs
are TTL. See Section 8.6 for additional information on
the Parallel Slave Port (PSP).
EXAMPLE 8-4: INITIALIZING PORTD
FIGURE 8-8: PORTD BLOCK DIAGRAM
IN I/O PORT MODE
Note: On a Pow er-on Reset, these pins are con-
figured as digital inputs.
CLRF PORTD ; Initialize PORTD by
; clearing output
; data latches
CLRF LATD ; Alternate method
; to clear output
; data latches
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISD ; Set RD<3:0> as inputs
; RD<5:4> as outputs
; RD<7:6> as inputs
Data
Bus
WR LATD
WR TRISD
RD PORTD
Data Latch
TRIS Latch
RD TRISD
Schmitt
Trigger
Input
Buffer
I/O pin(1)
QD
CK
QD
CK
EN
QD
EN
RD LATD
or
PORTD
Note 1: I/O pins have diode protection to VDD and VSS.
PIC18CXX2
DS39026D-page 86 1999-2013 Microchip Technology Inc.
TABLE 8-7: PORTD FUNCTIONS
TABLE 8-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name Bit# Buffer Type Function
RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0.
RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1.
RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2.
RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3.
RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4.
RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5.
RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6.
RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
RESETS
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
LATD LATD Data Output Register xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction Register 1111 1111 1111 1111
TRISE IBF OBF IBOV PSPMODE —PORTE Data Direction bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
1999-2013 Microchip Technology Inc. DS39026D-page 87
PIC18CXX2
8.5 PORTE, TRISE and LATE
Registers
This section is only applicable to the PIC18C4X2
devices.
PORTE is a 3-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISE bit (= 0) will
make the co rresponding POR TE pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register reads and writes the latched output value for
PORTE.
PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7), which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
Register 8-1 shows the TRISE register , which also co n-
trols the par alle l slave port operation.
PORTE pins are multiplexed with analog inputs. When
select ed as an anal og input, thes e pins will re ad as '0's.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
EXAMPLE 8-5: INITIALIZING PORTE
FIGURE 8-9: PORTE BLOCK DIAGRAM
IN I/O PORT MODE
Note: On a Pow er-on Reset, these pins are con-
figured as digital inputs.
Note: On a Pow er-on Reset, these pins are con-
figured as analog inputs.
CLRF PORTE ; Initialize PORTE by
; clearing output
; data latches
CLRF LATE ; Alternate method
; to clear output
; data latches
MOVLW 0x07 ; Configure A/D
MOVWF ADCON1 ; for digital inputs
MOVLW 0x03 ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
Data
Bus
WR LATE
WR TRISE
RD PORTE
Data Latch
TRIS Latch
RD TRISE
Schmitt
Trigger
Input
Buffer
QD
CK
QD
CK
EN
QD
EN
I/O pin(1)
RD LATE
or
PORTE
To Analog Converter
Note 1: I/O pins have diode protect i on to VDD and VSS.
PIC18CXX2
DS39026D-page 88 1999-2013 Microchip Technology Inc.
REGISTER 8-1: TRISE REGISTER
R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0
bit 7 bit 0
bit 7 IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
bit 6 OBF: Output Buffer Full Status bit
1 = The ou tput buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4 PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General purpose I/O mode
bit 3 Unimplemented: Read as '0'
bit 2 TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1 TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0 TRISE0: RE0 Direction Control bit
1 = Input
0 = Output
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 89
PIC18CXX2
TABLE 8-9: PORTE FUNCTIONS
TABLE 8-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name Bit# Buffer Type Function
RE0/RD/AN5 bit0 ST/TTL(1)
Input/output port pin or read control input in Parallel Slave Port mode
or analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected).
RE1/WR/AN6 bit1 ST/TTL(1)
Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected).
RE2/CS/AN7 bit2 ST/TTL(1)
Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1 = Device is not select ed
0 = Device is se lected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Val ue on all
other
RESETS
PORTE — — — — —RE2RE1RE0
---- -000 ---- -000
LATE — — — — — LATE Data Output Register ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE — P OR TE Data Direction bits 0000 -111 0000 -111
ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 --0- -000 --0- -000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
PIC18CXX2
DS39026D-page 90 1999-2013 Microchip Technology Inc.
8.6 Parallel Slave Port
The Parallel Slave Port is implemented on the 40-pin
devi ce s onl y (PIC18C4 X2) .
PORTD operates as an 8-bit wide, parallel slave port,
or microprocessor port, when control bit PSPMODE
(TRISE<4>) is set. It is asynchronously readable and
writable by the external world through RD control input
pin RE0/RD and WR control input pin RE1/WR.
It can directl y int erface to an 8-bit microp roc es sor dat a
bus. The extern al mic roproc essor c an rea d or write th e
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be
set, whic h will co nfigure pins RE2:R E0 as dig ital I/O.
A write to the PSP occurs when both the CS and WR
lines are first dete cted low. A read from the PSP occurs
when both the CS and RD lines are fi rst detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
FIGURE 8-10: PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
FIGURE 8-11: PARALLEL SLAVE PORT WRITE WAVEFORMS
Data Bus
WR LATD RDx
QD
CK
EN
QD
EN
RD PORTD
pin
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1< 7>)
Read
Chip Select
Write
RD
CS
WR
Note: I/O pin has protection diodes to VDD and VSS.
TTL
TTL
TTL
TTL
or
PORTD
RD LATD
Data Latch
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
RD
IBF
OBF
PSPIF
PORTD<7:0>
1999-2013 Microchip Technology Inc. DS39026D-page 91
PIC18CXX2
FIGURE 8-12: PARALLEL SLAVE PORT READ WAVEFORMS
TABLE 8-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Q1 Q2 Q3 Q4
CS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
WR
IBF
PSPIF
RD
OBF
PORTD<7:0>
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on all
other
RESETS
PORTD Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu
LAT D LAT D Data Output bits xxxx xxxx uuuu uuuu
TRISD PORTD Data Direction bits 1111 1111 1111 1111
PORTE — — — — —RE2RE1RE0---- -000 ---- -000
LATE — — — — — LATE Data Output bits ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111
INTCON GIE/
GIEH PEIE/
GIEL TMR0IF INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 --0- -000 --0- -000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
PIC18CXX2
DS39026D-page 92 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 93
PIC18CXX2
9.0 T IMER0 MODULE
The Timer0 module has the following features:
• Software selectable as an 8-bit or 16-bit timer/
counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit
mode and FFFFh to 0000h in 16-bit mode
• Edge select for external clock
Figure 9-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 9-2 shows a
simplified block diagram of the T imer0 module in 16-bit
mode.
The T0CON register (Register 9-1) is a readable and
writ abl e register that co ntro ls al l t he as pec ts of T imer0,
including the prescale selection.
REGISTER 9-1: T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0
bit 7 bit 0
bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0
0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter
0 = Timer0 is configured as a 16-bit timer/counter
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 pre s cale r is NOT assi gned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2:0 T0PS2:T0PS0: Timer0 Prescaler Select bits
111 = 1:256 prescale value
110 = 1:128 prescale value
101 = 1:64 prescale value
100 = 1:32 prescale value
011 = 1:16 prescale value
010 = 1:8 prescale value
001 = 1:4 prescale value
000 = 1:2 prescale value
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 94 1999-2013 Microchip Technology Inc.
FIGURE 9-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
FIGURE 9-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
RA4/T0CKI
T0SE
0
1
0
1
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0
(2 TCY delay)
Data Bus
8
PSA
T0PS2, T0PS1, T0PS0 Set Interrupt
Flag bit TMR 0IF
on Overflow
3
Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
T0SE
0
10
1
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
Clocks TMR0L
(2 TCY delay)
Data Bus<7:0>
8
PSA
T0PS2, T0PS1, T0PS0
Set Interru p t
Flag bit TMR0 IF
on Overflow
3
TMR0
TMR0H
High Byte
88
8
Read TMR0L
Write TMR0L
1999-2013 Microchip Technology Inc. DS39026D-page 95
PIC18CXX2
9.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruc tion cy cle (with out pr escal er). If the TMR0 regis-
ter is w ritten , the i ncrem ent is inhi bited f or the follow ing
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment either on every
rising, or falling edge o f pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When an external cl ock input i s used for T ime r0, it must
meet certain requirements. The requirements ensure
the external clock can be synchroni zed with the internal
phase clock (TOSC). Al so, there is a delay in th e actual
incrementing of Timer0 after synchronization.
9.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module. The prescaler is not readable or
writable.
The PSA and T0PS2:T0PS0 bits determine the pres-
caler assignment and prescale ratio.
Clearing b it PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 reg ister (e.g. CLRF TMR0, MOVWF
TMR0, BSF TMR0, x....etc.) will clear the prescaler
count.
9.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on-the-fly” during program
execution).
9.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister ov erflows from FFh to 00h in 8-bit mod e, or FFFFh
to 0000h i n 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.
9.4 16-Bit Mode Timer Reads and
Writes
TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 9-2). The hig h by te
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16-bits of Timer0 without
having to verify that the read of the high and low byte
were valid due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through th e TM R 0H bu ffer reg ister. Timer0 high byte i s
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16-bit s of Timer0 to be
updated at onc e.
TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on all
other
RESETS
TMR0L Timer0 Module’s Low Byte Register xxxx xxxx uuuu uuuu
TMR0H Timer0 Module’s High Byte Register 0000 0000 0000 0000
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111
TRISA —— PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
PIC18CXX2
DS39026D-page 96 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 97
PIC18CXX2
10.0 TIMER1 MODULE
The Timer1 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module special event trigger
Figure 10-1 is a simplified block diagram of the Timer1
module.
Register 10-1 details the Timer1 control register. This
register controls the operating mode of the Timer1
module, and contains the Timer1 oscillator enable bit
(T1OSCEN). Timer1 can be enabled or disabled by set-
ting or clearin g cont rol bit TMR1ON (T1CON<0>).
REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Wri te Mod e Enable bit
1 = Enables register Read/Write of TImer1 in one 16-bit operation
0 = Enables register Read/Write of Timer1 in two 8-bit operations
bit 6 Unimplemented: R e ad as '0 '
bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable bit
1 = T imer1 Os ci llator is enabl ed
0 = Tim er1 Osci lla tor is shut-off
The oscillator inverter and feedback resistor are turned off to eliminate pow e r drain.
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 98 1999-2013 Microchip Technology Inc.
10.1 Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Ti mer1 increments on
every rising edge of the external clock input or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 13.0).
FIGURE 10-1: TIMER1 BLOCK DIAGRAM
FIGURE 10-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
TMR1H TMR1L
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0 SLEEP Inp ut
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
TMR1IF
Overflow TMR1 CLR
CCP Spec ial Event Trigger
T1OSCEN
Enable
Oscillator(1)
T1OSC
Interrupt
Flag bit
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1OSI
T1CKI/T1OSO
Timer 1 TMR1L
T1OSC T1SYNC
TMR1CST1CKPS1:T1CKPS0 SLEEP Input
T1OSCEN
Enable
Oscillator(1)
TMR1IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T13CKI/T1OSO
T1OSI
TMR1
Flag bit
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR1H 8
8
8
Read TMR1L
Write TMR1L
CLR
CCP Special Event Trigger
1999-2013 Microchip Technology Inc. DS39026D-page 99
PIC18CXX2
10.2 Timer1 Oscillator
A crystal oscillator circuit is built-in betwee n pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control b it T1OSCEN (T1CON<3>). The o scilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 10-1 shows the capacitor
selection for th e Timer1 oscillator.
The user m us t prov id e a so ftware tim e de lay to ensure
proper start-up of the Timer1 oscillator.
10.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow,
which is latched i n interrupt flag bit TM R1IF (PIR1<0>).
This in terrupt ca n be ena bled/disa bled by setting/c lear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
10.4 Resetting Timer 1 using a CCP
Trigger Output
If the CCP module is configured in compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or synchro-
nized counte r mode t o tak e advant age o f this fe ature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the even t that a write to T imer1 coi ncides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of o peration, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
10.5 Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes
(see Figure 10-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer regis ter f or th e hig h byte of Timer 1. A r ead
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16-bits of
Timer1, without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through th e TM R 1H bu ffer reg ister. Timer1 high byte i s
updated with the contents of TMR1H when a write
occurs to TMR 1L . Thi s a ll ows a us er to wr ite all 16 bits
to both the high and low bytes of Timer1 at once.
TMR1 H is up dat ed fr om the high byte when TMR1 L is
read.
The high b yt e of Timer1 is no t di rec tly readable or wri t-
able in thi s m ode . All rea ds and wri tes must t ak e pl ac e
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The pres-
caler is only cleared on writes to TMR1L.
TABLE 10-1: CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR
Osc Type Freq. C1 C2
LP 32 kHz TBD(1) TBD(1)
Crystal to be Tested:
32.768 kHz Epson C-001R32.768K-A 20
PPM
Note 1: Microchip suggests 33 pF as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
ch aracteristics, the user should cons ult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guida nce
only.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
PIC18CXX2
DS39026D-page 100 1999-2013 Microchip Technology Inc.
TABLE 10-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PS PI E and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc. DS39026D-page 101
PIC18CXX2
11.0 TIMER2 MODULE
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to gen-
erate clock shift
Timer2 has a control register shown in Register 11-1.
Timer2 can b e s hu t -off by clea ring c ont rol bit TMR2O N
(T2CON<2>) to minimize power consumption.
Figure 11-1 is a simplified block diagram of the Timer2
module. Register 11-1 shows the Timer2 control regis-
ter. The prescaler and postscaler selection of Timer2
are controlled by this register.
11.1 Timer2 Ope r ation
Timer2 can be used as the PWM time-base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
RESET. The input clock (FOSC/4 ) has a p rescal e optio n
of 1:1, 1:4, or 1:16, selected by control bits
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
TMR2 is not cleared when T2CON is written.
REGISTER 11-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0
bit 7 Unimplemented: R e ad as '0 '
bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Ti mer2 On bit
1 = Tim er2 is on
0 = Tim er2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Se lect bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 102 1999-2013 Microchip Technology Inc.
11.2 Timer2 Int e rr u p t
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
11.3 Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchron ous Serial Port mod ule, which opti onally use s
it to generate the shift clock.
FIGURE 11-1: TIMER2 BLOCK DIAGRAM
TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Comparator
TMR2 Sets Flag
TMR2
Output(1)
RESET
Postscaler
Prescaler
PR2
2
FOSC/4
1:1 1:16
1:1, 1:4, 1:16
EQ
4
bit TMR2IF
Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.
to
TOUTPS3:TOUTPS0
T2CKPS1:T2CKPS0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on
POR, BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TMR2 Timer2 Module Register 0000 0000 0000 0000
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Ti mer2 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc. DS39026D-page 103
PIC18CXX2
12.0 TIMER3 MODUL E
The Timer3 module timer/counter has the following
features:
• 16-bit timer/counter
(two 8-bit registers: TMR3H and TMR3L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• Reset from CCP module trigger
Figure 12-1 is a simplified block diagram of the Timer3
module.
Register 12-1 shows the Timer3 control register. This
register controls the operating mode of the Timer3
module and sets the CCP clock source.
Register 10-1 shows the Timer1 control register. This
register controls the operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable b it (T1OSCEN), whi ch can be a clock source f or
Timer3.
REGISTER 12-1: T3CON: TIMER3 CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
bit 7 bit 0
bit 7 RD16: 16-bit Read/Write Mode Enable
1 = Enables register Read/Write of Timer3 in one 16-bit operation
0 = Enables register Read/Write of Timer3 in two 8-bit operations
bit 6-3 T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits
1x = Timer3 is the clock source for compare/capture CCP modules
01 = Timer3 is the clock source for compare/capture of CCP2,
Timer1 is the clock source for compare/capture of CCP1
00 = Timer1 is the clock source for compare/capture CCP modules
bit 5-4 T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.
bit 1 TMR3CS: Timer3 Clock Source Select bit
1 = External clock input from Timer1 oscillator or T1CKI
(on the rising edge after the first falling edge)
0 = Internal clock (FOSC/4)
bit 0 TMR3ON: Timer3 On bit
1 = Enables Timer3
0 = Stops Timer3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 104 1999-2013 Microchip Technology Inc.
12.1 Timer3 Operation
Timer3 can operate in one of these modes:
•As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Ti mer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer3 also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 12.0).
FIGURE 12-1: TIMER3 BLOCK DIAGRAM
FIGURE 12-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
TMR3H TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0 SLEEP Input
T1OSCEN
Enable
Oscillator(1)
TMR3IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Inp ut
2
T1OSO/
T1OSI
Flag bit
(3)
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned of f. This eliminates power drain.
T13CKI
CLR
CCP Special Trigger
T3CCPx
Timer3
TMR3L
T1OSC T3SYNC
TMR3CS
T3CKPS1:T3CKPS0 SLEEP Input
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8 Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
TMR3
T13CKI
CLR
CCP Special Trigger
T3CCPx
To Timer1 Clock Input
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR3H 8
8
8
Read TMR3L
Write TMR3L
Set TMR3IF Flag bit
on Overflow
1999-2013 Microchip Technology Inc. DS39026D-page 105
PIC18CXX2
12.2 Timer1 Oscillator
The Timer1 osci llator ma y b e us ed as the clock so urc e
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low
power osci llator rat ed up to 200 KHz. See Sect ion 10.0
for further details.
12.3 Timer3 Interrupt
The TMR3 Register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched i n interrupt flag bit TM R3IF (PIR2<1>).
This in terrupt ca n be ena bled/disa bled by setting/c lear-
ing TMR3 interrupt enable bit, TMR3IE (PIE2<1>).
12.4 Resetting Timer 3 Using a CCP
Trigger Output
If the CCP module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer3.
T imer 3 must be co nfigured fo r either T i mer or Synch ro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RES ET operation m ay not work. In th e event tha t a
write to Timer3 coincides with a special event trigger
from CCP1 , the write will t ake precedence. In this mode
of operation, the CCPR1H:CCPR1L registers pair
effectively becomes the period register for Timer3.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Note: The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR1<0>).
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR2 — — — — BCLIF LVDIF TMR3IF CCP2IF 0000 0000 0000 0000
PIE2 — — — — BCLIE LVDIE TMR3IE CCP2IE 0000 0000 0000 0000
IPR2 — — — — BCLIP LVDIP TMR3IP CCP2IP 0000 0000 0000 0000
TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
T1CON RD16 —T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
PIC18CXX2
DS39026D-page 106 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 107
PIC18CXX2
13.0 CAPTURE/COMPARE/PWM
(CCP) MODULES
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/ slave Duty C ycle register. Table 13-1 show s the
timer resources of the CCP module modes.
The ope ration of CCP1 is ide ntical to t hat of CC P2, with
the exception of the special event trigger. Therefore,
operation of a CCP module in the following sections is
describ ed w ith res pect to CCP 1.
Table 13-2 shows the interaction of the CCP modules.
REGISTER 13-1: CCP1CON REGISTER/CCP2CON REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.
bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0001 = Reserved
0010 = Compare mode, toggle output on match (CCPxIF bit is set)
0011 = Reserved
0100 = Capt ure mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, ever y 16t h rising edge
1000 = Compare mode,
Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set)
1001 = Compare mode,
Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set)
1010 = Compare mode,
Generate software interrupt on compare match (CCPIF bit is set, CCP pin is
unaffected)
1011 = Compare mode,
Trigger special event (CCPIF bit is set)
11xx =PWM mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 108 1999-2013 Microchip Technology Inc.
13.1 CCP1 Module
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 13-1: CCP MODE - TIMER
RESOURCE
13.2 CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
TABLE 13-2: INTERACTION OF TWO CCP MODULES
CCP Mode Timer Resource
Capture
Compare
PWM
Timer1 or Ti mer3
Timer1 or Ti mer3
Timer2
CCPx Mode CCPy Mode Interaction
Capture Capture TMR1 or TMR3 time-base. Time-base can be diffe rent for each CCP.
Capture Compare The compare could be configured for the special event trigger,
which clears either TMR1, or TMR3, depending upon which time-base is used.
Compare Compare The compare(s) could be configured for the special event trigger,
which clears TMR1, or TMR3, depending upon which time-base is used.
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM Capture None.
PWM Compare None.
1999-2013 Microchip Technology Inc. DS39026D-page 109
PIC18CXX2
13.3 Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cle ared in sof tware. If a nother captu re occurs befo re
the value in register CCPR1 is read, the old captured
value wi ll be los t.
13.3.1 CCP PIN CONFIGURATION
In Capt ure m od e, th e R C2/CCP1 pin shoul d b e co nfi g-
ured as an input by setting the TRISC<2> bit.
13.3.2 TIMER1/TIMER3 MODE SELECTION
The timers that are to be used with the ca pture feature
(either T ime r1 and/or T imer3) must be run ning in T imer
mode or Synchronized Counter mode. In Asynchro-
nous Counter mode, the capture operation may not
work. The timer to be used with each CCP module is
selected in the T3CON register.
13.3.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in ope rati ng mod e.
13.3.4 CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleare d, therefore , the first cap ture may be from
a non-zero prescaler. Example 13-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 13-1: CHANGING BETWEEN
CAPTURE PRESCALERS
FIGURE 13-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
Note: If the RC2/CCP1 is configured as an out-
put, a write to the por t can cause a captu re
condition.
CLRF CCP1CON, F ; Turn CCP module off
MOVLW NEW_CAPT_PS ; Load WREG with the
; new prescaler mode
; value and CCP ON
MOVWF CCP1CON ; Load CCP1CON with
; this value
CCPR1H CCPR1L
TMR1H TMR1L
Set Flag bit CCP1IF TMR3
Enable
Q’s CCP1CON<3:0>
CCP1 pin
Prescaler
1, 4, 16
and
Edge Detect
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP2
CCPR2H CCPR2L
TMR1H TMR1L
Set Flag bit CCP2IF
TMR3
Enable
Q’s CCP2CON<3:0>
CCP2 pin
Prescaler
1, 4, 16
and
Edge Detect
TMR3H TMR3L
TMR1
Enable
T3CCP2
T3CCP1
T3CCP2
T3CCP1
PIC18CXX2
DS39026D-page 110 1999-2013 Microchip Technology Inc.
13.4 Compare Mode
In Compare mode, the 16-bit CCPR1 (CCPR2) register
value is constantly compared against either the TMR1
register pair value or the TMR3 register pair value.
When a match o ccurs, t he RC2/CCP 1 (RC1/CC P2) pin
is:
• driven High
• driven Low
• toggle output (High to Low or Low to High)
• remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the
same time, interrupt flag bit, CCP1IF (CCP2IF) is set.
13.4.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRISC bit.
13.4.2 TIMER1/TIMER3 MODE SELECTION
Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
13.4.3 SOFTWARE INTERRUPT MODE
When gen erat e sof tware i nte rrupt is chosen, the CCP1
pin is not af fected. On ly a CCP interrupt is generated (if
enabled).
13.4.4 SPECIAL EVENT TRIGGER
In this mod e, an internal hardware trigger is gene rated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 regi ste r pai r. Thi s al lows the CCPR 1 re gis ter to
ef fectively b e a 16-bit progra mmable pe riod registe r for
Timer1.
The special trigger output of CCPx resets either the
TMR1 or TMR3 register pair. Additionally, the CCP2
Special Event T r igger wil l st art an A/D convers ion if th e
A/D module is enabled.
FIGURE 13-2: COMPARE MODE OPERATION BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the RC2/CCP1 co mpare outp ut latch to the
default l ow le ve l. Th is is n ot th e da t a l atc h.
Note: The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.
CCPR1H CCPR1L
TMR1H TMR1L
Comparator
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP1IF
Match
RC2/CCP1
TRISC<2> CCP1CON<3:0>
Mode Select
Output Enab le
pin
Special Event Trigger will:
Reset Timer1or Timer3, but not set Timer1 or Timer3 Interrupt Flag bit,
and set bit GO/DONE (ADCON0<2>)
which starts an A/D Conversion (CCP2 only )
TMR3H TMR3L
T3CCP2
CCPR2H CCPR2L
Comparator
1
0
T3CCP2
T3CCP1
QS
ROutput
Logic
Special Event Trigger
Set Flag bit CCP2IF
Match
RC1/CCP2
TRISC<1> CCP2CON<3:0>
Mode Select
Output Enab le
pin
01
1999-2013 Microchip Technology Inc. DS39026D-page 111
PIC18CXX2
TABLE 13-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
PIR2 — — — — BCLIF LVDIF TMR3IF CCP2IF 0000 0000 0000 0000
PIE2 — — — — BCLIE LVDIE TMR3IE CCP2IE 0000 0000 0000 0000
IPR2 — — — — BCLIP LVDIP TMR3IP CCP2IP 0000 0000 0000 0000
TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON -000 0000 -uuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: T he PS PI F, PSPI E and PSP IP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
DS39026D-page 112 1999-2013 Microchip Technology Inc.
13.5 PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC dat a latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 13-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a ste p-by-step proc edure on how t o set up the CC P
module for PWM operation, see Section 13.5.3.
FIGURE 13-3: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 13-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 13-4: PWM OUTPUT
13.5.1 PWM PERIOD
The PWM p eriod is spec ified by writi ng to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing for mula:
PWM per iod = (PR2) + 1] • 4 • TOSC •
(TMR 2 pr e scale valu e)
PWM frequency is defined as 1 / [PWM period].
When TM R2 is equal to PR2, t he following three event s
occur on the next increment cycle:
•TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from C CPR1L into
CCPR1H
13.5.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1L c on tai ns
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 pre scale value)
CCPR1L and CCP1CON<5:4> can be written to a t any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to dou ble buf fer th e PWM duty cycle. Thi s doubl e
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescale r, t he CCP1 pin i s cleared.
The ma ximum P WM res olut ion (b its) for a given PWM
frequency is given by the equation:
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
RQ
S
Duty Cycle Registers CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC2/CCP1
Note: 8-bi t ti mer i s conc at enate d wi th 2-b it inter nal Q cl ock or
2 bits of the prescaler to create 10-bit time-base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
Note: The Timer2 postscaler (see Section 11.0)
is not used in the determination of the
PWM frequency. The postscaler could be
used to have a servo update rate at a dif-
ferent frequency than the PWM output.
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
FOSC
FPWM
---------------
log
2log
----------------------------- b it s=
PWM Resolution (max)
1999-2013 Microchip Technology Inc. DS39026D-page 113
PIC18CXX2
13.5.3 SETUP FOR PWM OPERA T ION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2
register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable T imer2
by writing to T2CON.
5. Configure the CCP1 modu le for PWM operation.
TABLE 13-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
TABLE 13-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2
PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz
Timer Prescaler (1, 4, 16)1641111
PR2 Va lue 0xFF 0xFF 0xFF 0x3 F 0x1F 0x17
Maximum Resol ution (bits) 14 12 10 8 7 6.58
Name Bi t 7 Bi t 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 B it 0 Va lue on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
TMR2 Timer2 Module Register 0000 0000 0000 0000
PR2 T imer2 Module Period Register 1111 1111 1111 1111
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: T he PS PI F, PSPI E and PSP IP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
DS39026D-page 114 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 115
PIC18CXX2
14.0 MASTER SYNCHRONOUS
SERIAL PORT (MS SP)
MODULE
14.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
periphera l or m icroc ontroll er dev ices. Th ese p eriphera l
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPITM)
• Inter-Integrated Circuit (I2CTM)
- Full Master mode
- Slave mode (with general address call)
The I2C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
PIC18CXX2
DS39026D-page 116 1999-2013 Microchip Technology Inc.
14.2 Control Registers
The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control regi st ers (SSPCON1 and SSPCON2).
REGISTER 14-1: SSPSTAT: MSSP STATUS REGISTER
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
bit 7 SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6 CKE: SPI Clock Edge Select bit
CKP = 0:
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1:
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5 D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4 P: STOP bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET)
0 = STOP bit was not detected last
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 117
PIC18CXX2
bit 3 S: START bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a START bit has been detected last (this bit is '0' on RESET)
0 = START bit was not detected la st
bit 2 R/W: Read/Write bit information (I2C mode only)
This bit h olds the R/W bit informa tion following the last addre ss match. Thi s bit is only valid from
the address match to the next START bit, STOP bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in
IDLE mode.
bit 1 UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
REGISTER 14-1: SSPSTAT: MSSP STATUS REGISTER (CONTINUED)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 118 1999-2013 Microchip Technology Inc.
REGISTER 14-2: SSPCON1: MSSP CONTROL REGISTER1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
bit 7 WCOL: Write Collision Detect bit
Master mode:
1 = A write to the SSP BUF re gister was att empted w hile the I2C condit ions were not v alid f or a
transmission to be started
0 =No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in s oftwar e)
0 =No collision
bit 6 SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is receiv ed while the SSPBUF registe r is still holdi ng the previ ous dat a. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.
In Slave mode, the user must read the SSPBUF, even if only transmitting data to avoid
setting overflow.
In Master mo de, th e ov erfl ow bit is no t set , since eac h ne w re ce ptio n (an d tran sm is si on) is
initiated by writing to the SSPBUF register (must be cleared in software).
0 = No overflow
In I2 C mode:
1 = A by te i s rec eiv ed whil e th e SSPBUF register is sti ll hol din g the previous by te. SSPOV is a
“don’t care” in Transmit mode (must be cleared in software).
0 = No overflow
bit 5 SSPEN: Synchronous Serial Port Enable bit
In both modes when enabled, these pins must be properly configured as input or output.
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SD I, and SS as the source of the serial
port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the
serial port pins
0 = Disables serial port and configures these pins as I/O port pins
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 119
PIC18CXX2
bit 4 CKP: Clock Polarity Selec t bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2 C Slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2 C Master mode:
Unused in this mode
bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mod e, clock = SCK p in. SS pin c ontrol d isabl ed. SS can b e used a s I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Mas ter mode, cloc k = FOSC / (4 * (SSPADD+1))
1001 = Reserved
1010 = Reserved
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
REGISTER 14-2: SSPCON1: MSSP CONTROL REGISTER1 (CONTINUED)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 120 1999-2013 Microchip Technology Inc.
REGISTER 14-3: SSPCON2: MSSP CONTROL REGISTER2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
bit 7 GCEN: General Call Enable bit (In I2C Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Maste r Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5 ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Maste r Receiv e mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1 = Not Acknowledge
0 = Acknowledge
bit 4 ACKEN: Acknow led ge Sequ enc e Enab le bit (In I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 =Acknowledge sequence idle
bit 3 RCEN: Receive Enable bit (In I2C Master mode only)
1 = Enables Receive mode for I2C
0 = Receive idle
bit 2 PEN: ST OP Condition Enab le bit (In I2C Master mode only)
SCK Release Control:
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
bit 1 RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1 = Initiate Repeated START condition on SDA and SCL pins.
Automatically cleared by hardware.
0 = Repeated START condition idle
bit 0 SEN: START Condition Enabled bit (In I2C Master mo de onl y)
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle
Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 121
PIC18CXX2
14.3 SPI Mode
The SPI mode allows 8-bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
• Serial Data Out (SDO) - RC5/SDO
• Serial Data In (SDI) - RC4/SDI/SDA
• Serial Clock (SCK) - RC3/SCK/SCL/LVOIN
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS ) - RA5/SS/AN4
14.3.1 OPERATION
When initializing the SPI, several options need to be
specif ied. This is done by progra mming the ap propriate
control bits (SSPCON1<5:0>) and SSPSTAT<7:6>.
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data input sample phase (middle or end of data
output time)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Figure 14-1 shows the block diagram of the MSSP
module, when in SPI mode.
FIGURE 14-1: MSSP BLOCK DIAGRAM
(SPI MODE)
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buf fer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the re ceived data is ready. Once the 8-bit s of data
have bee n received, that byte is m oved to th e SSPBUF
register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double buffering of the received data
(SSPBUF) allows the next byte t o start reception before
reading t he data that was just re ceived. Any w rite to the
SSPBUF register during transmission /reception of dat a
will b e ignored , and the wri te collis ion dete ct bit, WC OL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be de termin ed if the foll ow-
ing write(s) to the SSPBUF register completed
successfully.
Read Write
Internal
Data Bus
SSPSR reg
SSPBU F reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/R X in SSPSR
TRIS bit
2
SMP:CKE
SDI
SDO
SS
SCK
( )
PIC18CXX2
DS39026D-page 122 1999-2013 Microchip Technology Inc.
When the application software is expecting to receive
valid da ta, the SSPBUF shoul d be read before th e next
byte of dat a to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the MSSP Interrupt is used to
determine when the transmission/reception has com-
pleted. T he SSPBUF must be rea d and/or written. If the
interrupt metho d i s not going to b e u sed, then software
polling can be d one to ensure that a write collision d oes
not occur. Example 14-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
EXAMPLE 14-1: LOADING THE SSPBUF (SSPSR) REGISTER
The SSPSR is not directly readable or writable, and
can onl y be acce ss ed b y addressing th e SSPBUF reg-
ister . Additionally , the MSSP status register (SSPST A T)
indicates the various status conditions.
14.3.2 ENABLING SPI I/O
To enable the serial port, SSP enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
port pin s. For the pins to behave as the serial p ort func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed. That is:
• SDI is a utom at ic all y c ontrolled by the SPI mo dul e
• SDO must have TRISC<5> bit cleared
• SCK (Master mode) must have TRISC<3> bit cleared
• SCK (Slave mode) must have TRISC<3> bit set
•SS must have TRISC<4> bit set
Any serial po rt func tion that is not desired ma y be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value.
LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?
GOTO LOOP ;No
MOVF SSPBUF, W ;WREG reg = contents of SSPBUF
MOVWF RXDATA ;Save in user RAM, if data is meaningful
MOVF TXDATA, W ;W reg = contents of TXDATA
MOVWF SSPBUF ;New data to xmit
1999-2013 Microchip Technology Inc. DS39026D-page 123
PIC18CXX2
14.3.3 TYPIC AL CON NECT IO N
Figure 14-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
gramme d to same Clock Pola rity (CKP), then both co n-
trollers would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data—Slave sen ds dumm y data
• Master sends data—Slave sen ds dat a
• Master sends du mmy data—Slave sends data
FIGURE 14-2: SPI MAST E R/S LAVE CONNECTION
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
MSb LSb
SDO
SDI
PROC ES SOR 1
SCK
SPI Master SSPM3:SSPM0 = 00xxb
Serial Input Buffer
(SSPBUF)
Shift Register
(SSPSR)
LSb
MSb
SDI
SDO
PROCESSOR 2
SCK
SPI Slave SSPM 3:SSPM0 = 010xb
Serial Clock
PIC18CXX2
DS39026D-page 124 1999-2013 Microchip Technology Inc.
14.3.4 MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 14-2) is to broad-
cast dat a by the so ftware protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF registe r is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will co ntinue to shift in the sign al present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a “Line Activity Monitor” mode.
The clock polarity is sele cted by appropr iately program-
ming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication as shown in
Figure 14-3, Figure 14-5, and Figure 14-6, where the
MSB is t rans m itte d f irst. In Master mo de, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
•F
OSC/4 (or TCY)
•FOSC/16 (or 4 • TCY)
•F
OSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum data rate (at 40 MHz) of 10.00
Mbps.
Figure 14-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
dat a is shown.
FIGURE 14-3: SPI MODE WAVEFORM (MASTER MODE)
SCK
(CKP = 0
SCK
(CKP = 1
SCK
(CKP = 0
SCK
(CKP = 1
4 Clock
modes
Input
Sample
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
bit7 bit0
SDI
SSPIF
(SMP = 1)
(SMP = 0)
(SMP = 1)
CKE = 1)
CKE = 0)
CKE = 1)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
(CKE = 0)
(CKE = 1)
Next Q4 cy cle
after Q 2
1999-2013 Microchip Technology Inc. DS39026D-page 125
PIC18CXX2
14.3.5 SLAVE MODE
In Slave m ode , the data is tra ns mitted and receiv ed a s
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.
14.3.6 SLAVE SELECT
SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The Data Latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.
When the SPI module resets, the bit counter is forced
to 0. This can be done by either forcing the SS pin to a
high level, or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an in put. This d isables transmissi ons from th e SDO.
The SDI can always be left as an input (SDI function),
since it cann ot cre ate a bus con flict.
FIGURE 14-4: SLAVE SYNCHRONIZATION WAVEFORM
Note 1: When the SPI is in Slave mode with SS
pin control enabled (SSPCON<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: If the SPI is us ed in Slave mo de with CK E
set, then the SS pin control must be
enabled.
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7
SDO bit7 bit6 bit7
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
bit0
bit7 bit0
Next Q4 cycle
after Q2
PIC18CXX2
DS39026D-page 126 1999-2013 Microchip Technology Inc.
FIGURE 14-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
FIGURE 14-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 0)
CKE = 0)
(SMP = 0)
Write to
SSPBUF
SSPSR to
SSPBUF
SS
Flag
optional
Next Q4 cycle
after Q2
SCK
(CKP = 1
SCK
(CKP = 0
Input
Sample
SDI bit7 bit0
SDO bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SSPIF
Interrupt
(SMP = 0)
CKE = 1)
CKE = 1)
(SMP = 0)
Wr i te t o
SSPBUF
SSPSR to
SSPBUF
SS
Flag
not optional
Next Q4 cycle
after Q2
1999-2013 Microchip Technology Inc. DS39026D-page 127
PIC18CXX2
14.3.7 SLEEP OPERATION
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operat es asy nchron ously to the devi ce. Th is al lows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP inter-
rupt flag bit will be set and if enabled, will wake the
device from SLEEP.
14.3.8 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
14.3.9 BUS MODE COMPATIBILITY
Table 14-1 shows the compatibility between the stan-
dard SPI modes and the states of the CKP and CKE
control bits.
TABLE 14-1: SPI BUS MODES
There is also a SMP bit w hich co ntrols whe n the dat a is
sampled.
TABLE 14-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP (1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
TRISC PORTC Data Direction Register 1111 1111 1111 1111
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA — P ORTA Data Direction Register --11 1111 --11 1111
SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.
Note 1: The PSPIF, PSPIE and PSPIP bit s are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
PIC18CXX2
DS39026D-page 128 1999-2013 Microchip Technology Inc.
14.4 MSSP I2C Operation
The MSSP module in I2C mode, fully implements all
master an d sla ve func tion s (in cl udi ng general ca ll su p-
port) and pro vid es interrup ts on START and STOP bits
in hardw are to determine a free bus (m ulti-master fun c-
tion). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
T wo pins are used for data trans fer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/S DA pin, which i s the data ( SDA). T he user mu st
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
The MSSP module functions are enabled by setting
MSSP enable bit SSPEN (SSPCON<5>).
FIGURE 14-7: MSSP BLOCK DIAGRAM
(I2C MODE)
The MSSP module has six registers for I2C operation.
These are the:
• MSSP Control Register1 (SSPCON1)
• MSSP Control Register2 (SSPCON2)
• MSSP Status Register (SSPSTAT )
• Serial Receive/Transmit Buffer (SSPBUF)
• MSSP Shift Register (SSPSR) - Not directly
accessible
• MSSP Address Register (SSPADD)
The SSPCON1 register allows control of the I2C oper-
ation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
•I
2C Master mode, clock = OSC/4 (SSPADD +1)
•I
2C Slave mode (7-bit address)
•I
2C Slave mode (10-bit address)
•I
2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled
•I
2C Slave mo de (10-bit address) , with START and
STOP bit interrupts enabled
•I
2C Firmware controlled master operation, slave
is id le
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided thes e pin s are p rogr ammed t o be i nputs by set-
ting the appropriate TRISC bits .
14.4.1 SLAVE MODE
In Slave mod e, the SCL and SDA pin s must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (sl ave-tran smit ter).
When an address is matched or the data transfer after
an add ress m atc h is r ece ived , the hard ware aut omati -
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value cur-
rently in the SSPSR register.
There are certain conditions that will cause the MSSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overf low bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register , while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low fo r pro per ope rati on. The hi gh an d l ow ti mes of th e
I2C specification, as well as the requirement of the
MSSP module, are shown in timing parameter #100
and parameter #101.
Read Write
SSPSR reg
Match Detect
SSPADD reg
START and
STOP bit Detect
SSPBUF reg
Internal
Data Bus
Addr Match
Set, Reset
S, P bits
(SSPSTAT reg)
RC3/SCK/SCL
RC4/
Shift
Clock
MSb
SDI/ LSb
SDA
1999-2013 Microchip Technology Inc. DS39026D-page 129
PIC18CXX2
14.4.1.1 Addressing
Once the MSSP module has been enabled, it waits for
a START co ndition to o ccur. Following the START con-
dition, the 8-bit s are shifted int o the SSPSR register . All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a) The SSPSR register value is loaded into the
SSPBUF register.
b) The buffer full bit BF is set.
c) An ACK pulse is generated.
d) MSSP interrupt flag bit SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) on the falling
edge of the ninth SCL pulse.
In 10-bit address mode, tw o address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPST A T<2>) must specify a write so
the slave device will receive the second address byte.
For a 10-bit address, the first byte would equal ‘1111 0
A9 A8 0’, where A9 and A8 are the two MSbs of the
address. The sequence of events for 10-bit address is
as follows, with steps 7-9 for slave-transmitter:
1. Receive first (high) byte of Addre ss (bit s SSPIF,
BF and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the firs t (high)
byte of Address. If match releases SCL line, this
will clear bit UA.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive Repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
14.4.1.2 Reception
When the R/W bi t of the addres s byte i s clea r and an
address match occurs, the R/W bit of the SSPSTAT
register i s cleared . Th e receive d addre ss is loa ded in to
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. F lag bit SSPIF (PIR1<3>) must be cle ared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
14.4.1.3 Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RC3/SC K/SCL s ho uld be ena ble d by se t-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL p in p rior to as se rting anothe r cl oc k pu ls e. Th e
slave d evices may be ho lding off the master by stretc h-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 14-9).
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SC L input pulse. If the SD A line is high (not ACK),
then the data transfer is complete. When the ACK is
latched by the slave, the slave logic is reset (resets
SSPSTAT register) and the slave monitors for another
occurrence of the START bit. If the SDA line was low
(ACK), the transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Pin RC3/SCK/SCL should be enabled by setting bit
CKP.
PIC18CXX2
DS39026D-page 130 1999-2013 Microchip Technology Inc.
FIGURE 14-8: I2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 14-9: I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
P
9
8
765
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1SDA
SCL 1234567891234567891234
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK Receiving Data
Receiving Data D0
D1
D2
D3D4
D5
D6D7
ACK
R/W=0
Receiving Ad dr ess
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Not ACK
ACK is not sent.
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON1<4>)
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 Not ACKTransmitting DataR/W = 1Receiving Address
123456789 123456789 P
Cleared in software
SSPBUF is written in software From SSP Interrupt
Service Routine
Set bit after writing to SSPBUF
SData in
sampled SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written to
before the CKP bit can be set)
R/W = 0
1999-2013 Microchip Technology Inc. DS39026D-page 131
PIC18CXX2
FIGURE 14-10 : I2C SLAVE MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456 789 1 23456789 12345 789 P
1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 1 1 1 1 0 A8
R/W=1
ACK
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Master sends NACK
A9
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated.
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPADD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
Cleared by hardware when
SSPADD is updated.
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
Receive First Byte of Address
12345 789
D7 D6 D5 D4 D3 D1
ACK
D2
6
Transmitting Data Byte
D0
Dummy read of SSPBUF
to clear BF flag
Sr
Cleared in software
Write of SSPBUF
initiates transmit
Cleared in software
Tr ansmi t is comple te
CKP has to be set for clock to be released
Bus Master
terminates
transfer
PIC18CXX2
DS39026D-page 132 1999-2013 Microchip Technology Inc.
FIGURE 14-11: I2C SLAVE MODE WAVEFORM (RECEPTION 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
S123456 789 1 2345 67 89 12345 789 P
1 1 1 1 0 A9A8 A7 A6 A5A4A3A2A1 A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in s oftware
Bus Master
terminates
transfer
D2
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when
SSPADD is updated with
UA (SSPSTAT<1>)
Clock is held low until
update of SSPADD has
taken place
UA is set indicating that
the SSPA DD needs to be
updated
UA is set indicating that
SSPADD needs to be
updated
SSPBUF is written with
contents of SSPSR Dummy read of SSPBUF
to clear BF flag
ACK
R/W = 1
Cleared in software
Dummy read of SSPBUF
to clear BF flag Read of SSPBUF
clears BF flag
Cleared by hardware when
SSPADD is updated with
low byte of address. high byte of address.
1999-2013 Microchip Technology Inc. DS39026D-page 133
PIC18CXX2
14.4.2 GENERAL CALL ADDRESS
SUPPORT
The addressing procedure for the I2C bus is su ch that
the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master . The exception is the general call address which
can addre ss all devices . When thi s addre ss is use d, all
devices should, in theory, respond with an acknowl-
edge.
The general call address is one of eight addresses
reserved for specific purposes by the I2C protocol. It
consists of all 0’s with R/W = 0.
The general call address is recognized when the Gen-
eral Call Ena ble bit (GCEN) is enabled (SSPCON2< 7>
is set). Following a START bit detect, 8-bits are shifted
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.
If the general call address matches, the SSPSR is
transferre d to the S SPBUF, the BF f lag bit i s set (eigh th
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
When the i nterrupt is serviced, the s ou r ce f or the int er-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second h alf of th e addres s to ma tch, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 14-12).
FIGURE 14-12: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)
14.4.3 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET or when the MSSP module is
disabled. Control of the I2C bus may be taken w hen the
P bit is set, or th e bus is idle, with bo th the S and P bit s
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP interrupt, if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeat ed START
SDA
SCL S
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
Cleared in software
SSPBUF is read
R/W = 0ACK
General Call Address
Address is compared to General Call Address
GCEN (SSPCON2<7>)
Receiving Data ACK
123456789123456789
D7 D6 D5 D4 D3 D2 D1 D0
after ACK, set interru pt
'0'
'1'
PIC18CXX2
DS39026D-page 134 1999-2013 Microchip Technology Inc.
14.4.4 I2C MASTER MODE SUP PORT
Master mode is enabled by setting and clearing the
appropri ate SSPM bit s in SSPCON1 and by set ting the
SSPEN bit. Once Master mode is enabled, the user
has si x opti ons .
1. Assert a START condition on SDA and SCL.
2. Assert a Repeated START condition on SDA
and SCL.
3. Write to th e SSPBUF register initiati ng transmis-
sion of data/address.
4. Generate a STOP condition on SDA a nd SCL.
5. Con figure the I2C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
FIGURE 14-13: MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Note: The MSSP modu le, when configure d in I2C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, ind icating tha t a write
to the SSPBUF did not occur.
Read Write
SSPSR
START bit, STOP bit,
STAR T b it Detect
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb LSb
SDA
Acknowledge
Generate
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV
SCL
SCL in
Bus Collision
SDA in
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSP IF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
1999-2013 Microchip Technology Inc. DS39026D-page 135
PIC18CXX2
14.4.4.1 I2C Master Mode Operation
The master device generates all of the serial clock
pulses and th e START and STOP conditi ons. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is al so the begin ni ng of t he nex t s eri al transfer, the
I2C bus will not be released.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contai ns the slave address of the
recei vin g dev ice ( 7 bits) and the Rea d/Writ e (R/ W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a tim e. After each byte is t rans mit-
ted, an Ac knowledge bit is rec eived. START and STOP
conditions are output to indicate the beginning and the
end of a serial trans fer.
In Master Rec eive mode , the first byte transm itted con-
tains the slave address of the transmitting device
(7 bits) and th e R/W bit. In this case, the R/W bit wil l be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
addr ess fo llowed by a '1' to indi cate receive bit. Se rial
data is rece ived via S DA, while SCL o utp uts the se ri al
clock. Se rial dat a is received 8 bit s at a time. Aft er each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate gen erator use d for the SPI mode ope ra-
tion is now used to set the SCL clock frequency for
either 100 kHz, 400 kHz, or 1 MHz I2C operation. The
baud rate generator reload value is contained in the
lower 7 bits of the SSPADD register. The baud rate
generato r will automatica lly begin counting on a write to
the SSPBUF. Once the given operation is complete,
(i.e., transmission of the last data bit is followed by
ACK), the internal clock will automa tically stop counting
and the SCL pin will remain in its last state.
A typical transmit sequence would go as follows:
a) The user generates a START condition by set-
ting the START enable bit, SEN
(SSPCON2<0>).
b) SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.
c) The user loads the SSPBUF with the ad dress to
transmit.
d) Address is shifted o ut the SD A p in un til al l 8 bits
are transmitted.
e) The MSSP modu le shift s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) The MSSP module g enerate s an interrup t at th e
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
g) The user loads the SSPBUF with eight bits of
data.
h) Dat a is shif ted out the SDA pin un til al l 8 b its ar e
transmitted.
i) The MSSP modu le shift s in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The M SSP modul e gene rates an int errupt a t the
end of th e ninth c lock cyc le by settin g the SSPIF
bit.
k) The user generates a STOP condition by setting
the STOP enable bit, PEN (SSPCON2<2>).
l) Interrupt is generated once the STOP condition
is complete.
PIC18CXX2
DS39026D-page 136 1999-2013 Microchip Technology Inc.
14.4.5 BAUD RATE GENERATOR
In I2C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 14-14). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another re load has taken place. Th e BRG count is dec-
remented twice per instruction cycle (TCY) on the Q2
and Q4 clocks. In I2C Master mode, the BRG is
reloaded automatically. If Clock Arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 14-15).
FIGURE 14-14: BAUD RATE GENER ATOR BLOCK DIAGRAM
FIGURE 14-15: BAUD RATE GENER ATOR TIMING WITH CLOCK ARBITRATION
SSPM3:SSPM0
BRG Down Counter
CLKOUT FOSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control Reload
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place and BRG start s its count.
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration) SCL allowed to transition high
BRG decrements on
Q2 and Q4 cycles
1999-2013 Microchip Technology Inc. DS39026D-page 137
PIC18CXX2
14.4.6 I2C MASTER MODE START
CONDITION TIMING
To initiate a START condi tion, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pin s are sa mp led hig h, th e ba ud rate gene ra-
tor is reloaded with the contents of SSPADD<6:0> and
starts its coun t. If SCL an d SD A are bot h s am pl ed hig h
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended
leavin g the SDA l ine h eld lo w and the START cond ition
is complete.
14.4.6.1 WCOL Status Flag
If the user writes the SSPBUF when a START
sequenc e is in pro gress , the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-16: FIRST START BIT TIMING
Note: If, a t the begi nning of the START c onditi on,
the SDA and SCL pins are already sam-
pled l ow, or if du ri ng the START con ditio n,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF is set, the START condition is
aborted, and the I2C mo dule is rese t into it s
IDLE state.
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
conditi on is complete.
SDA
SCL
S
TBRG
1st Bit 2nd Bit
TBRG
SDA = 1, At completion of STA RT bit,
SCL = 1
Write to SSPBUF occurs here
TBRG
Hardware clears SEN bit
TBRG
Write to SEN bit occurs here. Set S bit (SSPSTAT<3>)
and sets SSPIF bit
PIC18CXX2
DS39026D-page 138 1999-2013 Microchip Technology Inc.
14.4.7 I2C MASTER MODE REP EA TED
START CONDITION TIMING
A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I2C
logic module is in the idle state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sample d low , the bau d rate generato r is loaded w ith the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generato r count (TBRG). Whe n the bau d rate gen erator
tim es out, if S DA is sampl ed hi gh, t he SC L pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL mu st be samp led high f or one TBRG. This action i s
then foll owed by asserti on of the SDA p in (SDA = 0) for
one TBRG, whil e SCL is high. Fo llo wing thi s, t he RSEN
bit (SSPCON2<1>) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin h eld lo w. As soon as a START cond ition is
detected on the SDA and SCL pins, the S bit
(SSPSTA T<3>) wi ll be set. Th e SSPIF bit will not be set
until the baud rate generator has timed out.
Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the use r may then transmit an additional eight
bits of add ress (1 0-bit mod e), or ei ght bi ts o f dat a (7-b it
mode).
14.4.7.1 WCOL Status Flag
If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn’t occur).
FIGURE 14-17: REPEAT START CONDITION WAVEFORM
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated
START condition occurs if:
• SDA is sampled low when SCL goes
from low to high.
• SCL goes low before SDA is
asserted low. This may indicate that
another master is attempting to
transmit a data "1".
Note: Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.
SDA
SCL
Sr = Repeated START
Write to SSPCON2
Writ e to SSPBUF occurs here.
Falling edge of ninth clock
End of Xmit
At completion of START bit,
hardware clear RSEN bit
1st Bit
Set S (SSPSTAT<3>)
TBRG
TBRG
SDA = 1,
SDA = 1,
SCL (no change) SCL = 1
occurs here.
TBRG TBRG TBRG
and set SSPIF
1999-2013 Microchip Technology Inc. DS39026D-page 139
PIC18CXX2
14.4.8 I2C MASTER MODE
TRANSMISSION
Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address, is accomplished by sim-
ply writing a value to the SSPBUF register. This action
will set the buffer full flag bit, BF, and allow the baud
rate generator to begin counting and start the next
transmission. Each bit of address/data will be shifted
out onto the SDA pin after the falling edge of SCL is
asserted (see data hold time specification parameter
106). SCL is held low for one baud rate generator roll-
ove r co un t ( TBRG). Data should be valid before SCL is
released high (see Data setup time specification
parameter 107) . Whe n the SC L pin is rel eas ed hi gh, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
allowing the slave device being addressed to respond
with an ACK bit during the ninth bit time, if an address
match o ccurs, or if dat a was re ceived prop erly . The sta-
tus of ACK is written into the ACKDT bit on the falling
edge of the ninth clock. If the master receives an
Acknowledge, the Acknowledge status bit, ACKSTAT,
is cleare d. If not, the bi t is s et. Af te r th e n int h c lo ck, the
SSPIF bit is s et and the master c lock (b aud ra te gen er-
ator) is suspended until the next data byte is loaded into
the SSPBUF, leaving SCL low and SDA unchanged
(Figure 14-18).
After the write to the SSPBUF, each bit of address will
be shifted out on the fall ing edge of SC L un til a ll s eve n
address bits and the R/W bit are completed. On the fal l-
ing edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was rec ognized by a sla ve. The st atus of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes p lace, holding SCL
low and allowing SDA to float.
14.4.8.1 BF Status Flag
In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF a nd is clea red , whe n
all 8 bits are shifted out.
14.4.8.2 WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress, (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
WCOL must be cleared in software.
14.4.8.3 ACKSTAT Status Flag
In T ran smit mod e, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowle dge when
it has recognized its address (including a general call),
or when the slave has properly received its data.
14.4.9 I2C MASTER MODE RECE P TION
Master mode recepti on is enabl ed by pro grammin g th e
receive enable bit, RCEN (SSPCON2<3>).
The baud rate generat or be gi ns c ou nti ng, and on each
rollover, the state of the SCL pin changes (high to low/
low to high) and data is shifted into the SSPSR. After
the falling edge of the eighth clock, the receive enable
flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF fl ag bit is set and the b aud rate genera-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next com-
mand. W hen th e buf fer is re ad by th e C PU, the BF flag
bit is aut om atic al ly c lea red. The u ser c an the n s en d a n
Acknowledge bit at the end of reception, by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).
14.4.9.1 BF Status Flag
In receiv e op eration, the BF bit is set w he n an add res s
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
14.4.9.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a prev ious reception.
14.4.9.3 WCOL Status Flag
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shif ting in a data
byte), th e WCOL bi t is set an d the conte nts of th e buffer
are unchanged (the write doesn’t occur).
Note: The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.
PIC18CXX2
DS39026D-page 140 1999-2013 Microchip Technology Inc.
FIGURE 14-18 : I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
SEN
A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7D6D5D4D3D2D1D0
ACK
Transmitting Data or Second Half
R/W = 0Transmit Address to Slave
123456789 123456789 P
Cleared in software service routine
SSPBUF is written in software
From SSP inter rupt
After START conditio n SEN cleared by hardware.
S
SSPBUF written with 7 bit address and R/W
start transmit
SCL held low
while CPU
responds to SSPIF
SEN = 0
of 10-bit Address
Write SSPCON2<0> SEN = 1
START condition begins From slave clear ACKSTAT bit SSPCON2<6>
ACKSTAT in
SSPCON2 = 1
cleared in software
SSPBUF written
PEN
Cleared in software
R/W
1999-2013 Microchip Technology Inc. DS39026D-page 141
PIC18CXX2
FIGURE 14-19 : I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4 A3 A2 A1
SDA
SCL 12345678912345678 9 1234
Bus Master
terminates
transfer
ACK Receiving Data from Slave
Receiving Data from Slave D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF
BF
ACK is not sent
Write to SSPCON2<0> (SEN = 1)
Write to SSPBUF occurs here ACK from Slav e
Master configured as a receiver
by programming SSPCON2<3>, (RCEN = 1) PEN bit = 1
written here
Data shifted in on falling edge of CLK
Cleared in software
S t art XM IT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
Cleared in software
Cleared in software
Set SSPIF interrupt
at end of receive
Set P bit
(SSPSTAT<4>)
and SSPIF
Cleared in
software
ACK from Master
Set SS PIF at end
Set SSPIF interrupt
at end of Acknowledge
sequence
Set SSPIF interrupt
at end of Acknow-
ledge sequence
of receive
Set ACKEN start Acknowledge sequence
SSPOV is set because
SSPBUF is still full
SDA = ACK D T = 1
RCEN cleared
automatically
RCEN = 1 start
next receive
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5 >) = 0
RCEN cleared
automatically
responds to SSPIF
ACKEN
Begin START Condition
Cleared in software
SDA = ACKDT = 0
PIC18CXX2
DS39026D-page 142 1999-2013 Microchip Technology Inc.
14.4.10 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
is presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
startin g an Acknowledge sequenc e. The baud rate gen-
erator then counts for one rollover period (TBRG) and the
SCL pin is de-asserted (pulled high ). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for TBRG. The SCL pin is then pulled low. Fol-
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned of f and the MSSP module
then goes into IDLE mode (Figure 14-20).
14.4.10.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buf fer are un chang ed (the w rite doe sn’t
occur).
14.4.11 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive /transm it by s etting th e STOP sequ ence en able
bit, PEN (SSPCON2<2>). At the end of a receive/trans-
mit, the SCL line is held low aft er the falling edg e of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low . Wh en the SDA line is sample d
low, the baud rate generator is reloaded and counts
down to 0. Whe n the baud rate gene rator times out, the
SCL pin will be brought high, and one TBRG (baud rate
generator rollover count) later, the SDA pin will be
de-asserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 14-21).
14.4.11.1 WCOL Status Flag
If the use r writes t he SSPBUF when a STO P sequenc e
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 14-20: ACKNOW LEDGE SEQUEN CE WAVEFORM
Note: TBRG = one baud rate generator period.
SDA
SCL
Set SSPIF at the end
Acknowledge sequence starts here,
Write to SSPCON 2 ACKEN automatically cleared
Cleared in
TBRG TBRG
of receive
ACK
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
software Set SSPIF at the end
of Acknowledge sequence
Cleared in
software
1999-2013 Microchip Technology Inc. DS39026D-page 143
PIC18CXX2
FIGURE 14-21: STOP CONDITION RECEIVE OR TRANSMIT MODE
14.4.12 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated START/STOP condi-
tion, de-a sserts the SCL pin (SCL allowed to float high).
When the SCL pin is allowed to float high, the baud rate
generator (BRG) is suspended from counting until the
SCL pin i s actua ll y s amp le d hi gh. When the SCL p in i s
sample d high, the baud rate gen erator is reloa ded wi th
the contents of SSPADD<6:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count, in the event tha t the clock
is held low by an external device (Figure 14-22).
14.4.13 SLEE P OP ERATION
While in SLEEP mode, the I2C module can receive
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
14.4.14 EFFECT OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
FIGURE 14-22: CLOCK ARBITRAT ION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
SDA asserted low before rising edge of clock
Write to SSPCON2
Set PEN
Falling edge of
SCL = 1 for Tbrg, followed by SDA = 1 for Tbrg
9th clock
SCL b rought high after TBRG
Note: TBRG = one baud rate generator period.
TBRG TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set
TBRG
to setup STOP condition.
ACK
P
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
SCL
SDA
BRG overflow,
Release SCL,
If SCL = 1, Load BRG with
SSPADD<6:0>, and start count BRG overflow occurs,
Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting
clock high interval.
SCL line sampled once every machine cycle (TOSC² 4).
Hold off BRG until SCL is sampled high.
TBRG TBRG TBRG
to measure high time interval
PIC18CXX2
DS39026D-page 144 1999-2013 Microchip Technology Inc.
14.4.15 MULTI-M AST ER MODE
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET, or
when the MSSP modul e is dis abl ed . Contro l of the I2C
bus may be taken when the P bit (SSPSTA T< 4>) is set,
or the bus is id le with both the S and P bit s clear . Whe n
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored, for arbitration, to see if the signal level is the
expect ed output level. This c heck is perfo rmed in hard-
ware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
14.4.16 MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA by letting SDA float high and
another m as ter a ssert s a ' 0'. Whe n th e SC L pi n fl oats
high, data should be stable. If the expected data on
SDA is a '1' an d the da ta s ampled o n the SDA pi n = '0',
then a bus collision has taken pl ace. The master wil l set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its IDLE state (Figure 14-23).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPB UF can be writte n to. W hen the user servi ces
the bus collision Interrupt Service Routine, and if the
I2C bus is free, the user c an resume com munication b y
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de- assert ed, and t he respe ctiv e contro l bit s in
the SSPCON2 registe r are cleared. When the user s er-
vices the bus collision Interrupt Service Routine, and if
the I2C bus is free, the user can resume communication
by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be
set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I2C
bus can be t aken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
FIGURE 14-23: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
SDA
SCL
BCLIF
SDA released
SDA line pulled low
by another source Sample SDA. While SCL is high
dat a doe sn ’t matc h what is driv en
Bus collision has occurred.
Set bus collis ion
interrupt (BCLIF)
by the master.
by master
Data changes
while SCL = 0
1999-2013 Microchip Technology Inc. DS39026D-page 145
PIC18CXX2
14.4.16.1 Bus Collision During a START
Condition
During a START condition, a bus collision occurs if:
a) SDA or SC L are sampled low at the begi nning of
the START condition (Figure 14-24).
b) SCL is s am pl ed l ow be fore SD A is as se rted low
(Figure 14-25).
During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the START condition is aborted,
• the BCLIF flag is set, and
• the MSSP module is reset to its IDLE state
(Figure 14-24).
The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START co ndition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 14-26). If, howe ver , a '1' is s ampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to 0, and during this time, if the SCL pins
are sampled as '0', a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.
FIGURE 14-24: BUS COLLISION DURING START CONDITION (SDA ONLY)
Note: The re ason that bus coll ision is not a fact or
during a START condition, is that no two
bus mas ters can a ssert a START co ndition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not c aus e a bu s
collis ion, because the two masters must be
allow ed to arbitrate t he first addres s follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START, or STOP conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
SSP module reset into idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable STA RT
condition if SDA = 1, SCL=1
SDA = 0, SCL = 1.
BCLIF
S
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
. Set BCL I F,
Set BCLIF.
START condition.
PIC18CXX2
DS39026D-page 146 1999-2013 Microchip Technology Inc.
FIGURE 14-25: BUS COLLISION DURING START CONDITION (SCL = 0)
FIGURE 14-26: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA
SCL
SEN Bus collision occurs, set BCLIF
SCL = 0 before SDA = 0,
Set SEN, enable START
sequence if SDA = 1, SCL = 1
TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
Interrupt cleared
in software
Bus collision occurs, set BCLIF
SCL = 0 before BRG time-out,
'0' '0'
'0''0'
SDA
SCL
SEN
Set S
Set SEN, enable START
sequence if SDA = 1, SCL = 1
Less th an TBRG TBRG
SDA = 0, SCL = 1
BCLIF
S
SSPIF
S
Interrupts cleared
in software
Set SS PIF
SDA = 0, SCL = 1
SDA pulled lo w by othe r master.
Reset BRG and assert SDA.
SCL pulled low after BRG
Time-out
Set SS PIF
'0'
1999-2013 Microchip Technology Inc. DS39026D-page 147
PIC18CXX2
14.4.16.2 Bus Collision During a Repeated
START Condition
During a Repeated START condition, a bus collision
occu rs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
b) SCL goes low before SDA is asserted low, indi-
cating that anoth er master is attempting to trans-
mit a data ’1’ .
When the user de-asserts SDA and the pin is allowed
to float high, the BRG is loaded with SSPADD<6:0>
and counts down to 0. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled.
If SDA is l ow , a b us collisi on has occurre d (i.e., anoth er
master is attempting to transmit a data ’0’,
Figure 14-27). If SDA is sampled high, the BRG is
reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
becaus e no tw o maste rs can a ssert SDA at exactl y the
same time.
If SCL goes from hig h to low bef ore th e BR G time s o ut
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ’1’ during the Repeated START condi-
tion, Figure 14-28.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.
FIGURE 14-27: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
FIGURE 14-28: BUS COLLISION DURING REPEATED S TART CONDITION (CASE 2)
SDA
SCL
RSEN
BCLIF
S
SSPIF
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
Cleared in software
'0'
'0'
SDA
SCL
BCLIF
RSEN
S
SSPIF
Interrupt cleare d
in software
SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.
TBRG TBRG
'0'
PIC18CXX2
DS39026D-page 148 1999-2013 Microchip Technology Inc.
14.4.16.3 Bus Collision During a STOP
Condition
Bus collision occurs during a STOP condition if:
a) After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is de-asserted, SCL is sam-
pled low bef ore SDA goes hig h.
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
floa t. Wh en t he p in i s sa mpled hig h (c loc k arbi tr atio n),
the baud rate generator is loaded with SSPADD<6:0>
and cou nt s d own to 0. After the BRG times o ut, SDA i s
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0' (Figu re 14-29). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of anot her master attempt-
ing to drive a data '0' (Figure 14-30).
FIGURE 14-29: BUS COLLISION DURING A STOP CONDITION (CASE 1)
FIGURE 14-30: BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
SDA asserted low
SDA sampled
low after TBRG,
Set BCLIF
'0'
'0'
SDA
SCL
BCLIF
PEN
P
SSPIF
TBRG TBRG TBRG
Assert SDA SCL goes low before SDA goes high
Set BCLIF
'0'
'0'
1999-2013 Microchip Technology Inc. DS39026D-page 149
PIC18CXX2
15.0 ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O mo dules . (USA RT is al so kno wn as a S erial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and perso nal co mputers, or it can be confi gured
as a half-d uplex synch ronous syste m that ca n comm u-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
In order to configure pins RC6/TX/CK and RC7/RX/DT
as the Uni versal Synchronou s Async hronou s Rece iver
Transmitter:
• bit SPEN (RCSTA<7>) must be set (= 1), and
• bits TRISC<7:6> must be cleared (= 0).
Register 15-1 shows the Transmit Status and Control
Register (TXSTA) and Register 15-2 shows the
Receive Status and Control Register (RCSTA).
REGISTER 15-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC —BRGHTRMTTX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 Unimplemented: Read as '0'
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’ 1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18CXX2
DS39026D-page 150 1999-2013 Microchip Technology Inc.
REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit
1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is clea red afte r reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer
when RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of received data, can be Address/Data bit or a parity bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
1999-2013 Microchip Technology Inc. DS39026D-page 151
PIC18CXX2
15.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 15-1 shows the formula for computation of the
baud rat e for dif feren t USART modes, wh ich only a pply
in Master mode (internal clock).
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculate d
using the formula in Table 15-1. From this, the error in
baud rate can be determined.
Example 15-1 shows the calculation of the baud rate
error for the following conditions:
•F
OSC = 16 MHz
• Desired Baud R ate = 9600
• BRGH = 0
• SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
becaus e the FOSC/(16(X + 1)) equat ion c an red uce th e
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new bau d rate.
15.1.1 SAMPLING
The dat a on the RC7/RX/D T pin is sampl ed three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
EXAMPLE 15-1: CALCULATING BAUD RATE ERROR
TABLE 15-1: BAUD RATE FORMULA
TABLE 15-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Desired Baud Rate = FOSC / (64 (X + 1))
Solving for X:
X = ( (FOSC / Desired Baud rate) / 64 ) - 1
X = ((16000000 / 9600) / 64) - 1
X = [25.042] = 25
Calculated Baud Rate = 16000000 / (64 (25 + 1))
= 9615
Error = (Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
= (9615 - 9600) / 9600
=0.16%
SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Sp eed)
0
1
(Asynchron ous ) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate = FOSC/(16(X+1))
NA
Legend: X = value in SPBRG (0 to 255)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
RESETS
TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unk no w n, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
PIC18CXX2
DS39026D-page 152 1999-2013 Microchip Technology Inc.
TABLE 15-3: BAUD RATES FOR SYNCHRONOUS MODE
BAUD
RATE
(K)
FOSC = 40 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
Actual
Rate (K) %
Error
SPBRG
value
(decimal)
Actua
l Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3NA— —NA— —NA— —NA— —
1.2NA— —NA— —NA— —NA— —
2.4NA— —NA— —NA— —NA— —
9.6 NA — — NA — — NA — — 9.766 +1.73 255
19.2 NA — — 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129
76.8 76.92 0 129 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32
96 96.15 0 103 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25
300 303.03 -0.01 32 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7
500 500.00 0 19 500 0 9 500 0 7 500 0 4
HIGH 39.06 — 255 5000 — 0 4000 — 0 2500 — 0
LOW 10000.00 — 0 19.53 — 255 15.625 — 255 9.766 — 255
BAUD
RATE
(K)
FOSC = 7.15909 MHz FOSC = 5.0688 MHz FOSC = 4 MHz FOSC = 3.579545 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 NA — — NA — — NA — —— NA — —
1.2NA— — NA— — NA— — NA— —
2.4NA— — NA— — NA— — NA— —
9.6 9.622 +0.23 185 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92
19.2 19.24 +0.23 92 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46
76.8 77.82 +1.32 22 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11
96 94.20 -1.88 18 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8
300 298.3 -0.57 5 316.8 +5.60 3 NA — — 298.3 -0.57 2
500 NA — — NA — — NA — — NA — —
HIGH 1789.8 — 0 1267 — 0 100 — 0 894.9 — 0
LOW 6.991 — 255 4.950 — 255 3.906 — 255 3.496 — 255
BAUD
RATE
(K)
FOSC = 1 MHz FOSC = 32.768 kHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 NA — — 0.303 +1.14 26
1.2 1.202 +0.16 207 1.170 -2.48 6
2.4 2.404 +0.16 103 NA — —
9.6 9.615 +0.16 25 NA — —
19.2 19.24 +0.16 12 NA — —
76.8 83.34 +8.51 2 NA — —
96 NA — — NA — —
300 NA — — NA — —
500 NA — — NA — —
HIGH 250 — 0 8.192 — 0
LOW 0.9766 — 255 0.032 — 255
1999-2013 Microchip Technology Inc. DS39026D-page 153
PIC18CXX2
TABLE 15-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
RATE
(K)
FOSC = 40 MHz FOSC = 20 MHz FOSC = 16 MHz F OSC = 10 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 NA — — NA — — NA — — NA — —
1.2 NA — — 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129
2.4 2.44 -1.70 255 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64
9.6 9.62 -0.16 64 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15
19.2 18.94 +1.38 32 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7
76.8 78.13 -1.70 7 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1
96 89.29 +7.52 6 104.2 +8.51 2 NA — — NA — —
300 312.50 -4.00 1 312.5 +4.17 0 NA — — NA — —
500 625.00 -20.00 0 NA — — NA — — NA — —
HIGH 2.44 — 255 312.5 — 0 250 — 0 156.3 — 0
LOW 625.00 — 0 1.221 — 255 0.977 — 255 0.6104 — 255
BAUD
RATE
(K)
FOSC = 7.15909 MHz FOSC = 5.0688 MHz FOSC = 4 MHz FOSC = 3.579545 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 NA — — 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185
1.2 1.203 +0.23 92 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46
2.4 2.380 -0.83 46 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22
9.6 9.322 -2.90 11 9.9 +3.13 7 NA — — 9.322 -2.90 5
19.2 18.64 -2.90 5 19.8 +3.13 3 NA — — 18.64 -2.90 2
76.8 NA — — 79.2 +3.13 0 NA — — NA — —
96 NA — — NA — — NA — — NA — —
300 NA — — NA — — NA — — NA — —
500 NA — — NA — — NA — — NA — —
HIGH 111.9 — 0 79.2 — 0 62.500 — 0 55.93 — 0
LOW 0.437 — 255 0.3094 — 255 3.906 — 255 0.2185 — 255
BAUD
RATE
(K)
FOSC = 1 MHz FOSC = 32.768 kHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
0.3 0.300 +0.16 51 0.256 -14.67 1
1.2 1.202 +0.16 12 NA — —
2.4 2.232 -6.99 6 NA — —
9.6 NA — — NA — —
19.2 NA — — NA — —
76.8 NA — — NA — —
96 NA — — NA — —
300 NA — — NA — —
500 NA — — NA — —
HIGH 15.63 — 0 0.512 — 0
LOW 0.0610 — 255 0.0020 — 255
PIC18CXX2
DS39026D-page 154 1999-2013 Microchip Technology Inc.
TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
RATE
(K)
FOSC = 40 MHz FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
9.6 9.77 -1.70 255 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64
19.2 19.23 -0.16 129 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32
38.4 38.46 -0.16 64 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15
57.6 58.14 -0.93 42 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10
115.2 113.64 +1.38 21 113.63 -1.36 10 111.11 -3.55 8 125 +8.51 4
250 250.00 0 9 250 0 4 250 0 3 NA — —
625 625.00 0 3 625 0 1 NA — — 625 0 0
1250 1250.00 0 1 1250 0 0 NA — — NA — —
BAUD
RATE
(K)
FOSC = 7.16MHz FOSC = 5.068 MHz FOSC = 4 MHz FOSC = 3.579545 M Hz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
9.6 9.520 -0.83 46 9.6 0 32 NA — — 9.727 +1.32 22
19.2 19.454 +1.32 22 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11
38.4 37.286 -2.90 11 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5
57.6 55.930 -2.90 7 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3
115.2 111.860 -2.90 3 105.6 -8.33 2 19.231 +0.16 12 111.86 -2.90 1
250 NA — — NA — — NA — — 223.72 -10.51 0
625 NA — — NA — — NA — — NA — —
1250 NA — — NA — — NA — — NA — —
BAUD
RATE
(K)
FOSC = 1 MHz FOSC = 32.768 kHz
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
Actual
Rate
(K)
%
Error
SPBRG
value
(decimal)
9.6 8.928 -6.99 6 NA — —
19.2 20.833 +8.51 2 NA — —
38.4 31.25 -18.61 1 NA — —
57.6 62.5 +8.51 0 NA — —
115.2 NA — — NA — —
250 NA — — NA — —
625 NA — — NA — —
1250 NA — — NA — —
1999-2013 Microchip Technology Inc. DS39026D-page 155
PIC18CXX2
15.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits and one STO P bit). Th e most comm on dat a form at
is 8-bits. An on-chip dedicated 8-bit baud rate genera-
tor c an be us ed to deriv e standa rd baud rate frequ en-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent, but use the
same d at a format and b aud rate. T he bau d ra te gen er-
ator produces a clock, either x16 or x64 of the bit shift
rate, depe nding on bit BRGH (TXSTA<2>). Parity is not
supporte d by the hard ware, but can be imple mente d in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
15.2.1 USART ASYNCHRONOUS
TRANSMITTER
The USART transmitter block diagram is shown in
Figure 15-1. The h eart of t he trans mitte r is the t ransm it
(serial) s hift register (TSR). The shif t register obta ins its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), th e TX REG re gis ter i s em pty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit, TXIE
( PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enab le bi t TXI E and ca nno t be cl eare d in soft -
ware. It will re set only wh en ne w dat a is loa ded i nto th e
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) shows the st atus of th e TSR registe r. S t a-
tus bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
To set up an asynchronous transmission:
1. Initialize the SPBRG re gis ter for the ap prop ria te
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 15.1).
2. Enable the asy nch ron ous serial port by cle arin g
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 15-1: USART TRANSMIT BLOCK DIAGRAM
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit T XIF is set whe n enable bit TXEN
is set.
TXIF
TXIE
Interrupt
TXEN Baud Rate CLK
SPBRG
Baud Rate Generato r TX9D
MSb LSb
Data Bus
TXREG Register
TSR Regist er
(8) 0
TX9
TRMT SPEN
RC6/TX/CK pin
Pin Buffer
and Control
8
PIC18CXX2
DS39026D-page 156 1999-2013 Microchip Technology Inc.
FIGURE 15-2: ASYNCHRONOUS TRANSMISSION
FIGURE 15-3: ASYNCHRONOUS TRANSM IS SION (BACK TO BACK)
TABLE 15-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Word 1 STOP Bit
Word 1
Transmit Shift Reg
START Bit Bit 0 Bit 1 Bit 7/8
Write to TXREG Word 1
BRG Output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(Transmit buffer
reg. empt y flag)
TRMT b it
(Transmit shift
reg. empty fl ag)
Transmit Shift Reg.
Write to TXREG
BRG Output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empt y flag)
Word 1 Word 2
Word 1 Word 2
START Bit STOP Bit START Bit
Transmit Shift Reg.
Word 1 Word 2
Bit 0 Bit 1 Bit 7/8 Bit 0
Note: Thi s timing di agram shows two consecutive transmissions.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Genera tor Regi ste r 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
1999-2013 Microchip Technology Inc. DS39026D-page 157
PIC18CXX2
15.2.2 USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 15-4.
The data is receiv ed on th e R C7/R X/DT p in an d dri ve s
the data recovery block. The data recovery block is
actuall y a h igh sp ee d s hifter operating at x 16 tim es th e
baud rate , whereas the main receive serial shif ter oper-
ates at the bit rate, or at FOSC. This mode would typi-
cally be used in RS-232 systems.
To set up an Asy nchronous Recepti on:
1. Initialize th e SPBRG re gis te r for the ap prop ria te
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 15.1).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, set enable bit RCIE.
4. If 9-bit reception is desired, set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete an d an interru pt will be generate d if enabl e
bit RCIE wa s set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit C RE N.
15.2.3 SETTING UP 9-BIT MODE WITH
ADDRESS DETECT
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRG re gis ter for the ap prop ria te
baud rate. If a high spe ed ba ud rate is requ ire d,
set the BRGH bit.
2. Enable the asy nch ron ous serial port by cle arin g
the SYNC bit and setting the SPEN bit.
3. If inte rrupts a re requi red, set t he RCEN b it and
select the desired pr iority level with the RCIP bit.
4. Set the RX9 bit to enable 9-bit reception.
5. Set the ADDEN bit to enable address detect.
6. Enable reception by setting the CREN bit.
7. The RCIF bit will be set when reception is com-
plete. The interrupt will be acknowledged if the
RCIE and GIE bits are set.
8. Read the RCSTA register to determine if any
error occurred during reception, as well as read
bit 9 of da ta (if applicable).
9. Read RCREG to determine if the device is being
addressed.
10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.
FIGURE 15-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT Pin Buffer
and Control
SPEN
Data
Recovery
CREN OERR FERR
RSR Register
MSb LSb
RX9D RCREG Register FIFO
Interrupt RCIF
RCIE Data Bus
8
64
16
or STOP START(8) 7 1 0
RX9
PIC18CXX2
DS39026D-page 158 1999-2013 Microchip Technology Inc.
FIGURE 15-5: ASYNCHRONOUS RECEPTION
TABLE 15-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
START
bit bit7/8
bit1bit0 bit7/8 bit0STOP
bit
START
bit START
bit
bit7/8 STOP
bit
RX (pin)
reg
Rcv buffer reg
Rcv shift
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Word 1
RCREG Word 2
RCREG
STOP
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read af ter the third word, causing
the OERR (overrun) bit to be set.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
1999-2013 Microchip Technology Inc. DS39026D-page 159
PIC18CXX2
15.3 USART Synchronous Master
Mode
In Sync hronous Ma ster mode, the data is trans mitted in
a half-duplex manner, (i.e., transmission and reception
do not occur at the sa me time). When tran smitting dat a,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode ind icates t hat the process or transmit s th e
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
15.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 15-1. The h eart of t he trans mitte r is the t ransm it
(serial) s hift register (TSR). The shif t register obta ins its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCYCLE), the TXREG i s empt y and int er-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE, and cannot be cleared in soft-
ware. It will re set only wh en ne w dat a is loa ded i nto th e
TXREG register . While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit, which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
To set up a Synchronous Master Transmission:
1. Initialize the SPBRG re gis ter for the ap prop ria te
baud rate (Section 15.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading data t o the TXREG
register.
TABLE 15-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
V alue on all
other
RESETS
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
PIC18CXX2
DS39026D-page 160 1999-2013 Microchip Technology Inc.
FIGURE 15-6: SYNCHRONOUS TRANSMISSION
FIGURE 15-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
Bit 0 Bit 1 Bit 7
Word 1
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 2 Bit 0 Bit 1 Bit 7
RC7/RX/DT
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
(Inte rru pt flag)
TRMT
TXEN bit '1' '1'
Word 2
TRMT b it
Write Wor d 1 Write Word 2
Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
pin
RC7/RX/DT pin
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
bit0 bit1 bit2 bit6 bit7
TXEN b it
1999-2013 Microchip Technology Inc. DS39026D-page 161
PIC18CXX2
15.3.2 USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCST A<5>), or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CRE N tak es prece den ce .
To set up a Synchronous Master Reception:
1. Initialize th e SPBRG re gis te r for the ap prop ria te
baud rate (Section 15.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, set enable bit RCIE.
5. If 9-bit reception is desired, set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set wh en receptio n
is complete and an interrupt will be generated if
the enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 15-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
FIGURE 15-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
RESETS
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Master Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(interrupt)
Read
RXREG
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'0'
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
'0'
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.
PIC18CXX2
DS39026D-page 162 1999-2013 Microchip Technology Inc.
15.4 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/ CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
15.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP ins truc tio n is e xecu ted , t he following will oc c ur:
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been sh ifted out of TSR,
the TXREG register will transfer the second word
to the TSR and flag bit TXIF will now be set.
e) If enable bit TXIE is set, the interrupt will wake the
chip from SLEEP. If the global interrupt is enabled,
the pro gr am w i ll br an ch to th e in terrupt v e ct or.
To set up a Synchronous Slave Transmission:
1. Enable the sy nchronou s slave seri al port by se t-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. S tart transmission by loading data t o the TXREG
register.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on all
other
RESETS
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Transmission.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
1999-2013 Microchip Technology Inc. DS39026D-page 163
PIC18CXX2
15.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a “don't care” in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP inst ruction , then a w ord m ay be rec eived durin g
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enabl e bit RCIE bit is set , the interrupt gene rated
will wake the chip from SLEEP. If the glob al inte rrupt is
enabled , the progra m will branch to the interrupt vector .
To set up a Synchronous Sl ave Reception:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF w i ll b e se t w he n rec ept ion is com -
plete. An i nte rrupt will be gen erated if en abl e b it
RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
8. If any error occurred, clear the error by clearing
bit CREN.
TABLE 15-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR,
BOR
Value on
all other
RESETS
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x
RCREG USART Receive Register 0000 0000 0000 0000
TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented, read as '0'.
Shaded cells are not used for Synchronous Slave Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
PIC18CXX2
DS39026D-page 164 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 165
PIC18CXX2
16.0 COMPATIBLE 10-BIT ANALOG-
TO-DIGITAL CONVERTER (A/D)
MODULE
The analog-to-digital (A/D) converter module has five
inputs for the PIC18C2x2 devices and eight for the
PIC18C4x2 devices. This module has the ADCON0
and ADCON1 register definitions that are compatible
with the mid-range A/D module.
The A/D allo w s co nve rsi on of an analog input si gna l to
a corresponding 10-bit digital number.
The A/D module has four registers. These registers
are:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 16-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 16-2, configures the func-
tions of the port pins.
REGISTER 16-1: ADCON0 REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON
bit 7 bit 0
bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCO N0 bits in bold)
bit 5-3 CHS2:CHS0: Analog Channel Select bits
000 = channel 0 (AN0)
001 = channel 1 (AN1)
010 = channel 2 (AN2)
011 = channel 3 (AN3)
100 = channel 4 (AN4)
101 = channel 5 (AN5)
110 = channel 6 (AN6)
111 = channel 7 (AN7)
Note: The PIC18C2X2 devices do not implement the full 8 A/D channels; the unimplemented selections
are reserved. Do not select any unimplemented channel.
bit 2 GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conve rsion in progress (setting this bit starts the A/D conversion which is automatically
cleared by hardware when the A/D conversion is complete)
0 = A/D conve rsion not in progress
bit 1 Unimplemented: Read as '0'
bit 0 ADON: A/D On bit
1 = A/D converter module is powered up
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
ADCON1
<ADCS2> ADCON0
<ADCS1:ADCS0> Clock Conversion
000 FOSC/2
001 FOSC/8
010 FOSC/32
011 FRC (clock derived from the internal A/D RC oscillator)
100 FOSC/4
101 FOSC/16
110 FOSC/64
111 FRC (clock derived from the internal A/D RC oscillator)
PIC18CXX2
DS39026D-page 166 1999-2013 Microchip Technology Inc.
REGISTER 16-2: ADCON1 REGISTER
R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’.
0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
bit 6 ADCS2: A/D Conversion Clock Select bit (ADCON1 bit s in bold)
bit 5-4 Unimplemented: Read as '0'
bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
Note: On any de vice RESET, the port pin s that are multip lexed with an alog func tions (ANx) are
forced to be an analog input.
ADCON1
<ADCS2> ADCON0
<ADCS1:ADCS0> Clock Conv ers io n
000 FOSC/2
001 FOSC/8
010 FOSC/32
011 FRC (clock derived from the internal A/D RC oscillator)
100 FOSC/4
101 FOSC/16
110 FOSC/64
111 FRC (clock derived from the internal A/D RC oscillator)
A = Analog input D = Digital I/O
C/R = # of analog input channels/# of A/D voltage references
PCFG AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VREF+VREF- C / R
0000 A A A A A A A A VDD VSS 8 / 0
0001 A A A A VREF+A A AAN3VSS 7 / 1
0010 D D D A A A A A VDD VSS 5 / 0
0011 D D D A VREF+A A AAN3VSS 4 / 1
0100 D D D D A D A A VDD VSS 3 / 0
0101 D D D D VREF+D A AAN3VSS 2 / 1
011x D D D D D D D D — — 0 / 0
1000 A A A A VREF+VREF- A A AN3 AN2 6 / 2
1001 D D A A A A A A VDD VSS 6 / 0
1010 D D A A VREF+A A AAN3VSS 5 / 1
1011 D D A A VREF+VREF- A A AN3 AN2 4 / 2
1100 D D D A VREF+VREF- A A AN3 AN2 3 / 2
1101 D D D D VREF+VREF- A A AN3 AN2 2 / 2
1110 D D D D D D D A VDD VSS 1 / 0
1111 D D D D VREF+VREF- D A AN3 AN2 1 / 2
1999-2013 Microchip Technology Inc. DS39026D-page 167
PIC18CXX2
The analog reference voltage is software selectable to
either the device’ s positive and negative sup ply voltag e
(VDD and VSS) or the voltage level on the RA3/AN3/
VREF+ pin and RA2/AN2/VREF-.
The A/D converter has a unique feature of being able
to opera te while th e device i s in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
Each port pi n associ ated with th e A/D converter can be
configu r ed as an anal og input (RA3 ca n als o be a vol t-
age reference) or as a digital I/O.
The ADRESH an d ADRESL registers contain t he result
of the A/D conversion. When the A/D conversion is
complete, the result is loaded into the ADRESH/
ADRESL registers, the GO/DONE bit (ADCON0<2>) is
cleared, and A/D interru pt flag bit ADIF is se t. The block
diagram of the A/D module is shown in Figure 16-1.
FIGURE 16-1: A/D BLOCK DIAGRAM
(Input Volta ge)
VAIN
VREF+
Reference
voltage
VDD
PCFG0
CHS2:CHS0
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
111
110
101
100
011
010
001
000
10-bit
Converter
VREF-
VSS
A/D
PIC18CXX2
DS39026D-page 168 1999-2013 Microchip Technology Inc.
The value that is in the ADRESH/ADRESL registers is
not modified for a Power-on Reset. The ADRESH/
ADRESL registers will contain unknown data after a
Power-on Reset.
After the A/D module has been configured as desired,
the sele cted channel must be acq uire d b efore the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 16.1.
Aft er this a cquis ition time h as el apsed , th e A/D co nver-
sion ca n be sta rted . The f oll owin g ste ps shoul d be f ol-
lowed for doing an A/D conversion:
1. Configure the A/D module:
• Config ure an alog pins, volt age refere nce and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D con ve rsi on clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Con figu re A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result registers (ADRESH/ADRESL);
clear bit ADIF if required.
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquis iti on st a rts.
16.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 16-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capa citor CHOLD. The sampling
switch (RSS) impedanc e varie s over the device volt age
(VDD). The sour ce impedanc e aff ects th e offse t voltag e
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
FIGURE 16-2: ANALOG INPUT MODEL
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
VAIN CPIN
Rs ANx
5 pF
VDD
VT = 0.6V
VT = 0.6V I leakage
RIC 1k
Sampling
Switch
SS RSS
CHOLD = 120 pF
VSS
6V
Sampling Switch
5V
4V
3V
2V
567891011
(k)
VDD
± 500 nA
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
1999-2013 Microchip Technology Inc. DS39026D-page 169
PIC18CXX2
To calculate the minimum acquisition time,
Equation 16-1 may be used. This equation assumes
that 1/2 LSb erro r is used (1024 step s for the A/D). The
1/2 LSb e rror is th e ma ximu m erro r a ll owed fo r the A/D
to meet its specified resolution.
EQUATION 16-1: ACQUISITION TIME
EQUATION 16-2: A/D MINIMUM CHARGING TIME
Example 16-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following application system assump-
tions:
•C
HOLD = 120 pF
•Rs = 2.5 k
• Conve rsi on Error1/2 LSb
•V
DD = 5V Rss = 7 k
• Temperature = 50C (system max.)
•V
HOLD = 0V @ time = 0
EXAMPLE 16-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=T
AMP + TC + TCOFF
VHOLD = (VREF - (VREF/2048)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
or
TC = -(120 pF)(1 k + RSS + RS) ln(1/2047)
TACQ =TAMP + TC + TCOFF
Temperature coefficient is only required for temperatures > 25C.
TACQ =2 s + Tc + [(Temp - 25C)(0.05 s/C)]
TC=-CHOLD (RIC + RSS + RS) ln(1/2047)
-120 pF (1 k + 7 k + 2.5 k) ln(0.0004885)
-120 pF (10.5 k) ln(0.0004885)
-1.26 s (-7.6241)
9.61 s
TACQ =2 s + 9.61 s + [(50C - 25C)(0.05 s/C)]
11.61 s + 1.25 s
12.86 s
PIC18CXX2
DS39026D-page 170 1999-2013 Microchip Technology Inc.
16.2 Selecting the A/D Conversion
Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 12 TAD per 10 -bit con versi on.
The source of the A/D conversion clock is software
selectable. The seven possible options for TAD are :
•2T
OSC
•4TOSC
•8TOSC
•16TOSC
•32TOSC
•64TOSC
• Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 s.
Table 16-1 shows the resultant TAD tim es de r iv e d fr om
the device operating frequencies and the A/D clock
sour ce se lec ted .
16.3 Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspo nding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output lev el (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
TABLE 16-1: TAD vs. DEVICE OPERATING FREQUENCIES
TABLE 16-2: TAD vs. DEVICE OPERATING FREQUENCIES (FOR EXTENDED, LC, DEVICES)
Note 1: When reading the port register , all pins con-
figured as analog input channels will read as
cleared (a low level). Pins configured as dig-
ital inputs will convert an analog input. Ana-
log levels on a digitally configur ed inpu t will
not affect the conversion accuracy.
2: Analog le vels on any pin that is de fined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to con-
sume current that is out of the devices
specification.
AD Clock Source (TAD) Device Frequ enc y
Operation ADCS2:ADCS0 40 MHz 20 MHz 5 MHz 1.25 MHz 333.33 kHz
2TOSC 000 50 ns 100 ns(2) 400 ns(2) 1.6 s6 s
4TOSC 100 100 ns 200 ns(2) 800 ns(2) 3.2 s12 s
8TOSC 001 200 ns 400 ns(2) 1.6 s6.4 s24 s(3)
16TOSC 101 400 ns 800 ns(2) 3.2 s12.8 s48 s(3)
32TOSC 010 800 ns 1.6 s6.4 s25.6 s(3) 96 s(3)
64TOSC 110 1.6 s3.2 s12.8 s51.2 s(3) 192 s(3)
RC 011 2 - 6 s(1) 2 - 6 s(1) 2 - 6 s(1) 2 - 6 s(1) 2 - 6 s(1)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
AD Clock Source (TAD) Device Frequency
Operation ADCS2:ADCS0 4 MHz 2 MHz 1.25 MHz 333.33 kHz
2TOSC 000 500 ns(2) 1.0 s(2) 1.6 s(2) 6 s
4TOSC 100 1.0 s(2) 2.0 s(2) 3.2 s(2) 12 s
8TOSC 001 2.0 s(2) 4.0 s6.4 s24 s(3)
16TOSC 101 4.0 s(2) 8.0 s 12.8 s48 s(3)
32TOSC 010 8.0 s16.0 s25.6 s(3) 96 s(3)
64TOSC 110 16.0 s32.0 s51.2 s(3) 192 s(3)
RC 011 3 - 9 s(1,4) 3 - 9 s(1,4) 3 - 9 s(1,4) 3 - 9 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 6 s.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
1999-2013 Microchip Technology Inc. DS39026D-page 171
PIC18CXX2
16.4 A/D Conversions
Figure 16-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the las t val ue writ ten to th e ADRESH:ADRESL re g-
isters). After the A/D convers ion is ab orted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, acquisition on the selected channel is
automatically started.
16.5 Use of the CCP2 Trigger
An A/D convers ion can be st arted by th e “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011 and that the A/D m od ule is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D conversion and
the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (A DON i s cleared), the
“special event trigger” will be ignored by the A/D mod-
ule, but will still reset the Timer1 (or Ti mer3) cou nter.
FIGURE 16-3: A/D CONVERSION TAD CYCLES
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
TAD1TAD2TAD3 TAD4TAD5 TAD6TAD7TAD8 TAD11
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
b9 b8 b7 b6 b5 b4 b3 b2 TAD9TAD10
b1 b0
TCY - TAD
Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
Conversion Starts
b0
PIC18CXX2
DS39026D-page 172 1999-2013 Microchip Technology Inc.
TABLE 16-3: SUMMARY OF A/D REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on
POR, BOR
Value on all
other
RESETS
INTCON GIE/
GIEH PEIE/
GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
PIR2 — — — — BCLIF LVDIF TMR3IF CCP2IF ---- 0000 ---- 0000
PIE2 — — — — BCLIE LVDIE TMR3IE CCP2IE ---- 0000 ---- 0000
IPR2 — — — — BCLIP LVDIP TMR3IP CCP2IP ---- 0000 ---- 0000
ADRESH A/D Result Register xxxx xxxx uuuu uuuu
ADRESL A/D Result Register xxxx xxxx uuuu uuuu
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/
DONE —ADON0000 00-0 0000 00-0
ADCON1 ADFM ADCS2 —— PCFG3 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
PORTA — RA6 RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
TRISA — PORTA Data Direction Register --11 1111 --11 1111
PORTE — — — — —RE2RE1RE0---- -000 ---- -000
LATE — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu
TRISE IBF OBF IBOV PSPMODE — PORTE Dat a Direction bits 0000 -111 0000 -111
Legend: x = unknown, u = unchanged, — = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: The PSPIF, PSPIE and PSP IP bits are reserved on the PIC18C2X2 devices. Always maintain these bits clear.
1999-2013 Microchip Technology Inc. DS39026D-page 173
PIC18CXX2
17.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the
device voltage (VDD) is below a specified voltage level
is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do “housekeeping tasks” before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the v oltage of the device be comes lower then the
specif ied poin t, an inter rupt fl ag is set. If the interrupt is
enabled , the program exec ution will bran ch to the inter-
rupt vec tor addre ss and the sof tware can then res pond
to that interrupt source.
The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be “turned
off” by the software, which minimizes the current con-
sumption for the device.
Figur e 17-1 sho ws a po ssible a pplication v olt age curve
(typically for batteries). Over time, the device voltage
decreas es. When the dev ice voltage equals voltage VA,
the LVD logic generates an interrupt. This occurs at
time TA. The application software then has the time,
until the device voltage is no longer in valid operating
range, to shut-dow n the sys tem. Voltage poin t VB is the
minimum valid operating voltage specification. This
occurs at time TB. The difference TB - TA is the total
time for shut-down.
FIGURE 17-1: TYPICAL LOW VOLTAGE DETECT APPLICATION
The block diagram for the LVD module is shown in
Figure 17-2. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a “trip
point” voltage. The “trip point” voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage
refe rence mod ule. T he comparat or then ge nerates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 17-2). The trip point is selected by program-
ming the LVDL3:LVDL0 bits (LVDCON<3:0>).
Time
Voltage
VA
VB
TATB
VA = LVD trip point
VB = Minimum valid device
operating voltage
Legend:
PIC18CXX2
DS39026D-page 174 1999-2013 Microchip Technology Inc.
FIGURE 17-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM
The LVD module has an additional feature that allows
the user to supply the trip voltage to the module from
an external source. This mode is enabled when bits
LVDL3:LVDL0 are set to 1111. In this state, the com-
parator input is multiplexed from the external input pin
LVDIN (Figure 17-3).
This gives flexibility, because it allows a user to config-
ure the Low Voltage Detect interrupt to occur at any
voltage in the valid operating range.
FIGURE 17-3: LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
LVDIF
VDD
16 to 1 MUX
LVDEN
LVD Control
Register
Internally Generated
Nominal Reference Voltage
LVDIN
1.2V
LVD
EN
LVD Control
16 to 1 MUX
BGAP
BODEN
LVDEN
VxEN
LVDIN
Register
VDD VDD
Externally Generated
Trip Point
1999-2013 Microchip Technology Inc. DS39026D-page 175
PIC18CXX2
17.1 Control Register
The Low Voltage Detect Control register controls the
operation of the Low Voltage Detect circuitry.
REGISTER 17-1: LVDCON REGISTER
U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
—— IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0
bit 7 bit 0
bit 7-6 Unimplemented: Read as '0'
bit 5 IRVST: Internal Reference Voltage Stable Flag bit
1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the
specified voltage range
0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the
specified voltage range and the LVD interrupt should not be enabled
bit 4 LVDEN: Low Voltage Detect Power Enab le bit
1 = Enables LVD, powers up LVD circuit
0 = Disables LVD, powers down LVD circuit
bit 3-0 LVDL3:LVDL0: Low Voltage Detection Limit bits
1111 = External analog input is used (input comes from the LVDIN pin)
1110 = 4.5V min. - 4.77V max.
1101 = 4.2V min. - 4.45V max.
1100 = 4.0V min. - 4.24V max.
1011 = 3.8V min. - 4.03V max.
1010 = 3.6V min. - 3.82V max.
1001 = 3.5V min. - 3.71V max.
1000 = 3.3V min. - 3.50V max.
0111 = 3.0V min. - 3.18V max.
0110 = 2.8V min. - 2.97V max.
0101 = 2.7V min. - 2.86V max.
0100 = 2.5V min. - 2.65V max.
0011 = 2.4V min. - 2.54V max.
0010 = 2.2V min. - 2.33V max.
0001 = 2.0V min. - 2.12V max.
0000 = 1.8V min. - 1.91V max.
Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage
of the device are not tested.
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ - n = Value at POR reset
PIC18CXX2
DS39026D-page 176 1999-2013 Microchip Technology Inc.
17.2 Operation
Depen ding on the power s our ce for th e devi ce vol tag e,
the voltage normally decreases relatively slowly. This
means that the LVD module does not need to be con-
stantly operating. To decrease the current require-
ments, the LVD circuitry only needs to be enabled for
short periods, where the voltage is checked. After
doing the check, the LVD module may be disabled.
Each tim e that the LVD module i s enab led, th e circ uitry
requires some time to stabilize. After the circuitry has
stabilized, all status flags may be cleared. The module
will then indicate the proper state of the system.
The following steps are needed to set up the LVD module:
1. Write the value to the LVDL3:LVDL0 bits (LVD-
CON register), which selects the desired LVD
Trip Point.
2. Ensure that LVD interrupts are disabled (the
LVDIE bit is cleared, or the GIE bit is cleared).
3. Enable the LVD module (set the LVDEN bit in
the LVDCON register).
4. Wait for the LVD module to stabilize (the IRVST
bit to become set).
5. Clear the LVD interrupt flag, which may have
falsely become set until the LVD module has
stabilized (clear the LVDIF bit).
6. Enable the LVD interrupt (s et the LVDIE and the
GIE bits).
Figure 17-4 shows typical waveforms that the LVD
module may be used to detect.
FIGURE 17-4: LOW VOLT AGE DETECT WAVEFORMS
VLVD
VDD
LVDIF
VLVD
VDD
Enable LVD
Internally Generated 50 ms
LVDIF may not be set
Enable LVD
50 ms
LVDIF
LVDIF cleared in software
LVDIF cleared in software
LVDIF cleared in software,
CAS E 1:
CAS E 2:
LVDIF remains set since LVD condition still exists
Reference stable
Internally Generated
Reference stable
1999-2013 Microchip Technology Inc. DS39026D-page 177
PIC18CXX2
17.2.1 REFERENCE VOLTAGE SET POINT
The Internal Reference Voltage of the LVD module may
be used by other internal circuitry (the Programmable
Brown-out Reset). If these circuits are disabled (lower
current consumption), the reference voltage circuit
requires a time to become stable before a low voltage
condition can be reliably detected. This time is invariant
of system clock speed. This start-up time is specified in
electrical specification parameter #36. The low voltage
interrupt flag will not be enabled until a stable reference
voltage is reached. Refer to the waveform in Figu re 17-4.
17.2.2 CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and
voltage divider are enabled and will consume static cur-
rent. The voltage divider can be tapped from multiple
places in the resistor array. Total current consumption,
when enabled, is specified in electrical specification
parameter #D022B.
17.3 Operation During SLEEP
When enabled, the LVD circuitry continues to operate
during SLEEP. If the device voltage crosses the trip
point, the L VDIF bit will be set and the device will wak e-
up from SLEEP. Device execution will continue from
the interru pt vector address, if interrupts have been glo-
bally enabled.
17.4 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the LVD module to be turned off.
PIC18CXX2
DS39026D-page 178 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 179
PIC18CXX2
18.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and o ffer code prot ectio n. These are:
• OSC Selection
• RESET
- Powe r-on Reset (POR )
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-circuit Serial Programming
All PIC1 8CXX2 devic es have a W atchd og T imer, which
is permanently enabled via the configuration bits or
software-controlled. It runs off its own RC oscillator for
added reli ability. There are two time rs th at offer neces-
sary del ays o n power-up . One i s the Oscil lator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
18.1 Configuration Bits
The configuration b its can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/
Unprogrammed
Value
300000h CONFIG1L CP CP CP CP CP CP CP CP 1111 1111
300001h CONFIG1H —— OSCSEN —— FOSC2 FOSC1 FOSC0 111- -111
300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111
300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111
300005h CONFIG3H — — — — — — — CCP2MX ---- ---1
300006h CONFIG4L — — — — — — LVEN STVREN ---- --11
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 0000 0000
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0010
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’
PIC18CXX2
DS39026D-page 180 1999-2013 Microchip Technology Inc.
REGISTER 18-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 300001h)
REGISTER 18-2: CONFIGURATION REGISTER 1 LOW (CONFIG1L: BYTE ADDRESS 300000h)
R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1
Reserved Reserved OSCSEN —— FOSC2 FOSC1 FOSC0
bit 7 bit 0
bit 7-6 Reserved: Read as ’1’
bit 5 OSCSEN: Oscillator System Clock Switch Enable bit
1 = Oscillator system clock switch option is disabled (main oscillator is source)
0 = Oscillator system clock switch option is enabled (oscillator switching is enabled)
bit 4-3 Unimplemented: Read as ’0’
bit 2-0 FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator w/OSC2 configured as RA6
110 = HS oscillator with PLL enabled/Clock frequency = (4 x FOSC)
101 = EC oscillator w/OSC2 configured as RA6
100 = EC oscillator w/OSC2 configured as divide-by-4 clock output
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
CP CP CP CP CP CP CP CP
bit 7 bit 0
bit 7-0 CP: Code Protection bits (apply when in Code Protected Microcontroller mode)
1 = Program memory code protection off
0 = All of program memory code protected
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
1999-2013 Microchip Technology Inc. DS39026D-page 181
PIC18CXX2
REGISTER 18-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003h)
REGISTER 18-4: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 300002h)
U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
— — — — WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0
bit 7-4 Unimplemented: Read as ’0’
bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111 = 1:1
110 = 1:2
101 = 1:4
100 = 1:8
011 = 1:16
010 = 1:32
001 = 1:64
000 = 1:128
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTEN bit)
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1
— — — — BORV1 BORV0 BOREN PWRTEN
bit 7 bit 0
bit 7-4 Unimplemented: Read as ’0’
bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 1 BOREN: Brown-out Reset Enable bit(1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
Note: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardles s of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
bit 0 PWRTEN: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
Note: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT),
regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled any
time Brown-out Reset is enabled.
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
PIC18CXX2
DS39026D-page 182 1999-2013 Microchip Technology Inc.
REGISTER 18-5: CONFIGURATION REGISTER 3 HIGH (CONFIG3H: BYTE ADDRESS 300005h)
REGISTER 18-6: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 300006h)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1
— — — — — — — CCP2MX
bit 7 bit 0
bit 7-1 Unimplemented: Read as ’0’
bit 0 CCP2MX: CCP2 Mux bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1
— — — — — — Reserved STVREN
bit 7 bit 0
bit 7-2 Unimplemented: Read as ’0’
bit 1 Reserved: Maintain this bit set
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack Full/Underflow will cause RESET
0 = Stack Full/Underflow will not cause RESET
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state
1999-2013 Microchip Technology Inc. DS39026D-page 183
PIC18CXX2
18.2 Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external compo-
nent s. T his RC oscilla tor is s ep arate from the R C osci l-
lator of the OSC1/CLKI pin. That means that the WDT
will run, even if the clock on the OSC1/CLKI and OSC2/
CLKO/RA6 pins of the device has been stopped, for
exampl e, by ex ecu tion of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (W atchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software exe-
cution m ay not di sable thi s function. W hen the WD TEN
configuration bit is cleared, the SWDTEN bit enables/
disables the operation of the WDT.
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.
18.2.1 CONTROL REGISTER
Register 18-7 shows the WDTCON register. This is a
readable and wri table re gister, which cont ains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.
REGISTER 18-7: WDTCON REGISTER
Note: The CLRWDT and SLEEP instructi on s cl ear
the WDT and the pos tscaler, if assign ed to
the WDT, and prevent it from timing out
and generat ing a device RESET condi tion.
Note: When a CLRWDT instruction is executed
and the pos tsca ler is assi gned to the WD T,
the post scaler count will be c leared, but the
postscaler assignment is not changed.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —SWDTEN
bit 7 bit 0
bit 7-1 Unimplemented: Read as ’0’
bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration
register = ’0’
Legend:
R = Readable bit W = Writable bit
U = Unimplemented bit, read as ‘0’ - n = Value at POR Reset
PIC18CXX2
DS39026D-page 184 1999-2013 Microchip Technology Inc.
18.2.2 WDT POS TSCAL ER
The WDT has a postscaler that can extend the WDT
Reset period. The postscaler is selected at the time of
device programming, by the value written to the
CONFIG2H configuration register.
FIGURE 18-1: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 18-2: SUMMARY OF WATCHDOG TIMER REGISTERS
Postscaler
WDT Timer
WDTEN
8 - to - 1 MUX WDTPS2:WDTPS0
WDT
Time-out
8
SWDTEN bit
Configuration bit
Note: WDPS2:WDPS0 are bits in register CONFIG2H.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CONFIG2H ———— WDTPS2 WDTPS2 WDTPS0 WDTEN
RCON IPEN LWRT —RI TO PD POR BOR
WDTCON ———————SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
1999-2013 Microchip Technology Inc. DS39026D-page 185
PIC18CXX2
18.3 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lo west curr ent c onsum pti on in this mo de, plac e all
I/O pins at either VDD or VSS, ensure no external cir-
cuitr y is dr awing cu rrent from th e I/O pi n, powe r-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid s witchi ng curre nts caus ed by fl oating input s. Th e
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
18.3.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or a
Peripheral Interrupt.
The follo wing periph eral interrupt s can wake the device
from SLEEP:
1. PSP read or write.
2. TMR1 interrup t. T imer1 m ust be ope rating as an
asynchronous counter.
3. TMR3 interrup t. T imer3 m ust be ope rating as an
asynchronous counter.
4. CCP capture mode inte rrup t .
5. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
6. MSSP (START/STOP) bit detect interrupt.
7. MSSP transmit or receive in Slave mode
(SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a “wake-up”. The TO and PD
bits in th e RCO N r egiste r can be us ed to determ ine th e
cause of the de vice RESET. The PD bit, which is se t on
powe r-up, is cleared w hen SLEEP is in voked. Th e TO
bit is cleared, if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up thro ugh an interrupt eve nt, the co rres pon din g
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
ins tructi on afte r the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruct ion after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should hav e a NOP after the SLEEP instruction.
18.3.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and inte rrupt fla g bit s et, one of the fo llow ing wil l occu r:
• If an interrupt conditi on (interru pt flag bit and inter-
rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will comple te as a NOP. Therefore, the WDT and
WDT pos tsc aler wil l not be c leared , the T O bit will
not be set and PD bits will not be cleared.
• If the interrupt condition occurs during or after
the execution of a SLEEP instructi on, the dev ic e
will immediatel y wake u p from SLE EP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postsc aler will be clear ed, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction c ompletes. To
determine whether a SLEEP ins tructio n execut ed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instr uc-
tion should be executed before a SLEEP instruction.
PIC18CXX2
DS39026D-page 186 1999-2013 Microchip Technology Inc.
FIGURE 18-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
18.4 Program Verification/Code
Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for ver ification purposes.
18.5 ID Locations
Five m emory loc ations (2 00000h - 200004h) are desi g-
nated as ID loc ati ons , whe r e th e us er c an st ore ch ec k-
sum or other code identification numbers. These
locations are accessible during normal execution
through t he TBLRD instru ction or du ring progra m/verify.
The ID locations can be read when the device is code
protected.
18.6 In-Circuit Serial Programming
PIC18CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and dat a, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF Flag
(INTCON<1>)
GIEH bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
PC PC+2 PC+4
Inst(PC) = SLEEP
Inst(PC - 1)
Inst(PC + 2)
SLEEP
Processor in
SLEEP
Interrupt Latency(3)
Inst(PC + 4)
Inst(PC + 2)
Inst(0008h) Inst(000Ah)
Inst(0008h)
Dummy cycle
PC + 4 0008h 000Ah
Dummy cycle
TOST(2)
PC+4
Note 1: XT, HS or LP oscillator mode assumed.
2: GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
3: TOST = 1024TOSC (drawing not to scale) This delay will not occur for RC and EC osc modes.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
Note: Microchip Technology does not recom-
mend code protect ing windowed devices.
1999-2013 Microchip Technology Inc. DS39026D-page 187
PIC18CXX2
19.0 INSTRUCTION SET SUMMARY
The PIC18CXXX instruction set adds many enhance-
ments to the previous PIC inst ruction sets, while main -
taining an easy migration from these PIC MCU
instr uction sets.
Most instructions are a single program memory word
(16-bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
•Byte-oriented operations
•Bit-oriented operations
•Literal operati ons
•Control operations
The PIC18CXXX instruction set summary in Table 19-2
lists byte-oriented, bit-oriented, literal and control
operatio ns. Table 19-1 shows the opc ode fie ld des crip-
tions.
Most byte-oriented in str uct ions have three op eran ds :
1. The file register (specified by ‘f’)
2. The destination of the result (specified by ‘d’)
3. The access ed memory (specified by ‘a’)
The file re gis ter designator 'f' spec ifies which file regi s-
ter is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1. The file register (specified by ‘f’)
2. The bit in the file register (specified by ‘b’)
3. The access ed memory (specified by ‘a’)
The bit fi el d designa tor 'b ' s el ec t s t he n um ber of the bit
affected by the operation, while the file register desig-
nator 'f' represents the number of the file in which the
bit is located.
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
(specified by ‘k’)
• The desired FS R regi ster to load the lit eral value
into (specified by ‘f’)
• No operand required (specified by ‘—’)
The control ins tructions ma y use so me of the foll owing
operands:
• A program memory address (specified by ‘n’)
• The mode of the Call or Return instructions
(specified by ‘s’)
• The mode of the Table Read and Table Write
ins tructions (specified by ‘m’)
• No operand required (specified by ‘—’)
All instru cti ons are a sing le w or d, ex ce pt fo r thre e dou-
ble word instructions. These three instructions were
made double word instructions so that all the required
info rma tion is a vail abl e in th ese 32-bi ts. In th e se cond
word, the 4 MSb’s are 1’s. If this second word is exe-
cuted as an instruction (by itself), it will execute as a
NOP.
All single word instructions are executed in a single
inst ruct ion c yc le , un le ss a conditio nal te st is tru e or the
program counter is changed as a result of the instruc-
tion. In th ese cases, the execution takes tw o instruction
cycle s, with the addit ional instru ction cyc le(s) exec uted
as a NOP.
The doubl e word inst ructions ex ecute in two i nstructio n
cycles.
One in struction cycle consist s of f our oscil lator p eriods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two wor d branch instructions (if true) would take 3 s.
Figur e 19-1 show s the gener al format s that the ins truc-
tions can have.
All examples use the format ‘nnh’ to represent a
hexadecimal number, where ‘h’ si gn i fie s a he xa deci -
mal digit.
The Instruction Set Summary, shown in Table 19-2,
lists the instructions recognized by the Microchip
assembler (MPASMTM).
Section 19.1 prov ides a desc ription of ea ch inst ruction.
PIC18CXX2
DS39026D-page 188 1999-2013 Microchip Technology Inc.
TABLE 19-1: OPCODE FIELD DESCRIPTIONS
Field Description
aRAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7)
BSR Bank Select Register. Used to select the current RAM bank.
dDestination select bit;
d = 0: store result in WREG,
d = 1: store result in file register f.
dest Destination either the WREG register or the specified register file location
f8-bit Register file address (0x00 to 0xFF)
fs 12-bit Register file address (0x000 to 0xFFF). This is the source address.
fd 12-bit Register file address (0x000 to 0xFFF). This is the destination address.
kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)
label Label name
mm The mode of the TBLPTR register for the Table Read and Table Write instructions
Only used with Table Read and Table Write instructions:
*No Change to register (such as TBLPTR with Table reads and writes)
*+ Post-Increm ent register (such as TBLPT R with Table reads and writes)
*- Post-Decrement register (such as TBLPTR with Table reads and writes)
+* Pre-Increment register (such as TBLPTR with Table reads and writes)
nThe relative address (2’s complem ent numb er) for relative branch instructions, or the direct address for
Call/Branch and Return instructions
PRODH Product of Multiply high byte
PRODL Product of Multiply low byte
sFast Call/Return mode select bit.
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
uUnused or Unchanged
WREG Working register (accumulator)
xDon't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.
TBLPTR 21-bit Table Pointe r (points to a Program Memory location)
TABLAT 8-bit Table Latch
TOS Top-of-Stack
PC Program Counter
PCL Program Counter Low Byte
PCH Program Counter High Byte
PCLATH Program Counter High Byte Latch
PCLATU Program Counter Upper Byte Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer
TO Time-out bit
PD Power-down bit
C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative
[ ] Optional
( ) Contents
Assigned to
< > Register bit field
In the set of
italics User defined term (font is courier)
1999-2013 Microchip Technology Inc. DS39026D-page 189
PIC18CXX2
FIGURE 19-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations
15 10 9 8 7 0
d = 0 for result destination to be WREG register
OPCODE d a f (FILE #)
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
Bit-oriented file register operations
15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #)
b = 3-bit position of bit in file register (f)
Literal operations
15 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
Byte to Byte move operations (2-word)
15 12 11 0
OPCODE f (Source FILE #)
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal)
n = 20-bit immediate value
a = 1 for BSR to select bank
f = 8-bit file register address
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address
15 12 11 0
1111 n<19:8> (liter a l )
15 12 11 0
1111 f (Destin a tion FILE #)
f = 12-bit file register address
Control operations
Example Instruction
ADDWF MYREG, W, B
MOVFF MYREG1, MYREG2
BSF M YREG, bit, B
MOVLW 0x7F
GOTO Label
15 8 7 0
OPCODE n<7:0> (literal)
15 12 11 0
n<19:8> (liter a l )
CALL MYFUNC
15 11 10 0
OPCODE n<10:0> (literal)
S = Fast bit
BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
S
PIC18CXX2
DS39026D-page 190 1999-2013 Microchip Technology Inc.
TABLE 19-2: PIC18CXXX INSTRUCTION SET
Mnemonic,
Operands Description Cycles 16-bit Instruction Word Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF
MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB
SUBWF
SUBWFB
SWAPF
TSTFSZ
XORWF
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
fs, fd
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a
Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Comple ment f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Inc rement f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move f s (source) to 1st word
fd (destination)2nd word
Move WREG to f
Multipl y WR EG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f
1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
1
0010
0010
0001
0110
0001
0110
0110
0110
0000
0010
0100
0010
0011
0100
0001
0101
1100
1111
0110
0000
0110
0011
0100
0011
0100
0110
0101
0101
0101
0011
0110
0001
01da
00da
01da
101a
11da
001a
010a
000a
01da
11da
11da
10da
11da
10da
00da
00da
ffff
ffff
111a
001a
110a
01da
01da
00da
00da
100a
01da
11da
10da
10da
011a
10da
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None
None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N
C, DC, Z, OV, N
C, DC, Z, OV, N
None
None
Z, N
1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1
1, 2
1, 2
1, 2
1, 2
4
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG
f, b, a
f, b, a
f, b, a
f, b, a
f, d, a
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f
1
1
1 (2 or 3)
1 (2 or 3)
1
1001
1000
1011
1010
0111
bbba
bbba
bbba
bbba
bbba
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
None
None
None
None
None
1, 2
1, 2
3, 4
3, 4
1, 2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 wo rd instructions. The s econd word of thes e inst ructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to inte rnal memory, the write will continue until terminated.
1999-2013 Microchip Technology Inc. DS39026D-page 191
PIC18CXX2
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n
n
n
n
n
n
n
n
n, s
—
—
n
—
—
—
—
n
s
k
s
—
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word
2nd word
Clear Watchdog Timer
Deci mal Adjust WREG
Go to address1st word
2nd word
No Operation
No Operation (Note 4)
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into standby mode
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2
1
1
2
1
1
1
1
2
1
2
2
2
1
1110
1110
1110
1110
1110
1110
1110
1101
1110
1110
1111
0000
0000
1110
1111
0000
1111
0000
0000
1101
0000
0000
0000
0000
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
0000
1111
kkkk
0000
xxxx
0000
0000
1nnn
0000
0000
1100
0000
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0100
0111
kkkk
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
None
None
None
None
None
None
None
None
None
TO, PD
C
None
None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD
TABLE 19-2: PIC18CXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 word instructions. The second word of thes e inst ructions will be execut ed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to inte rnal memory, the write will continue until terminated.
PIC18CXX2
DS39026D-page 192 1999-2013 Microchip Technology Inc.
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR
MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW
k
k
k
f, k
k
k
k
k
k
k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word
to FSRx 1st word
Move literal to BSR<3:0>
Move literal to WREG
Multipl y literal w ith WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG
1
1
1
2
1
1
1
2
1
1
0000
0000
0000
1110
1111
0000
0000
0000
0000
0000
0000
1111
1011
1001
1110
0000
0001
1110
1101
1100
1000
1010
kkkk
kkkk
kkkk
00ff
kkkk
0000
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z, OV, N
Z, N
Z, N
None
None
None
None
None
C, DC, Z, OV, N
Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*
Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-inc rement
2
2 (5)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
1001
1010
1011
1100
1101
1110
1111
None
None
None
None
None
None
None
None
TABLE 19-2: PIC18CXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles 16-bit Instruction Word Status
Affected Notes
MSb LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is
driven low by an external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
4: Some instructions are 2 wo rd instructions. The s econd word of thes e inst ructions will be executed as a NOP,
unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to inte rnal memory, the write will continue until terminated.
1999-2013 Microchip Technology Inc. DS39026D-page 193
PIC18CXX2
19.1 Instruction Set
ADDLW ADD literal to WREG
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (WREG) + k WREG
Status Affected: N,OV, C, DC, Z
Encoding: 0000 1111 kkkk kkkk
Desc ript ion : The content s of WREG are add ed
to the 8 -bit literal ' k' and the re sult is
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
Data Write to
WREG
Example:ADDLW 0x15
Before Instruction
WREG = 0x10
After Instruction
WREG = 0x25
ADDWF ADD WREG to f
Syntax: [ label ] ADDWF f [,d [,a] f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) + (f) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0010 01da ffff ffff
Description: Add WREG to register 'f'. If 'd' is 0,
the result is stored in WREG. If 'd'
is 1, th e result i s sto red bac k in reg-
ister 'f' (default). If ‘a’ is 0, the
Access Bank will be selected. If ‘a’
is 1, the BSR is used.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:ADDWF REG, 0, 0
Before Instruc tio n
WREG = 0x17
REG = 0xC2
After Instruction
WREG = 0xD9
REG = 0xC2
PIC18CXX2
DS39026D-page 194 1999-2013 Microchip Technology Inc.
ADDWFC ADD WREG and Carry bit to f
Syntax: [ label ] ADDWFC f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) + (f) + (C) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Descript ion: Add WREG, th e Carry Flag and dat a
memory location 'f'. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed in data memory
location 'f'. If ‘a’ is 0, the Access
Bank will be selected. If ‘a’ is 1, the
BSR will not be overridden.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:ADDWFC REG, 0, 1
Before Instruction
Carry bit= 1
REG = 0x02
WREG = 0x4D
After Instruction
Carry bit= 0
REG = 0x02
WREG = 0x50
ANDLW AND literal with WREG
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operati on: (WR EG) .AND . k WREG
Status Af fe cte d: N,Z
Encoding: 0000 1011 kkkk kkkk
Descr ipti on : The co ntents of WREG are ANDed
with the 8 - bit li teral 'k' . Th e re su lt i s
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'k' Process
Data Write to
WREG
Example:ANDLW 0x5F
Before Instruc tio n
WREG = 0xA3
After Instruction
WREG = 0x03
1999-2013 Microchip Technology Inc. DS39026D-page 195
PIC18CXX2
ANDWF AND WREG with f
Syntax: [ label ] ANDWF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) .AND. (f) dest
Status Affected: N,Z
Encoding: 0001 01da ffff ffff
Desc ription: The con tents of WREG are AND’ ed
with register 'f'. If 'd' is 0, the result
is stored in WREG. If 'd' is 1, the
result is sto r ed bac k in regi ste r 'f'
(default). If ‘a’ is 0, the Access
Bank w il l be se lec te d. If ‘a’ is 1, the
BSR will not be overridden
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:ANDWF REG, 0, 0
Before Instruction
WREG = 0x17
REG = 0xC2
After Instruction
WREG = 0x02
REG = 0xC2
BC Branch if Carry
Syntax: [ label ] BC n
Operands: -128 n 127
Operation: if carry bit is ’1’
(PC) + 2 + 2n PC
Status Af fe cte d: None
Encoding: 1110 0010 nnnn nnnn
Description: If the Carry bit is ’1’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BC 5
Before Instruc tio n
PC = address (HERE)
After Instruction
If Carry = 1;
PC = address (HERE+12)
If Carry 0;
PC = address (HERE+2)
PIC18CXX2
DS39026D-page 196 1999-2013 Microchip Technology Inc.
BCF Bit Clear f
Syntax: [ label ] BCF f,b[,a]
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 0 f<b>
Status Affected: None
Encoding: 1001 bbba ffff ffff
Description: Bit 'b' in register 'f' is cleared. If ‘a’
is 0, the Access Bank will be
selec ted, over riding the BSR value .
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
register 'f'
Example:BCF FLAG_REG, 7, 0
Before Instruction
FLAG_REG = 0xC7
After Instruction
FLAG_REG = 0x47
BN Branch if Negative
Syntax: [ label ] BN n
Operands: -128 n 127
Operation: if negative bit is ’1’
(PC) + 2 + 2n PC
Status Af fe cte d: None
Encoding: 1110 0110 nnnn nnnn
Description: If the Negative bit is ’1’, then the
progr am w ill branc h.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BN Jump
Before Instruc tio n
PC = address (HERE)
After Instruction
If Negative = 1;
PC = address (Jump)
If Negative 0;
PC = address (HERE+2)
1999-2013 Microchip Technology Inc. DS39026D-page 197
PIC18CXX2
BNC Branch if Not Carry
Syntax: [ label ] BNC n
Operands: -128 n 127
Operation: if carry bit is ’0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0011 nnnn nnnn
Description: If the Carry bit is ’0’, then the pro-
gram will branch.
The 2’s complem en t number ’ 2n ’ is
added to the PC. Since the PC wil l
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BNC Jump
Before Instruction
PC = address (HERE)
After Instruction
If Carry = 0;
PC = address (Jump)
If Carry 1;
PC = address (HERE+2)
BNN Branch if Not Negative
Syntax: [ label ] BNN n
Operands: -128 n 127
Operation: if negative bit is ’0’
(PC) + 2 + 2n PC
Status Af fe cte d: None
Encoding: 1110 0111 nnnn nnnn
Description: If the Negative bit is ’0’, then the
progr am w ill branc h.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BNN Jump
Before Instruc tio n
PC = address (HERE)
After Instruction
If Negative 0;
PC = address (Jump)
If Negative = 1;
PC = address (HERE+2)
PIC18CXX2
DS39026D-page 198 1999-2013 Microchip Technology Inc.
BNOV Branch if Not Overflow
Syntax: [ label ] BNOV n
Operands: -128 n 127
Operation: if overflow bit is ’0’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0101 nnnn nnnn
Description: If the Overflow bit is ’0’, then the
program will branch.
The 2’s complem en t number ’ 2n ’ is
added to the PC. Since the PC wil l
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BNOV Jump
Before Instruction
PC = address (HERE)
After Instruction
If Overflow = 0;
PC = address (Jump)
If Overflow 1;
PC = address (HERE+2)
BNZ Branch if Not Zero
Syntax: [ label ] BNZ n
Operands: -128 n 127
Operati on: i f zero bit is ’0’
(PC) + 2 + 2n PC
Status Af fe cte d: None
Encoding: 1110 0001 nnnn nnnn
Description: If the Zero bit is ’0’, then the pro-
gram will branch.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BNZ Jump
Before Instruc tio n
PC = address (HERE)
After Instruction
If Zero = 0;
PC = address (Jump)
If Zero 1;
PC = address (HERE+2)
1999-2013 Microchip Technology Inc. DS39026D-page 199
PIC18CXX2
BRA Unconditional Branch
Syntax: [ label ] BRA n
Operands: -1024 n 1023
Operation: (PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 0nnn nnnn nnnn
Description: Add the 2’s complement number
’2n’ to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2 n. T his i ns truc tio n is a tw o-
cycle instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE BRA Jump
Before Instruction
PC = address (HERE)
After Instruction
PC = address (Jump)
BSF Bit Set f
Syntax: [ label ] BSF f,b[,a]
Operands: 0 f 255
0 b 7
a [0,1]
Operation: 1 f<b>
Status Af fe cte d: None
Encoding: 1000 bbba ffff ffff
Description: Bit 'b' in register 'f' is set. If ‘a’ is 0
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the b ank wi ll be selec ted as per th e
BSR value.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
register 'f'
Example:BSF FLAG_REG, 7, 1
Before Instruc tio n
FLAG_REG= 0x0A
After Instruction
FLAG_REG= 0x8A
PIC18CXX2
DS39026D-page 200 1999-2013 Microchip Technology Inc.
BTFSC Bit Test File, Skip if Clear
Syntax: [ label ] BTFSC f,b[,a]
Operands: 0 f 255
0 b 7
a [0,1]
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 1011 bbba ffff ffff
Description: If bit 'b' in register ’f' is 0, then the
next instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched du ring th e c urre nt i ns truc tio n
execution is discarded, and a NOP is
execu ted ins tead, making this a two-
cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSC
:
:
FLAG, 1, 0
Before Instruction
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (TRUE)
If FLAG<1> = 1;
PC = address (FALSE)
BTFSS Bit Test File, Skip if Set
Syntax: [ label ] BTFSS f,b[,a]
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: skip if (f<b>) = 1
Status Af fe cte d: None
Encoding: 1010 bbba ffff ffff
Descr iption: If bit 'b' in register 'f' i s 1 then the next
instr uction is skipped.
If bit 'b' is 1, the n the ne xt instruction
fetched during the current instruc-
tion execution, is discarded and a
NOP is executed instead, making this
a two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1(2)
Note: 3 cycl es if skip and followe d
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE
FALSE
TRUE
BTFSS
:
:
FLAG, 1, 0
Before Instruc tio n
PC = address (HERE)
After Instruction
If FLAG<1> = 0;
PC = address (FALSE)
If FLAG<1> = 1;
PC = address (TRUE)
1999-2013 Microchip Technology Inc. DS39026D-page 201
PIC18CXX2
BTG Bit Toggle f
Syntax: [ label ] BTG f,b[,a]
Operands: 0 f 255
0 b < 7
a [0,1]
Operation: (f<b>) f<b>
Status Affected: None
Encoding: 0111 bbba ffff ffff
Description: Bit 'b' in data memory locat ion 'f' is
inverted. If ‘a’ is 0, the Access Bank
will be selected, overriding the BSR
value. I f ‘a’ = 1, the n th e ban k w il l be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
register 'f'
Example:BTG PORTC, 4, 0
Before Instruction:
PORTC = 0111 0101 [0x75]
After Instruction:
PORTC = 0110 0101 [0x65]
BOV Branch if Overflow
Syntax: [ label ] BOV n
Operands: -128 n 127
Operation: if overflow bit is ’1’
(PC) + 2 + 2n PC
Status Af fe cte d: None
Encoding: 1110 0100 nnnn nnnn
Description: If the Overflow bit is ’1’, then the
progr am w ill branc h.
The 2’s complement number ’2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two -cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump :Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BOV Jump
Before Instruc tio n
PC = address (HERE)
After Instruction
If Overflow = 1;
PC = address (Jump)
If Overflow 0;
PC = address (HERE+2)
PIC18CXX2
DS39026D-page 202 1999-2013 Microchip Technology Inc.
BZ Branch if Zero
Syntax: [ label ] BZ n
Operands: -128 n 127
Operation: if Zero bit is ’1’
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1110 0000 nnnn nnnn
Description: If the Zero bit is ’1’, then the pro-
gram will branch.
The 2’s complem en t number ’ 2n ’ is
added to the PC. Since the PC wil l
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
If Jump: Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data Write to PC
No
operation No
operation No
operation No
operation
If No Jump:
Q1 Q2 Q3 Q4
Decode Read literal
'n' Process
Data No
operation
Example:HERE BZ Jump
Before Instruction
PC = address (HERE)
After Instruction
If Zero = 1;
PC = address (Jump)
If Zero 0;
PC = address (HERE+2)
CALL Subroutine Call
Syntax: [ label ] CALL k [,s]
Operands: 0 k 1048575
s [0,1]
Operati on: (PC) + 4 TOS,
k PC<20:1>,
if s = 1
(WREG) WS,
(STATUS) STATUSS,
(BSR) BSRS
Status Af fe cte d: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111
110s
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: Subroutine call of entire 2M byte
memory range. First, return
address (PC+ 4) is pushe d onto the
return stack. If ’s’ = 1, the W,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then the 20-bit
value ’k’ is loaded into PC<20:1>.
CALL is a two-cycle instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'k'<7:0>, Push PC to
stack Read literal
’k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:HERE CALL THERE,1
Before Instruc tio n
PC = Address(HERE)
After Instruction
PC = Address(THERE)
TOS = Address (HERE + 4)
WS = WREG
BSRS= BSR
STATUSS = STATUS
1999-2013 Microchip Technology Inc. DS39026D-page 203
PIC18CXX2
CLRF Clear f
Syntax: [label] CLRF f [,a]
Operands: 0 f 255
a [0,1]
Operation: 000h f
1 Z
Status Affected: Z
Encoding: 0110 101a ffff ffff
Description: Clears the contents of the specified
registe r. If ‘a’ is 0 , th e Ac ce ss Bank
will be selected, overriding the BSR
value. If ‘a’ = 1, then the bank will
be selec ted as per the BSR valu e
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
register 'f'
Example:CLRF FLAG_REG,1
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 000h WDT,
000h WDT postscaler,
1 TO,
1 PD
Status Af fe cte d: TO, PD
Encoding: 0000 0000 0000 0100
Description: CLRWDT instruction resets the
Watchdog Timer. It also resets the
postscaler of the WDT. Status bits
TO and PD are set.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data No
operation
Example:CLRWDT
Before Instruc tio n
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT Postscaler = 0
TO =1
PD =1
PIC18CXX2
DS39026D-page 204 1999-2013 Microchip Technology Inc.
COMF Complement f
Syntax: [ label ] COMF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: dest
Status Affected: N,Z
Encoding: 0001 11da ffff ffff
Desc ript ion : T he con ten t s of regi ste r 'f' are com-
plemented. If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the
result is sto r ed bac k in regi ste r 'f'
(default). If ‘a’ is 0, the Access
Bank w ill b e selec ted, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:COMF REG, 0, 0
Before Instruction
REG = 0x13
After Instruction
REG = 0x13
WREG = 0xEC
(f)
CPFSEQ Compare f with WREG,
skip if f = WREG
Syntax: [ label ] CPFSEQ f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) – (WREG),
skip if (f) = (WREG)
(unsign ed comp aris on )
Status Af fe cte d: None
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data
memory location 'f' to the contents
of WREG by perfor ming an
unsign ed sub t ract i on.
If 'f' = WREG, then the fetched
instruction is discarded and a NOP
is executed instead, maki ng thi s a
two- cycle instruction. If ‘ a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1 , then
the bank wi ll be selec ted as p er the
BSR value (defaul t).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruc tio n
PC Address = HERE
WREG = ?
REG = ?
After Instruction
If REG = WREG;
PC = Address (EQUAL)
If REG WREG;
PC = Address (NEQUAL)
1999-2013 Microchip Technology Inc. DS39026D-page 205
PIC18CXX2
CPFSGT Compare f with WREG,
skip if f > WREG
Syntax: [ label ] CPFSGT f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) WREG),
skip if (f) > (WREG)
(unsigned comparison)
Status Affected: None
Encoding: 0110 010a ffff ffff
Description: Compares the contents of data
memory location 'f' to the contents
of the WRE G by performing an
unsign ed su btraction.
If the content s of 'f ' are great er than
the contents of WREG, then the
fetched instruct ion is disca rded and
a NOP is executed instead, making
this a two-cycle instruction. If ‘a’ is
0, the Access Bank will be
selec ted, over riding the BSR value .
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2 -word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSGT REG, 0
NGREATER :
GREATER :
Before Instruction
PC = Address (HERE)
WREG = ?
After Instruction
If REG > WREG;
PC = Address (GREATER)
If REG WREG;
PC = Address (NGREATER)
CPFSLT Compare f with WREG ,
skip if f < WREG
Syntax: [ label ] CPFSLT f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) –WREG),
skip if (f) < (WREG)
(unsign ed comp aris on )
Status Af fe cte d: None
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data
memory location 'f' to the contents
of WREG by perfor ming an
unsigned subtraction.
If the contents of 'f' are less than
the contents of WREG, then the
fetched instruct ion is dis carded and
a NOP is execut ed instead, making
this a two-cycle instruction. If ‘a’ is
0, the Access Bank will be
selec ted. If ’a’ is 1, the BSR w i ll no t
be overridden (default).
Words: 1
Cycles: 1(2)
Note: 3 cycl es if ski p and fol low e d
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE CPFSLT REG, 1
NLESS :
LESS :
Before Instruc tio n
PC = Address (HERE)
W= ?
After Instruction
If REG < WREG;
PC = Address (LESS)
If REG WREG;
PC = Address (NLESS)
PIC18CXX2
DS39026D-page 206 1999-2013 Microchip Technology Inc.
DAW Decimal Adjust WREG Register
Syntax: [label] DAW
Operands: None
Operati on: If [WREG <3:0> > 9] or [DC = 1] th en
(WREG<3:0>) + 6 WREG<3:0>;
else
(WREG<3:0>) WREG<3:0>;
If [WREG<7:4> >9] or [C = 1] then
(WREG<7:4>) + 6 WREG<7:4>;
else
(WREG<7:4>) WREG<7:4>;
Status Affected: C
Encoding: 0000 0000 0000 0111
Desc ript ion : DAW adjust s the eig ht-b it val ue in
WREG, resulting from the earlier
addition of two variables (each in
packed BCD format) and produces
a correct packed BCD result.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register
WREG
Process
Data Write
WREG
Example1:DAW
Before Instruction
WREG = 0xA5
C=0
DC = 0
After Instruction
WREG = 0x05
C=1
DC = 0
Example 2:
Before Instruction
WREG = 0xCE
C=0
DC = 0
After Instruction
WREG = 0x34
C=1
DC = 0
DECF Decrement f
Syntax: [ label ] DECF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest
Status Affected: C,DC,N,OV,Z
Encoding: 0000 01da ffff ffff
Descr iption : Decreme nt regist er 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the resu lt is stor ed bac k in regi ste r
'f' (default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:DECF CNT, 1, 0
Before Instruc tio n
CNT = 0x01
Z=0
After Instruction
CNT = 0x00
Z=1
1999-2013 Microchip Technology Inc. DS39026D-page 207
PIC18CXX2
DECFSZ Decrement f, skip if 0
Syntax: [ label ] DECFSZ f [,d [,a]]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if resu lt = 0
Status Affected: None
Encoding: 0010 11da ffff ffff
Desc ript ion : The content s of regi ste r 'f' are
decrem ented. If 'd' i s 0, the resu lt is
placed in WREG. If 'd' is 1, the
result is placed back in regi ster 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank w ill b e selec ted, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DECFSZ CNT, 1, 1
GOTO LOOP
CONTINUE
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT - 1
If CNT = 0;
PC = Address (CONTINUE)
If CNT 0;
PC = Address (HERE+2)
DCFSNZ Decrement f, skip if not 0
Syntax: [label] DCFSNZ f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – 1 dest,
skip if result 0
Status Af fe cte d: None
Encoding: 0100 11da ffff ffff
Description: The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is place d back i n register 'f'
(default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead, making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected,
overridi ng the BSR v alue. I f ’a’ = 1,
then the bank will be selected as
per the BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE DCFSNZ TEMP, 1, 0
ZERO :
NZERO :
Before Instruc tio n
TEMP = ?
After Instruction
TEMP = TEMP - 1,
If TEMP = 0;
PC = Address (ZERO)
If TEMP 0;
PC = Address (NZERO)
PIC18CXX2
DS39026D-page 208 1999-2013 Microchip Technology Inc.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 1048575
Operation: k PC<20:1>
Status Affected: None
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>) 1110
1111
1111
k19kkk
k7kkk
kkkk
kkkk0
kkkk8
Description: GOTO allows an unconditional
branch anywhere within entire
2 Mbyte memory range. The 20-bit
value ’k’ is loaded into PC<20:1>.
GOTO is always a two-cycle
instruction.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'k'<7:0>, No
operation Read literal
’k’<19:8>,
Write to PC
No
operation No
operation No
operation No
operation
Example:GOTO THERE
After Instruction
PC = Address (THERE)
INCF I ncrem ent f
Syntax: [ label ] INCF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest
Status Af fe cte d: C,DC, N ,OV,Z
Encoding: 0010 10da ffff ffff
Description: The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is place d back i n register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:INCF CNT, 1, 0
Before Instruc tio n
CNT = 0xFF
Z=0
C=?
DC = ?
After Instruction
CNT = 0x00
Z=1
C=1
DC = 1
1999-2013 Microchip Technology Inc. DS39026D-page 209
PIC18CXX2
INCFSZ Increment f, skip if 0
Syntax: [ label ] INCFSZ f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if resu lt = 0
Status Affected: None
Encoding: 0011 11da ffff ffff
Desc ript ion : The content s of regi ste r 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is placed back in regi ster 'f'
(default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ’a’ is 0, the Access
Bank w ill b e selec ted, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycl es if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
CNT = CNT + 1
If CNT = 0;
PC = Address(ZERO)
If CNT 0;
PC = Address(NZERO)
INFSNZ Increment f, skip if not 0
Syntax: [label] INFSNZ f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) + 1 dest,
skip if result 0
Status Af fe cte d: None
Encoding: 0100 10da ffff ffff
Description: The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in WREG. If 'd' is 1, the
result is place d back i n register 'f'
(default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead, making it a two-
cycle instruction. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ = 1, then
the b ank wi ll be selec ted as per th e
BSR value (defaul t).
Words: 1
Cycles: 1(2)
Note: 3 cycl es if skip and follow e d
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE INFSNZ REG, 1, 0
ZERO
NZERO
Before Instruc tio n
PC = Address (HERE)
After Instruction
REG = REG + 1
If REG 0;
PC = Address (NZERO)
If REG = 0;
PC = Address (ZERO)
PIC18CXX2
DS39026D-page 210 1999-2013 Microchip Technology Inc.
IORLW Inclusive OR literal with WREG
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (WREG) .OR. k WREG
Status Affected: N,Z
Encoding: 0000 1001 kkkk kkkk
Desc ript ion : The content s of WR EG are OR’ ed
with the eight-bit literal 'k'. The
result is placed in WR EG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
Data Write to
WREG
Example:IORLW 0x35
Before Instruction
WREG = 0x9A
After Instruction
WREG = 0xBF
IORWF Inclusive OR WREG with f
Syntax: [ label ] IORWF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) .OR. (f) dest
Status Af fe cte d: N,Z
Encoding: 0001 00da ffff ffff
Description: Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selec ted, overri ding the BSR value .
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:IORWF RESULT, 0, 1
Before Instruc tio n
RESULT = 0x13
WREG = 0x91
After Instruction
RESULT = 0x13
WREG = 0x93
1999-2013 Microchip Technology Inc. DS39026D-page 211
PIC18CXX2
LFSR Load FSR
Syntax: [ label ] LFSR f,k
Operands: 0 f 2
0 k 4095
Operation: k FSRf
Status Affected: None
Encoding: 1110
1111
1110
0000
00ff
k7kkk
k11kkk
kkkk
Desc ription : The 12-bit litera l 'k' is l oaded in to
the file select register pointed to
by 'f'.
Words: 2
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'k' MSB Process
Data Write
literal 'k'
MSB to
FSRfH
Decode Read literal
'k' L S B Process
Data Write literal
'k' to FSRf L
Example:LFSR 2, 0x3AB
After Instruction
FSR2H = 0x03
FSR2L = 0xAB
MOVF Move f
Syntax: [ label ] MOVF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: f dest
Status Af fe cte d: N,Z
Encoding: 0101 00da ffff ffff
Description: The contents of register 'f' are
moved to a destination dependent
upon the status of ’d’. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is placed back in register
'f' (default). Location 'f' can be any-
where in the 256 byte bank. If ’a’ is
0, the Access Bank will be
selec ted, overri ding the BSR value .
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Wri te W REG
Example:MOVF REG, 0, 0
Before Instruc tio n
REG = 0x22
WREG = 0xFF
After Instruction
REG = 0x22
WREG = 0x22
PIC18CXX2
DS39026D-page 212 1999-2013 Microchip Technology Inc.
MOVFF Move f to f
Syntax: [label] MOVFF fs,fd
Operands: 0 fs 4095
0 fd 4095
Operation: (fs) fd
Status Affected: None
Encoding:
1st word (source)
2nd word (destin.) 1100
1111
ffff
ffff
ffff
ffff
ffffs
ffffd
Description: The contents of source register 'fs'
are moved to destination register
'fd'. Location of source 'fs' can be
anywhere in the 4096 byte data
spa ce (00 0h to FFF h), and locati on
of destin ation 'fd' can also be any-
where from 000h to FFFh.
Either so urc e or de st ination ca n be
WREG (a usef ul spe ci al si tuation).
MOVFF is particularly useful for
transfer ring a data memory location
to a periph eral register (such as the
transmit buffer or an I/O port).
The MOVFF instruction cannot use
the PCL, T OSU, T OSH or TOSL as
the destination register.
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
(src)
Process
Data No
operation
Decode No
operation
No dummy
read
No
operation Write
register 'f'
(dest)
Example:MOVFF REG1, REG2
Before Instruction
REG1 = 0x33
REG2 = 0x11
After Instruction
REG1 = 0x33,
REG2 = 0x33
MOVLB Move literal to low nibble in BSR
Syntax: [ label ] MOVLB k
Operands: 0 k 255
Operation: k BSR
Status Af fe cte d: Non e
Encoding: 0000 0001 kkkk kkkk
Description: The 8-bit literal 'k' is loaded into
the Bank Select Register (BSR).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'k' Process
Data Write
literal 'k' to
BSR
Example:MOVLB 5
Before Instruc tio n
BSR register = 0x02
After Instruction
BSR register = 0x05
1999-2013 Microchip Technology Inc. DS39026D-page 213
PIC18CXX2
MOVLW Move literal to WREG
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k WREG
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Desc ription : The eigh t-bit lit eral 'k ' is load ed into
WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
Data Write to
WREG
Example:MOVLW 0x5A
After Instruction
WREG = 0x5A
MOVWF Move WREG to f
Syntax: [ label ] MOVWF f [,a]
Operands: 0 f 255
a [0,1]
Operation: (WREG) f
Status Af fe cte d: None
Encoding: 0110 111a ffff ffff
Description: Move data from WREG to register
'f'. Location 'f' can be anywhere in
the 256 byte bank. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the b ank wi ll be selec ted as per th e
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
register 'f'
Example:MOVWF REG, 0
Before Instruc tio n
WREG = 0x4F
REG = 0xFF
After Instruction
WREG = 0x4F
REG = 0x4F
PIC18CXX2
DS39026D-page 214 1999-2013 Microchip Technology Inc.
MULLW Multiply Literal with WREG
Syntax: [ label ] MULLW k
Operands: 0 k 255
Operation: (WREG) x k PRODH:PRODL
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Desc ription : An unsigned multipl icati on is car-
ried out between the contents of
WREG and the 8-bit literal 'k'.
The 16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
WREG is unchanged.
None of the status flags are
affected.
Note that neither overflow, nor
carry is possible in this opera-
tion. A z ero re sult is po ss ible bu t
not detected.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
Data Write
registers
PRODH:
PRODL
Example:MULLW 0xC4
Before Instruction
WREG = 0xE2
PRODH = ?
PRODL = ?
After Instruction
WREG = 0xE2
PRODH = 0xAD
PRODL = 0x08
MULWF Multiply WREG with f
Syntax: [ label ] MULWF f [,a]
Operands: 0 f 255
a [0,1]
Operation: (WREG) x (f) PRODH:PRODL
Status Af fe cte d: Non e
Encoding: 0000 001a ffff ffff
Descr iption : An unsigned multipl icati on is car-
ried out between the contents of
WREG and the register file loca-
tion 'f'. The 16-bit result is stored
in the PROD H:PROD L register
pair . PRODH contains the high
byte.
Both WREG and 'f' are
unchanged.
None of the status flags are
affected.
Note that neither overflow, nor
carry is possible in this opera-
tion. A zero resul t is poss ible but
not detected. If ‘a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ‘a’=
1, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
registers
PRODH:
PRODL
Example:MULWF REG, 1
Before Instruc tio n
WREG = 0xC4
REG = 0xB5
PRODH = ?
PRODL = ?
After Instruction
WREG = 0xC4
REG = 0xB5
PRODH = 0x8A
PRODL = 0x94
1999-2013 Microchip Technology Inc. DS39026D-page 215
PIC18CXX2
NEGF Negate f
Syntax: [label] NEGF f [,a]
Operands: 0 f 255
a [0,1]
Operation: ( f ) + 1 f
Status Affected: N,OV, C, DC, Z
Encoding: 0110 110a ffff ffff
Description: Location ‘f’ is negated using two’s
compl ement. The re sult is pla ced in
the data memory location 'f'. If ’a’ is
0, the Access Bank will be
selec ted, over riding the BSR value .
If ’a’ = 1, then the bank will be
selected as per the BSR value.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
register 'f'
Example:NEGF REG, 1
Before Instruction
REG = 0011 1010 [0x3A]
After Instruction
REG = 1100 0110 [0xC6]
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Af fe cte d: None
Encoding: 0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
Description: No operation.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
Example:
None.
PIC18CXX2
DS39026D-page 216 1999-2013 Microchip Technology Inc.
POP Pop Top of Return Stack
Syntax: [ label ] POP
Operands: None
Operation: (TOS) bit bucket
Status Affected: None
Encoding: 0000 0000 0000 0110
Description: The TOS value is pulled off the
return stack and is discarded. The
T OS val ue then becomes the previ-
ous val ue that was pushe d onto the
return stack.
This instruction is provided to
enable the user to properly manage
the return stack to incorporate a
software stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation POP TOS
value No
operation
Example:POP
GOTO NEW
Before Instruction
TOS = 0031A2h
Stack (1 level down)= 014332h
After Instruction
TOS = 014332h
PC = NEW
PUSH Push Top of Return Stack
Syntax: [ label ] PUSH
Operands: None
Operation: (PC+2) TOS
Status Af fe cte d: None
Encoding: 0000 0000 0000 0101
Descr iption: The PC+2 is pus hed onto the top of
the return stack. The previous TOS
value is pushed down on the stack.
This instruction allows to implement
a sof tware stac k by modifyi ng TOS,
and then push it onto the return
stack.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode PUSH PC+2
onto return
stack
No
operation No
operation
Example:PUSH
Before Instruc tio n
TOS = 00345Ah
PC = 000124h
After Instruction
PC = 000126h
TOS = 000126h
Stack (1 level down) = 00345Ah
1999-2013 Microchip Technology Inc. DS39026D-page 217
PIC18CXX2
RCALL Relative Call
Syntax: [ label ] RCALL n
Operands: -1024 n 1023
Operation: (PC) + 2 TOS,
(PC) + 2 + 2n PC
Status Affected: None
Encoding: 1101 1nnn nnnn nnnn
Description: Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since t he PC will hav e incremented
to fetch the next instruction, the
new address will be PC+ 2+2n.
This instruction is a two-cycle
instruction.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read literal
'n'
Push PC to
stack
Process
Data Write to PC
No
operation No
operation No
operation No
operation
Example:HERE RCALL Jump
Before Instruction
PC = Address(HERE)
After Instruction
PC = Address(Jump)
TOS = Address (HERE+2)
RESET Reset
Syntax: [ label ] RESET
Operands: None
Operation: Reset all registers and flags that
are affected by a MCLR reset.
Status Af fe cte d: All
Encoding: 0000 0000 1111 1111
Description: This instruction provides a way to
execute a MCLR Reset in software.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Start
reset No
operation No
operation
Example:RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
PIC18CXX2
DS39026D-page 218 1999-2013 Microchip Technology Inc.
RETFIE Return from Interrupt
Syntax: [ label ] RETFIE [s]
Operands: s [0,1]
Operation: (TOS) PC,
1 GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) WREG ,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH,PEIE/GIEL.
Encoding: 0000 0000 0001 000s
Description: Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit . If ‘s’ = 1, the contents of
the shadow regi ste rs WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STAT US and BSR. If
‘s’ = 0, no upda te o f these regist ers
occurs (default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation pop PC from
stack
Set GIEH or
GIEL
No
operation No
operation No
operation No
operation
Example:RETFIE 1
After Interrupt
PC = TOS
W=WS
BSR = BSRS
STATUS = STATUSS
GIE/GIEH, PEIE/GIEL= 1
RETLW Return Literal to WREG
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k WREG,
(TOS) PC,
PCLATU, PCLATH are unchanged
Status Af fe cte d: None
Encoding: 0000 1100 kkkk kkkk
Description: WREG is loaded with the eight-bit
literal 'k'. Th e program counter i s
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
Data pop PC from
stack, Write
to WREG
No
operation No
operation No
operation No
operation
Example:
CALL TABLE ; WREG contains table
; offset value
; WREG now has
; table value
:
TABLE
ADDWF PCL ; WREG = offset
RETLW k0 ; Begin table
RETLW k1 ;
:
:
RETLW kn ; End of table
Before Instruc tio n
WREG = 0x07
After Instruction
WREG = value of kn
1999-2013 Microchip Technology Inc. DS39026D-page 219
PIC18CXX2
RETURN Return from Subroutine
Syntax: [ label ] RETURN [s]
Operands: s [0,1]
Operation: (TOS) PC,
if s = 1
(WS) WREG ,
(STATUSS) STATUS,
(BSRS) BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counte r . If ‘s’= 1, the c ontents of the
shadow regi ste rs WS, STATUSS
and BSRS are lo aded int o their cor-
responding registers, WREG,
STATUS and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data pop PC from
stack
No
operation No
operation No
operation No
operation
Example:RETURN
After Interrupt
PC = TOS
RLCF Rotate Left f through Carry
Syntax: [ label ] RLCF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n+1>,
(f<7>) C,
(C) dest<0>
Status Af fe cte d: C,N,Z
Encoding: 0011 01da ffff ffff
Description: The contents of register 'f' ar e
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:RLCF REG, 0, 0
Before Instruc tio n
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
WREG = 1100 1100
C=1
Cregister f
PIC18CXX2
DS39026D-page 220 1999-2013 Microchip Technology Inc.
RLNCF Rotate Left f (no carry)
Syntax: [ label ] RLNCF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n+1>,
(f<7>) dest<0>
Status Affected: N,Z
Encoding: 0100 01da ffff ffff
Description: The contents of register 'f' are
rotated one bit to the left. If 'd' is 0,
the result is placed in WREG. If 'd'
is 1, th e re su lt i s s tored back i n re g-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a ’ is 1, then
the bank wi ll be selec ted as per th e
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:RLNCF REG, 1, 0
Before Instruction
REG = 1010 1011
After Instruction
REG = 0101 0111
register f
RRCF Rotate Right f through Carry
Syntax: [ label ] RRCF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n-1>,
(f<0>) C,
(C) dest<7>
Status Af fe cte d: C,N , Z
Encoding: 0011 00da ffff ffff
Description: The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is place d back i n register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:RRCF REG, 0, 0
Before Instruc tio n
REG = 1110 0110
C=0
After Instruction
REG = 1110 0110
WREG = 0111 0011
C=0
Cregister f
1999-2013 Microchip Technology Inc. DS39026D-page 221
PIC18CXX2
RRNCF Rotate Right f (no carry)
Syntax: [ label ] RRNCF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<n>) dest<n-1>,
(f<0>) dest<7>
Status Affected: N,Z
Encoding: 0100 00da ffff ffff
Desc ript ion : The content s of regi ste r 'f' are
rotat ed one bi t to the right. I f 'd' is 0,
the result is placed in WREG. If 'd'
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding th e BSR value. If ’ a’ is 1, then
the bank wi ll be selec ted as p er the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example 1:RRNCF REG, 1, 0
Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011
Example 2:RRNCF REG, 0, 0
Before Instruction
WREG = ?
REG = 1101 0111
After Instruction
WREG = 1110 1011
REG = 1101 0111
register f
SETF Set f
Syntax: [label] SETF f [,a]
Operands: 0 f 255
a [0,1]
Operation: FFh f
Status Af fe cte d: None
Encoding: 0110 100a ffff ffff
Description: The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding th e BSR value. If ’a ’ is 1, then
the b ank wi ll be selec ted as per th e
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write
register 'f'
Example:SETF REG,1
Before Instruc tio n
REG = 0x5A
After Instruction
REG = 0xFF
PIC18CXX2
DS39026D-page 222 1999-2013 Microchip Technology Inc.
SLEEP Enter SLEEP mode
Syntax: [ label ] SLEEP
Operands: None
Operation: 00h WDT,
0 WDT postscaler,
1 TO,
0 PD
Status Affected: TO, PD
Encoding: 0000 0000 0000 0011
Descript ion: The po wer-down statu s bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its po s tscale r are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation Process
Data Go to
sleep
Example:SLEEP
Before Instruction
TO =?
PD =?
After Instruction
TO =1 †
PD =0
† If WDT causes wake-up, this bit is cleared.
SUBFWB Subtract f from WREG with bo rrow
Syntax: [ label ] SUBFWB f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) – (f) – (C) dest
Status Af fe cte d: N,OV, C, DC, Z
Encoding: 0101 01da ffff ffff
Description: Subtract register 'f' and carry flag
(borrow) from WREG (2’s comple-
ment method). If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result
is stored in register 'f' (default). If ’a’ is
0, the Access Bank will be selected,
overriding the BSR value. If ’a’ is 1,
then the bank will be selected as per
the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example 1:SUBFWB REG, 1, 0
Before Instruc tio n
REG = 3
WREG = 2
C=1
After Instruction
REG = FF
WREG = 2
C=0
Z=0
N = 1 ; result is negative
Example 2:SUBFWB REG, 0, 0
Before Instruc tio n
REG = 2
WREG = 5
C=1
After Instruction
REG = 2
WREG = 3
C=1
Z=0
N = 0 ; result is positive
Example 3:SUBFWB REG, 1, 0
Before Instruc tio n
REG = 1
WREG = 2
C=0
After Instruction
REG = 0
WREG = 2
C=1
Z = 1 ; result is zero
N=0
1999-2013 Microchip Technology Inc. DS39026D-page 223
PIC18CXX2
SUBLW Subtract WREG from literal
Syntax: [ label ]SUBLW k
Operands: 0 k 255
Operation: k – (WREG) WREG
Status Affected: N,OV, C, DC, Z
Encoding: 0000 1000 kkkk kkkk
Description: WREG is subtracted from the
eight-bit literal 'k'. The result is
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
Data Write to
WREG
Example 1: SUBLW 0x02
Before Instruction
WREG = 1
C=?
After Instruction
WREG = 1
C = 1 ; result is positive
Z=0
N=0
Example 2:SUBLW 0x02
Before Instruction
WREG = 2
C=?
After Instruction
WREG = 0
C = 1 ; result is zero
Z=1
N=0
Example 3:SUBLW 0x02
Before Instruction
WREG = 3
C=?
After Instruction
WREG = FF ; (2’s complement)
C = 0 ; result is negative
Z=0
N=1
SUBWF Subtract WREG from f
Syntax: [ label ]SUBWF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operati on: (f) – (WREG) dest
Status Af fe cte d: N,OV, C, DC, Z
Encoding: 0101 11da ffff ffff
Description: Subtract WREG from register 'f'
(2’s complement method). If 'd' is
0, the result is stored in WREG. If
'd' is 1, the result is stored back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected,
overriding the BSR value. If ’a’ is
1, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example 1:SUBWF REG, 1, 0
Before Instruc tio n
REG = 3
WREG = 2
C=?
After Instruction
REG = 1
WREG = 2
C = 1 ; result is positive
Z=0
N=0
Example 2:SUBWF REG, 0, 0
Before Instruc tio n
REG = 2
WREG = 2
C=?
After Instruction
REG = 2
WREG = 0
C = 1 ; result is zero
Z=1
N=0
Example 3:SUBWF REG, 1, 0
Before Instruc tio n
REG = 1
WREG = 2
C=?
After Instruction
REG = FFh ;(2’s complement)
WREG = 2
C = 0 ; result is negative
Z=0
N=1
PIC18CXX2
DS39026D-page 224 1999-2013 Microchip Technology Inc.
SUBWFB Subtract WR EG from f wit h Borrow
Syntax: [ label ] SUBWFB f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f) – (WREG) – (C) dest
Status Affected: N,OV, C, DC, Z
Encoding: 0101 10da ffff ffff
Description: Subtract WREG and the carry flag
(borrow) from register 'f' (2’s comple-
ment method). If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the result
is stored back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value. If
’a’ is 1, then the bank will be selected
as per the BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example 1:SUBWFB REG, 1, 0
Before Instruction
REG = 0x19 (0001 1001)
WREG = 0x0D (0000 1101)
C=1
After Instruction
REG = 0x0C (0000 1011)
WREG = 0x0D (0000 1101)
C=1
Z=0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 0x1B (0001 1011)
WREG = 0x1A (0001 1010)
C=0
After Instruction
REG = 0x1B (0001 1011)
WREG = 0x00
C=1
Z = 1 ; result is zero
N=0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 0x03 (0000 0011)
WREG = 0x0E (0000 1101)
C=1
After Instruction
REG = 0xF5 (1111 0100)
; [2’s comp]
WREG = 0x0E (0000 1101)
C=0
Z=0
N = 1 ; result is negative
SWAPF Swap f
Syntax: [ label ] SWAPF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (f<3:0>) dest<7:4>,
(f<7:4>) dest<3:0>
Status Af fe cte d: None
Encoding: 0011 10da ffff ffff
Descr iption : The upper an d lower nibb les of reg-
ister 'f ' are exc hanged. If 'd' is 0, the
result is placed in WREG. If 'd' is 1,
the result is pl aced in regi ster 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR value (defaul t).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:SWAPF REG, 1, 0
Before Instruc tio n
REG = 0x53
After Instruction
REG = 0x35
1999-2013 Microchip Technology Inc. DS39026D-page 225
PIC18CXX2
TBLRD Table Read
Syntax: [ label ] TBLRD ( *; *+; *-; +*)
Operands: None
Operation: if TBLRD *,
(Prog Mem (TBLPTR)) TABLAT;
TBLPTR - No Change;
if TBLRD * +,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) +1 TBLPTR;
if TBLRD * -,
(Prog Mem (TBLPTR)) TABLAT;
(TBLPTR) -1 TBLPTR;
if TBLRD +*,
(TBLPTR) +1 TBLPTR;
(Prog Mem (TBLPTR)) TABLAT;
Status Affected: None
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the
content s of Program Memory (P.M.). To
address the prog ram memory, a
pointer called Table Pointer (TBLPTR)
is used.
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR h as a 2 Mbyte address rang e.
TBLPTR[0] = 0:Least Signi fican t
Byte of Program Memo ry Word
TBLPTR[0] = 1:Most Si gnificant
Byte of Program Memo ry Word
The TBLRD instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No
operation
(Read
Program
Memory)
No
operation No
operation
(Write
TABLAT)
TBLRD Table Read (cont’d)
Example 1:TBLRD *+ ;
Before Instruc tio n
TABLAT = 0x55
TBLPTR = 0x00A356
MEMORY(0x00A356) = 0x34
After Instruction
TABLAT = 0x34
TBLPTR = 0x00A357
Example 2:TBLRD +* ;
Before Instruc tio n
TABLAT = 0xAA
TBLPTR = 0x01A357
MEMORY(0x01A357) = 0x12
MEMORY(0x01A358) = 0x34
After Instruction
TABLAT = 0x34
TBLPTR = 0x01A358
PIC18CXX2
DS39026D-page 226 1999-2013 Microchip Technology Inc.
TBLWT Table Write
Syntax: [ label ] TBLWT ( *; *+; *-; +*)
Operands: None
Operation: if TBLWT*,
(TABLAT) Prog Mem (TBLPTR)
or Holding Register;
TBLPTR - No Change;
if TBLWT*+,
(TABLAT) Prog Mem (TBLPTR)
or Holding Register;
(TBLPTR) +1 TBLPTR;
if TBLWT*-,
(TABLAT) Prog Mem (TBLPTR)
or Holding Register;
(TBLPTR) -1 TBLPTR;
if TBLWT+*,
(TBLPTR) +1 TBLPTR;
(TABLAT) Prog Mem (TBLPTR)
or Holding Register;
Status Affected: None
Encoding: 0000 0000 0000 11nn
nn=0 *
=1 *+
=2 *-
=3 +*
Desc ription: This in struction is used to prog ram the
contents of Program Memory (P.M.).
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2 Mbyte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.
TBLPTR[0] = 0:Least Significant
Byte of Program Memory Word
TBLPTR[0] = 1:Most Significant
Byte of Program Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:
• no change
• post-increment
• post-decrement
• pre-increment
Words: 1
Cycles: 2 (many if long write is to on-chip
EPROM progra m memory)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No
operation No
operation No
operation
No
operation No
operation
(Read
TABLAT)
No
operation No
operation
(Write to Holding
Register or Memory)
TBLWT Table Write (Continued)
Example 1:TBLWT *+;
Before Instruc tio n
TABLAT = 0x55
TBLPTR = 0x00A356
MEMORY(0x00A356) = 0xFF
After Instructions (table write completion)
TABLAT = 0x55
TBLPTR = 0x00A357
MEMORY(0x00A356) = 0x55
Example 2:TBLWT +*;
Before Instruc tio n
TABLAT = 0x34
TBLPTR = 0x01389A
MEMORY(0x01389A) = 0xFF
MEMORY(0x01389B) = 0xFF
After Instruction (table write completion)
TABLAT = 0x34
TBLPTR = 0x01389B
MEMORY(0x01389A) = 0xFF
MEMORY(0x01389B) = 0x34
1999-2013 Microchip Technology Inc. DS39026D-page 227
PIC18CXX2
TSTFSZ Test f, skip if 0
Syntax: [ label ] TSTFSZ f [,a]
Operands: 0 f 255
a [0,1]
Operation: skip if f = 0
Status Affected: None
Encoding: 0110 011a ffff ffff
Description: If 'f' = 0, the next instruction,
fetched during the current instruc-
tion execution, is discarded and a
NOP is exec uted, m aking thi s a tw o-
cycle instruction. If ’a’ is 0, the
Access Ba nk w il l b e s el ected , ov er-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (def ault ).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data No
operation
If skip: Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation No
operation No
operation No
operation
No
operation No
operation No
operation No
operation
Example:HERE TSTFSZ CNT, 1
NZERO :
ZERO :
Before Instruction
PC = Address(HERE)
After Instruction
If CNT = 0x00,
PC = Address (ZERO)
If CNT 0x00,
PC = Address (NZERO)
XORLW Exclusive OR literal with WREG
Syntax: [ label ]XORLW k
Operands: 0 k 255
Operation: (WREG) .XOR. k WREG
Status Af fe cte d: N,Z
Encoding: 0000 1010 kkkk kkkk
Description: The contents of WREG are
XORed with the 8-bit literal 'k'.
The result is placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k' Process
Data Write to
WREG
Example:XORLW0xAF
Before Instruc tio n
WREG = 0xB5
After Instruction
WREG = 0x1A
PIC18CXX2
DS39026D-page 228 1999-2013 Microchip Technology Inc.
XORWF Exclusive OR WREG with f
Syntax: [ label ] XORWF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (WREG) .XOR. (f) dest
Status Affected: N,Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of
WREG with register 'f'. If 'd' is 0, the
result is stored in WREG. If 'd' is 1,
the resu lt is sto red back in the reg-
ister 'f' (default). If ‘a’ is 0, the
Access Bank will be selected, over-
riding th e BSR value. If ’ a’ is 1, then
the bank wi ll be se lected as p er the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f' Process
Data Write to
destination
Example:XORWF REG, 1, 0
Before Instruction
REG = 0xAF
WREG = 0xB5
After Instruction
REG = 0x1A
WREG = 0xB5
1999-2013 Microchip Technology Inc. DS39026D-page 229
PIC18CXX2
20.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
• Simulators
- MPLAB SIM Software Simulator
•Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD for PIC16F87X
• Device Progra mmers
-PRO MATE
® II Univer sa l D evi ce Pro grammer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demons trati on Boar d
- PICDEM 17 Demonstration Board
-K
EELOQ® Demonstration Board
20.1 MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• An interface to debugging tools
- simulator
- programmer (sold sep arately )
- emul ator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
• Customizable toolbar and key mapping
• A status bar
• On-line help
The MPLAB IDE allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (auto-
matically updates all project information)
• Debug us ing :
- source files
- absolute listing file
- machine code
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
20.2 MPASM Assembler
The MPASM assembler is a full-featured universal
macro assembl er for all P IC MCUs.
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be us ed through MPLAB ID E. The MP ASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
• Condit ion al as sem bl y for mult i-p urpo se sourc e
files.
• Directives that allow complete control over the
assembly pr ocess.
20.3 MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C1 7 and MP LAB C18 Code De vel op me nt
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microc ontrollers, re spectively. Thes e compile rs provide
powerful integration capabilities and ease of use not
found with other compilers.
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
PIC18CXX2
DS39026D-page 230 1999-2013 Microchip Technology Inc.
20.4 MPLINK Object Linker/
MPLIB Object Librari an
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine w ill be linked in with the ap plicatio n. This allo ws
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
• Allows all m emory areas to be defin ed as se ctio ns
to provide l ink -time flex ibi lity.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
20.5 MPLAB SIM Software Simulator
The MPL AB SIM sof tware sim ulator allow s code de vel-
opment in a PC-hosted environment by simulating the
PIC s eri es m icroc ont roll ers on a n in stru cti on level . On
any given instruction, the data areas can be examined
or modified and stimuli can be applied from a file, or
user-defined key press, to any of the pins. The execu-
tion can be performed in single step, execute until
break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MP ASM assembler . The soft ware simulator
offers the flexibility to develop and debug code outside of
the laborat ory envir onment, making it an excellent mu lti-
project software development tool.
20.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers (MCUs). Software control of the MPLAB ICE
in-circu it emulator is provided by the MPLAB Integrated
Developm en t Environment (ID E), w hich allows edi tin g,
building, downloading and source debugging from a
single environment.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
featur es. Interchangea ble processo r modules al low the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC micro co ntrol le rs.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
20.7 ICEPIC In-Circuit Emulator
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular sy stem can su pport d ifferen t subset s of PIC16 C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
applic atio n circ ui try bei ng pres en t.
1999-2013 Microchip Technology Inc. DS39026D-page 231
PIC18CXX2
20.8 MPLAB ICD In-Circuit Debugger
Microc hip's In-Circu it Debugger , M PLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC16F87X and can be used to
develo p for this and other PIC microcontrollers from the
PIC16CXXX family. The MPLAB ICD utilizes the in-cir-
cuit debugging capabi lity built into t he PIC16F87X. Thi s
feature, along with Microchip's In-Circuit Serial
ProgrammingTM protocol, offers cost-effective in-circuit
FLASH debugging from the graphical user interface of
the MPLAB Int egrated Development Environment. This
enables a des ign er to dev el op and debug so urc e cod e
by watching variables, single-stepping and setting
break points. Running at full speed enables testing
hardware in real-time.
20.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program PIC
devices. It can also set code protection in this mode.
20.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Inte grated D evelopm ent Envir onment software m akes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PIC devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76 X, may be suppor ted with an a dapter socket.
The PICSTART Plus development programmer is CE
compliant.
20.11 PICDEM 1 Low Cost PIC MCU
Demonstration Board
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microc hip’ s m icroc ontrol lers. T he mi croco ntrolle rs su p-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulato r and download th e firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
20.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with t he PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches , a poten tiomet er for simula ted anal og inpu t, a
serial EEPROM to d emonstra te usage o f the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
PIC18CXX2
DS39026D-page 232 1999-2013 Microchip Technology Inc.
20.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-p in PLCC micro controlle rs with an LCD Mo d-
ule. All the necessary hardware and software is
includ ed to r un the basic dem onstrat ion pro grams . The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II devi ce programmer , o r a PICSTART Plu s
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may a lso be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided t o the use r for ad ding hardwa re and con necting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commo ns and 1 2 segments, that is capable of displa y-
ing time, temperature and day of the week. The
PICDEM 3 d emons tration board pr ovi des an add itiona l
RS-232 interface and Windows software for showing
the demul tiplexed LC D signals on a PC. A si mple serial
interface allows the user to construct a hardware
demultiplexer f or the LCD signals.
20.14 PICDEM 17 Demonstration Board
The P ICDEM 17 de mo ns t r at i on boa r d is an ev al u at i on
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hard ware is inc luded to ru n basic d emo progra ms,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstratio n board supports download ing of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMAST ER emulat or and al l of the sample progr ams
can be run and modified using either emulator . Addition-
ally, a generous prototype area is available for user
hardware.
20.15 KEELOQ Evaluati on and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
1999-2013 Microchip Technology Inc. DS39026D-page 233
PIC18CXX2
TABLE 20-1: DEVELOPMENT TOOLS FROM MICROCHIP
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
PIC16C7XX
PIC16C8X
PIC16F8XX
PIC16C9XX
PIC17C4X
PIC17C7XX
PIC18CXX2
24CXX/
25CXX/
93CXX
HCSXXX
MCRFXXX
MCP2510
Soft war e Tools
MPLAB® Integrated
Development Environment
MPLAB® C17 C Compiler
MPLAB® C18 C Compiler
MPASMTM Assembler/
MPLINKTM Object Linker
Emulators
MPLAB® ICE In-Circuit Emulator
**
ICEPICTM In -Circu it Emu lat or
Debugger
MPLAB® ICD In-Circuit
Debugger **
Programmers
PICSTART® Plus Entr y Le vel
Development Programmer
**
PRO MATE® II
Universal Device Programmer
**
Demo Boards and Eval Kits
PICDEMTM 1 Demonstration
Board
†
PICDEMTM 2 Demonstration
Board ††
PICDEMTM 3 Demonstration
Board
PICDEMTM 14A Demonstration
Board
PICDEMTM 17 Demonstration
Board
KEELOQ® Evaluation Kit
KEELOQ® Transponder Kit
microIDTM Programmer’s Kit
125 kHz microIDTM
Developer’s Kit
125 kHz Anticollision microIDTM
Developer’s Kit
13.56 MHz Antico llision
microIDTM Developer’s Kit
MCP2510 CAN Developer’s Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
†Development tool is available on select devices.
PIC18CXX2
DS39026D-page 234 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 235
PIC18CXX2
21.0 ELECTRICAL CHARACTERIST ICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature.............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) .......................................-0.3 V to (VDD + 0.3 V)
Volta ge on VDD with respect to VSS ....................................................................................................... -0.3 V to +7.5 V
Volta ge on MCLR with respect to VSS (Note 2)....................................................................................... 0 V to +13.25 V
Voltage on RA4 with respect to Vss.............................................................................................................0 V to +8.5 V
Total power di ssipation (Note 1) ..............................................................................................................................1.0 W
Maximum current out of VSS pin...........................................................................................................................300 mA
Maximum current into VDD pin..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA
Output clamp current, I OK (VO < 0 or VO > VDD) 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin....................................................................................................25 mA
Maximum current sunk byPORTA, PORTB, and PORTE (Note 3) (combined)...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined)....... ..... ............................................. ...... ...200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA
Note 1: Power diss ipation is calcula ted as follows :
Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
2: V o ltage sp ikes below VSS at the MCLR/VPP pin, in ducin g curre nts grea ter than 80 m A, ma y cause latc h-up.
Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR/VPP pin, rath er
than pulling this pin directly to VSS.
3: PORTD and PORTE not available on the PIC18C2X2 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
PIC18CXX2
DS39026D-page 236 1999-2013 Microchip Technology Inc.
FIGURE 21-1: PIC18CXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED)
FIGURE 21-2: PIC18LCXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
40 MHz
5.0 V
3.5 V
3.0 V
2.5 V
PIC18CXXX
4.2V
Frequency
Voltage
6.0 V
5.5 V
4.5 V
4.0 V
2.0 V
40 MHz
5.0 V
3.5 V
3.0 V
2.5 V
PIC18LCXXX
FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.5 V) + 6 MHz
Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
6 MHz
4.2V
1999-2013 Microchip Technology Inc. DS39026D-page 237
PIC18CXX2
21.1 DC Charact eristics
PIC18LCXX2
(Industrial) Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
PIC18CXX2
(Industrial, Extended)
Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
VDD Supply Voltage
D001 PIC18LCXX2 2.5 — 5.5 V HS, XT, RC and LP osc mode
D001 PIC18CXX2 4.2 —5.5 V
D002 VDR RAM Data Retention
Voltage(1) 1.5 — — V
D003 VPOR VDD Start Voltage
to ensure internal
Power-on Reset signal
— — 0.7 V See section on Power-on Reset for details
D004 SVDD VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05 — — V/ms See section on Power-on Reset for detai ls
VBOR Brown-out Reset Voltage
D005 PIC18LCXX2
BORV1:BORV0 = 11 2.5 — 2.66 V
BORV1:BORV0 = 10 2.7 — 2.86 V
BORV1:BORV0 = 01 4.2 — 4.46 V
BORV1:BORV0 = 00 4.5 — 4.78 V
D005 PIC18CXX2
BORV1:BORV0 = 1x N.A. —N.A. VN ot in operating voltage range of device
BORV1:BORV0 = 01 4.2 —4.46 V
BORV1:BORV0 = 00 4.5 —4.78 V
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the lim it to whic h VDD can be lowere d in SLEEP mode , or during a device RESET, withou t losing RAM
data.
2: The supply cu rren t is mainl y a fu nc tion of the op era ting vo ltage and frequenc y. Othe r fac tors , su ch as I/O p in
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabl ed/di sabled as specified.
3: The powe r-down c urrent i n SLEEP mo de doe s not dep end on the os cillato r ty pe. Power-d own current is mea-
sured with the p art in SLEEP mode, wit h all I/O pins in hi-im pedan ce stat e and tied to VDD or VSS, and all fea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
PIC18CXX2
DS39026D-page 238 1999-2013 Microchip Technology Inc.
IDD Supply Current(2,4)
D010 PIC18LCXX2 — — 2 mA XT, RC, RCIO osc configurations
FOSC = 4 MHz, VDD = 2.5V
D010 PIC18CXX2 — — 4 mA XT, RC, RCIO osc configurations
FOSC = 4 MHz, VDD = 4.2V
D010A PIC18LCXX2 — — 55 A LP osc configuration
FOSC = 32 kHz, VDD = 2.5V
D010A PIC18CXX2 — — 250 ALP osc configuration
FOSC = 32 kHz, VDD = 4.2V
D010C PIC18LCXX2 — — 38 mA EC, ECIO osc configurations
FOSC = 40 MHz, VDD = 5.5V
D010C PIC18CXX2 — — 38 mA EC, ECIO osc configurations
FOSC = 40 MHz, VDD = 5.5V
D013 PIC18LCXX2 —
—
—
—
—
—
3.5
25
38
mA
mA
mA
HS osc configuration
FOSC = 6 MHz, VDD = 2.5V
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
FOSC = 10 MHz, VDD = 5.5V
D013 PIC18CXX2 —
—
—
—
25
38
mA
mA
HS osc configuration
FOSC = 25 MHz, VDD = 5.5V
HS + PLL osc configurations
FOSC = 10 MHz, VDD = 5.5V
D014 PIC18LCXX2 ——55ATimer1 osc configuration
FOSC = 32 kHz, VDD = 2.5V
D014 PIC18CXX2 —
——
—200
250 A
A
OSCB osc configuration
FOSC = 32 kHz, VDD = 4.2V, -40C to +85C
FOSC = 32 kHz, VDD = 4.2V, -40C to +125C
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the lim it to whic h VDD can be lowere d in SLEEP mode , or during a device RESET, withou t losing RAM
data.
2: The supply cu rren t is mainl y a fu nc tion of the op era ting vo ltage and frequenc y. Othe r fac tors , su ch as I/O p in
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabl ed/di sabled as specified.
3: The power-do wn curren t in SL EEP mode does not depend on the osc illato r type. Power-down current is mea-
sured with the p art in SLEEP mode, wit h all I/O pins in hi-im pedan ce stat e and tied to VDD or VSS, and all fea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
21.1 DC Characteristics (Continued)
PIC18LCXX2
(Industrial) Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
PIC18CXX2
(Industrial, Extended)
Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
1999-2013 Microchip Technology Inc. DS39026D-page 239
PIC18CXX2
IPD Power-down Current(3)
D020 PIC18LCXX2 —
—<.5
—2
4A
AVDD = 2.5V, -40C to +85C
VDD = 5.5V, -40C to +85C
D020
D021B
PIC18CXX2 —
—
—
—
<1
—
—
—
3
4
15
20
A
A
A
A
VDD = 4.2V, -40C to +85C
VDD = 5.5V, -40C to +85C
VDD = 4.2V, -40C to +125C
VDD = 5.5V, -40C to +125C
Module Differen tial Current
D022 IWDT Watchdog Timer
PIC18LCXX2 —
——
—1
15 A
AVDD = 2.5V
VDD = 5.5V
D022 Watchdog Timer
PIC18CXX2 —
——
—15
20 A
AVDD = 5.5V, -40C to +85C
VDD = 5.5V, -40C to +125C
D022A IBOR Brow n-out Reset
PIC18LCXX2 ——45AVDD = 2.5V
D022A Brown-out Reset
PIC18CXX2 —
——
—50
50 A
AVDD = 5.5V, -40C to +85C
VDD = 5.5V, -40C to +125
D022B ILVD Low Voltage Detect
PIC18LCXX2 ——45AVDD = 2.5V
D022B Low Voltage Detect
PIC18CXX2 —
——
—50
50 A
AVDD = 4.2V, -40C to +85C
VDD = 4.2V, -40C to +125C
D025 IOSCB Timer1 Oscillator
PIC18LCXX2 ——15AVDD = 2.5V
D025 Timer1 Oscillator
PIC18CXX2 —
——
—100
120 A
AVDD = 4.2V, -40C to +85C
VDD = 4.2V, -40C to +125C
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the lim it to whic h VDD can be lowere d in SLEEP mode , or during a devi ce RESET, without losing RAM
data.
2: The supply cu rren t is mainl y a fu nc tion of the op era ting vo ltage and frequenc y. Othe r fac tors , su ch as I/O p in
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD
MCLR = VDD; WDT enabl ed/di sabled as specified.
3: The powe r-down c urrent i n SLEEP mo de doe s not dep end on the os cillato r ty pe. Power-d own current is mea-
sured with the p art in SLEEP mode, wit h all I/O pins in hi-im pedan ce stat e and tied to VDD or VSS, and all fea-
tures that add delta current disabled (such as WDT, Timer1 Oscillator, BOR,...).
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formul a Ir = VDD/2REXT (mA) with REXT in kOhm.
21.1 DC Characteristics (Continued)
PIC18LCXX2
(Industrial) Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
PIC18CXX2
(Industrial, Extended)
Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Typ Max Units Conditions
PIC18CXX2
DS39026D-page 240 1999-2013 Microchip Technology Inc.
21.2 DC Characteristics: PIC18CXX2 (Industrial, Extended)
PIC18LCXX2 (Industrial)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
VIL Input Low Voltage
I/O ports:
D030 with TTL buffer Vss 0.15VDD VVDD < 4.5V
D030A — 0.8 V 4.5V VDD 5.5V
D031 with Schmitt Trigger buffer
RC3 and RC4 Vss
Vss 0.2VDD
0.3VDD V
V
D032 MCLR VSS 0.2VDD V
D032A OSC1 (in XT, HS and LP modes)
and T1OSI VSS 0.3VDD V
D033 OSC1 (in RC and EC mode)(1) VSS 0.2VDD V
VIH Input High Voltage
I/O ports:
D040 with TTL buffer 0.25VDD +
0.8V VDD VVDD < 4.5V
D040A 2.0 VDD V4.5V VDD 5.5V
D041 with Schmitt Trigger buffer
RC3 and RC4 0.8VDD
0.7VDD VDD
VDD V
V
D042 MCLR, OSC1 (EC mode) 0.8VDD VDD V
D042A OSC1 (in XT, HS and LP modes)
and T1OSI 0.7VDD VDD V
D043 OSC1 (RC mode)(1) 0.9VDD VDD V
IIL Input Leakage Current(2,3)
D060 I/O ports — 1AVSS VPIN VDD,
Pin at hi-impedance
D061 MCLR —5AVss VPIN VDD
D063 OSC1 — 5AVss VPIN VDD
IPU Weak Pull-up Current
D070 IPURB PORTB weak pull-up current 50 400 AVDD = 5V, VPIN = VSS
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC MCU be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
1999-2013 Microchip Technology Inc. DS39026D-page 241
PIC18CXX2
VOL Output Low Voltage
D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V,
-40C to +85C
D080A — 0.6 V IOL = 7.0 mA, VDD = 4.5V,
-40C to +125C
D083 OSC2/CLKOUT
(RC mode) —0.6VI
OL = 1.6 mA, VDD = 4.5V,
-40C to +85C
D083A — 0.6 V IOL = 1.2 mA, VDD = 4.5V,
-40C to +125C
VOH Output High Voltage(3)
D090 I/O ports VDD - 0.7 — V IOH = -3.0 mA, VDD = 4.5V,
-40C to +85C
D090A VDD - 0.7 — V IOH = -2.5 mA, VDD = 4.5V,
-40C to +125C
D092 OSC2/CLKOUT
(RC mode) VDD - 0.7 — V IOH = -1.3 mA, VDD = 4.5V,
-40C to +85C
D092A VDD - 0.7 — V IOH = -1.0 mA, VDD = 4.5V,
-40C to +125C
D150 VOD Open Drain High Voltage — 8.5 V RA4 pin
Capacitive Loading Specs
on Output Pins
D101 CIO All I/O pins and OSC2
(in RC mode) — 50 pF To meet the AC Timing
Specifications
D102 CBSCL, SDA — 400 pF In I2C mode
21.2 DC Characteristics: PIC18CXX2 (Industrial, Extended)
PIC18LCXX2 (Industrial) (Continued)
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC MCU be driven with an external clock while in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
PIC18CXX2
DS39026D-page 242 1999-2013 Microchip Technology Inc.
FIGURE 21-3: LOW VOLTAGE DETECT CHARACTERISTICS
TABLE 21-1: LOW VOLTAGE DETECT CHARACTERISTICS
VLVD
LVDIF
VDD
(LVDIF set by hardware)
(LVDIF can be
cleared in software)
S tandard Operating Conditions (unless otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No. Symbol Characteristic Min Max Units Conditions
D420 VLVD LVD Voltage LVV<3:0> = 0100 2.5 2.66 V
LVV<3:0> = 0101 2.7 2.86 V
LVV<3:0> = 0110 2.8 2.98 V
LVV<3:0> = 0111 3.0 3.2 V
LVV<3:0> = 1000 3.3 3.52 V
LVV<3:0> = 1001 3.5 3.72 V
LVV<3:0> = 1010 3.6 3.84 V
LVV<3:0> = 1011 3.8 4.04 V
LVV<3:0> = 1100 4.0 4.26 V
LVV<3:0> = 1101 4.2 4.46 V
LVV<3:0> = 1110 4.5 4.78 V
1999-2013 Microchip Technology Inc. DS39026D-page 243
PIC18CXX2
TABLE 21-2: EPROM PROGRAMMING REQUIREMENTS
DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +40°C
Param.
No. Sym Characteristic Min Max Units Conditions
Internal Program Memory
Programming Specs (Note 1)
D110 VPP Voltage on MCLR/VPP pin 12.75 13.25 V (Note 2)
D111 VDDP Suppl y vol t ag e during
programming 4.75 5.25 V
D112 IPP Current into MCLR/VPP pin — 50 mA
D113 IDDP Supply current during
programming —30mA
D114 TPROG Programming pulse width 50 1000 s Terminated via internal/external
interrupt or a RESET
D115 TERASE EPROM erase time
Device operation 3V
Device operation 3V 60
30 —
—min.
min.
Note 1: These specifications are for the programming of the on-chip program memory EPROM through the use of
the table wri te ins truc ti ons . The com ple te prog ram mi ng sp eci fic ati on s can be foun d in the
PIC18CXXX Programming Specifications (Literature Number DS39028).
2: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended.
PIC18CXX2
DS39026D-page 244 1999-2013 Microchip Technology Inc.
21.3 AC (Timing) Characteristics
21.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created
following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
TF Frequency T Time
Lowercase letters (pp) and their meanings:
pp cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
SF Fall P Period
HHigh RRise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC HD Hold SU Setup
ST DAT DATA input hold STO STOP condition
STA START condition
1999-2013 Microchip Technology Inc. DS39026D-page 245
PIC18CXX2
21.3.2 TIMING CONDITIONS
The temperature and voltages specified in Table 21-3
apply to all timing specifications unless otherwise
noted. Figure 21-4 specifies the load conditions for the
timing specification s.
TABLE 21-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
FIGURE 21-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions (unle ss otherw is e stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Operating volta ge VDD range as described in D C spec Section 21.1.
LC parts operate for industrial temperatures only.
VDD/2
CL
RL
Pin
Pin
VSS
VSS
CL
RL=464
CL= 50 pF for all pins except OSC2/CLKOUT
and including D and E outputs as ports
Load condition 1 Load condition 2
PIC18CXX2
DS39026D-page 246 1999-2013 Microchip Technology Inc.
21.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 21-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
TABLE 21-4: EXTERNAL CLOCK TIMING REQUIREMENTS
OSC1
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
1
23344
Param. No. Symbol Characteristic Min Max Units Conditions
1A FOSC External CLKIN
Frequency(1) DC 4 MHz XT osc
DC 25 MHz HS osc
4 10 MHz HS + PLL osc
DC
DC 40
40 kHz
MHz LP osc
EC, ECIO
Oscillator Frequency(1) DC 4 MHz RC osc
0.1 4 MHz XT osc
4 2 5 MHz HS osc
4 10 MHz HS + PLL osc
5 200 kHz LP osc mode
1T
OSC External CLKIN Period(1) 250 — ns XT and RC osc
40 — ns HS osc
100 250 ns HS + PLL osc
25
25 —
—s
ns LP osc
EC, ECIO
Oscillator Period(1) 250 — ns RC osc
250 10,000 ns XT osc
25
100 250
250 ns
ns HS osc
HS + PLL osc
25 — sLP osc
2T
CY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC
3 TosL,
TosH Ex tern al C lock in (OSC 1 )
High or Low Time 30 — ns XT osc
2.5 — sLP osc
10 — ns HS osc
4TosR,
TosF Ex tern al C lock in (OSC 1 )
Rise or Fall Time — 20 ns XT osc
— 50 ns LP osc
— 7.5 ns HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result
in an uns table oscill ato r o peration and /or hi ghe r than expected cu rrent c ons um pt ion . All devic es a r e tes ted
to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock
input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
1999-2013 Microchip Technology Inc. DS39026D-page 247
PIC18CXX2
TABLE 21-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
FIGURE 21-6: CLKOUT AND I/O TIMING
TABLE 21-6: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
TRC PLL Start-up Time (Lock Time) — 2 ms
CLK CLKOUT Stability (Jitter) using PLL -2 +2 %
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
10 TosH2ckL OSC1 to CLKOUT — 75 200 ns (1)
11 TosH2ckH OSC1 to CLKOUT — 75 200 ns (1)
12 TckR CLKOUT rise time — 35 100 ns (1)
13 TckF CLKOUT fall time — 35 100 ns (1)
14 Tc kL2ioV CLKOUT to Port out valid — — 0.5TCY + 20 ns (1)
15 TioV2ckH Port in valid before CLKOUT 0.25TCY + 25 — — ns (1)
16 TckH2ioI Port in hold after CLKOUT 0——ns(1)
17 TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns
18 TosH2ioI OSC1 (Q2 cycle) to
Port input invalid
(I/O in hold time)
PIC18CXXX 100 — — ns
18A PIC18LCXXX 200 — — ns
19 TioV2osH Port input valid to OSC1
(I/O in setup tim e) 0——ns
20 TioR Port output rise time PIC 18CXXX — 12 25 ns
20A PIC18LCXXX — — 50 ns
21 TioF Port output fall time PIC18CXXX — 12 25 ns
21A PIC18LCXXX — — 50 ns
22†† TINP INT pin high or low time TCY ——ns
23†† TRBP RB7:RB4 change INT high or low time TCY ——ns
24†† TRCP RC7:RC4 change INT high or low time 20 ns
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
Note: Refer to Figure 21-4 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4 Q1 Q2 Q3
10
13 14
17
20, 21
19 18
15
11
12
16
old value new value
PIC18CXX2
DS39026D-page 248 1999-2013 Microchip Technology Inc.
FIGURE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
FIGURE 21-8: BROWN-OUT RESET TIMING
TABLE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No. Symbol Characteristic Min Typ Max Units Conditions
30 TmcL MCLR Pulse Width (low) 2 — — s
31 TWDT Watchdog Timer Time-out Period
(No Postscaler) 71833ms
32 TOST Oscillation Start-up Timer Period 1024TOSC — 1024TOSC —TOSC = OSC1 period
33 TPWRT Power up Timer Period 28 72 132 ms
34 TIOZ I/O Hi-impedance from MCLR
Low or Watchdog Timer Reset —2—s
35 TBOR Brown-out Reset Pulse Width 200 — — sVDD BVDD (See D005)
36 Tivrst Time for Internal Reference
Voltage to become stable —2050 s
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O Pins
34
Note: Refer to Figure 21-4 for load conditions.
VDD BVDD
35 VBGAP = 1.2V
VIRVST
Enable Internal Reference Voltage
Internal Reference Voltage Stable 36
1999-2013 Microchip Technology Inc. DS39026D-page 249
PIC18CXX2
FIGURE 21-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 21-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Note: Refer to Figure 21-4 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T1CKI
TMR0 o r
TMR1
Param
No. Symbol Characteristic Min Max Units Conditions
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — ns
With Prescaler 10 — ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — ns
With Prescaler 10 — ns
42 Tt0P T0CK I Period No Prescaler TCY + 10 — ns
With Prescaler Greater of:
20 nS or TCY + 40
N
—nsN = prescale
value
(1, 2, 4,..., 256)
45 Tt1H T1CKI
High
Time
Synchronous, no prescaler 0.5TCY + 20 — ns
Synchronous,
with prescaler PIC18CXXX 10 — ns
PIC18LCXXX 25 — ns
Asynchronous PIC18CXXX 30 — ns
PIC18LCXXX 40 — ns
46 Tt1L T1CKI
Low
Time
Synchronous, no prescaler 0.5TCY + 20 — ns
Synchronous,
with prescaler PIC18CXXX 15 — ns
PIC18LCXXX 30 — ns
Asynchronous PIC18CXXX 30 — ns
PIC18LCXXX 40 — ns
47 Tt1P T1CKI
input
period
Synchronous Greater of:
20 nS or TCY + 40
N
—nsN = prescale
value
(1, 2, 4, 8)
Asynchronous 60 — ns
Ft1 T1CKI oscillator input frequency range DC 50 kHz
48 Tcke2tmrI Delay from external T1CKI clock edge to
timer increm en t 2TOSC 7TOSC —
PIC18CXX2
DS39026D-page 250 1999-2013 Microchip Technology Inc.
FIGURE 21-10: CAP TURE/ COMPARE/PWM TIMINGS (CCP1 AND CCP2)
TABLE 21-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Note: Refer to Figure 21-4 for load conditions.
CCPx
(Capture Mode)
50 51
52
CCPx
53 54
(Compare or PWM Mode)
Param.
No. Symbol Characteristic Min Max Units Conditions
50 TccL CCPx input low
time No Prescaler 0.5TCY + 20 — ns
With
Prescaler PIC18CXXX 10 — ns
PIC18LCXXX 20 — ns
51 TccH CCPx input
high time No Prescaler 0.5TCY + 20 — ns
With
Prescaler PIC18CXXX 10 — ns
PIC18LCXXX 20 — ns
52 TccP CCPx input period 3TCY + 40
N— ns N = prescale
value (1,4 or 16)
53 TccR CCPx output fall time PIC18CXXX — 25 ns
PIC18LCXXX — 50 ns
54 TccF CCPx output fall time PIC18CXXX — 25 ns
PIC18LCXXX — 50 ns
1999-2013 Microchip Technology Inc. DS39026D-page 251
PIC18CXX2
FIGURE 21-11: PARALLEL SLAVE PORT TIMING (PIC18C4X2)
TABLE 21-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C4X2)
Note: Refer to Figure 21-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65
Param.
No. Symbol Characteristic Min Max Units Conditions
62 TdtV2wrH Data in valid before WR or CS
(setup time) 20
25 —
—ns
ns Extended Temp. Range
63 TwrH2dtI WR or CS to data–in invalid
(hold time) PIC18CXXX 20 — ns
PIC18LCXXX 35 — ns
64 TrdL2dtV RD and CS to data–out valid —
—80
90 ns
ns Extended Temp. Range
65 TrdH2dtI RD or CS to data–o ut invalid 10 30 ns
66 TibfINH Inhibit of the IBF flag bit being cl eared from
WR or CS—3T
CY
PIC18CXX2
DS39026D-page 252 1999-2013 Microchip Technology Inc.
FIGURE 21-12 : EXAMP LE SP I MAST ER MODE TIMING (CKE = 0)
TABLE 21-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76
78
79
80
79
78
MSb LSb
BIT6 - - - - - -1
MSb IN LSb IN
BIT6 - - - -1
Note: Refer to Figure 21-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK inp ut TCY —ns
71 TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 Ts cL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 — ns
73A TB2BLast clock edge of Byte1 to the 1st clock edge
of Byte2 1.5TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — ns
75 TdoR SDO data output rise time PIC18CXXX — 25 ns
PIC18LCXXX — 45 ns
76 TdoF SDO dat a outp ut fall time — 25 ns
78 TscR SCK output rise time
(Master mo de) PIC18CXXX — 25 ns
PIC18LCXXX — 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO dat a outp ut val id afte r
SCK edge PIC18CXXX — 50 ns
PIC18LCXXX — 100 ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
1999-2013 Microchip Technology Inc. DS39026D-page 253
PIC18CXX2
FIGURE 21-13 : EXAMP LE SP I MAST ER MODE TIMING (CKE = 1)
TABLE 21-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 21-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
71 TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 Ts cL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Setup time of SDI data input to SCK edge 100 — ns
73A TB2BLast clock edge of Byte1 to the 1st clock edge
of Byte2 1.5TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — ns
75 TdoR SDO data output rise time PIC18CXXX — 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO dat a outp ut fall time — 25 ns
78 TscR SCK output rise time
(Master mo de) PIC18CXXX — 25 ns
PIC18LCXXX 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO dat a outp ut val id afte r
SCK edge PIC18CXXX — 50 ns
PIC18LCXXX 100 ns
81 TdoV2scH,
TdoV2scL SDO data output setup to SCK edge TCY —ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
PIC18CXX2
DS39026D-page 254 1999-2013 Microchip Technology Inc.
FIGURE 21-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
TABLE 21-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
73 74
75, 76 77
78
79
80
79
78
SDI
MSb LSb
BIT6 - - - - - -1
MSb IN BIT6 - - - -1 LSb IN
83
Note: Refer to Figure 21-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK input TCY —ns
71 TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL Se tup time of S DI data input to SCK edg e 100 — ns
73A TB2BLast clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 — ns
75 TdoR SDO data output rise time PIC18CXXX — 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO data output fall time — 25 ns
77 TssH2doZ SS to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time
(Master mode) PIC18CXXX — 25 ns
PIC18LCXXX 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after SCK
edge PIC18CXXX — 50 ns
PIC18LCXXX 100 ns
83 TscH2ssH,
TscL2ssH SS after SCK edge 1.5TCY + 40 — ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
1999-2013 Microchip Technology Inc. DS39026D-page 255
PIC18CXX2
FIGURE 21-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 21-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
70
71 72
82
SDI
74
75, 76
MSb BIT6 - - - - - -1 LSb
77
MSb IN BIT6 - - - -1 LSb IN
80
83
Note: Refer to Figure 21-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
70 TssL2scH,
TssL2scL SS to SCK or SCK input TCY —ns
71 TscH SCK input high time
(Slave mode) Continuous 1.25TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK input low time
(Slave mode) Continuous 1.25TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A TB2BLast clock edge of Byte1 to the first clock edge of Byte2 1.5TCY + 40 — ns (Note 2)
74 TscH2diL,
TscL2diL Hold time of SDI data input to SCK edge 100 —ns
75 TdoR SDO dat a outp ut ris e time PIC1 8CXXX — 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO dat a outp ut fall time — 25 ns
77 TssH2doZ SS to SDO output hi-impedance 10 50 ns
78 TscR SCK output rise time
(Master mo de) PIC18CXXX — 25 ns
PIC18LCXXX — 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV SDO data output valid after SCK
edge PIC18CXXX — 50 ns
PIC18LCXXX — 100 ns
82 TssL2doV SDO data output valid after SS
edge PIC18CXXX — 50 ns
PIC18LCXXX — 100 ns
83 TscH2ssH,
TscL2ssH SS after SCK edge 1.5TCY + 40 —ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.
PIC18CXX2
DS39026D-page 256 1999-2013 Microchip Technology Inc.
FIGURE 21-16 : I2C BUS START/STOP BITS TIMING
TABLE 21-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Note: Refer to Figure 21-4 for load conditions.
91
92
93
SCL
SDA
START
Condition STOP
Condition
90
Param.
No. Symbol Characteristic Min Max Units Conditions
90 Tsu:sta START condition 100 kHz mode 4700 — ns Only relevant for Repeated
START condition
Setup time 400 kHz mode 600 —
91 Thd:sta START condition 100 kHz mode 4000 — ns After this period the first
clock pul se is generated
Hold time 400 kHz mode 600 —
92 Tsu:sto STOP condition 100 kHz mode 4700 — ns
Setup time 400 kHz mode 600 —
93 Thd:sto STOP condition 100 kHz mode 4000 — ns
Hold time 400 kHz mode 600 —
1999-2013 Microchip Technology Inc. DS39026D-page 257
PIC18CXX2
FIGURE 21-17 : I2C BUS DATA TIMING
TABLE 21-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 4.0 — s P IC18 CXX X must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 — s PIC18CXXX must op erate at a
minimum of 10 MHz
SSP Module 1.5TCY —
101 TLOW Clock low time 100 kHz mode 4.7 — s P IC1 8CXX X must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 — s PIC18CXXX must op erate at a
minimum of 10 MHz
SSP Module 1.5TCY —
102 TRSDA and SCL rise
time 100 kHz mode — 1000 ns
400 kHz mode 20 + 0.1CB300 ns CB is specified to be from
10 to 400 pF
103 TFSDA and SCL fall time 100 kHz mode — 300 ns
400 kHz mode 20 + 0.1CB300 ns CB is specified to be from
10 to 400 pF
90 TSU:STA START condition
setup time 100 kHz mode 4.7 — s Only relevant for Repeated
START condition
400 kHz mode 0.6 — s
91 THD:STA START condition hold
time 100 kHz mode 4.0 — s After this period the first clock
pulse is generated
400 kHz mode 0.6 — s
106 THD:DAT Data input hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 s
107 TSU:DAT Dat a input setup time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
92 TSU:STO STOP condition setup
time 100 kHz mode 4.7 — s
400 kHz mode 0.6 — s
109 TAA Output valid from
clock 100 kHz mode — 3500 ns (Note 1)
400 kHz mode — — ns
110 TBUF Bus free time 100 kHz mode 4.7 — s T ime the bus must be free before
a new transmission can st art
400 kHz mode 1.3 — s
D102 CBBus capacitive loading — 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement TSU:DAT 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is
released.
Note: Refer to Figure 21-4 for load conditions.
90
91 92
100
101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC18CXX2
DS39026D-page 258 1999-2013 Microchip Technology Inc.
FIGURE 21-18: MAS TER SS P I2C BUS START/STOP BITS TIMING WAVEFORMS
TABLE 21-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Note: Refer to Figure 21-4 for load conditions.
91 93
SCL
SDA
START
Condition STOP
Condition
90 92
Param.
No. Symbol Characteristic Min Max Units Conditions
90 TSU:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for
Repeated START
condition
Setup tim e 4 00 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
91 THD:STA START condition 100 kHz mode 2(TOSC)(BRG + 1) — ns After this period the
first clock pulse is
generated
Hold time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
92 TSU:STO STOP condit ion 100 kHz mode 2(TOSC)(BRG + 1) — ns
Setup tim e 4 00 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
93 THD:STO STOP conditi on 100 kH z mo de 2(TOSC)(BRG + 1) — ns
Hold time 400 kHz mode 2(TOSC)(BRG + 1) —
1 MHz mode(1) 2(TOSC)(BRG + 1) —
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
1999-2013 Microchip Technology Inc. DS39026D-page 259
PIC18CXX2
FIGURE 21-19: MAS TER SS P I2C BUS DATA TIMING
TABLE 21-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param.
No. Symbol Characteristic Min Max Units Conditions
100 THIGH Clock high time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
101 TLOW Clock low time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
102 TRSDA and SCL
rise time 100 kHz mode — 1000 ns CB is specif ie d to be
from 10 to 400 pF 400 kHz mode 20 + 0.1CB300 ns
1 MHz mode(1) — 300 ns
103 TFSDA and SCL
fall time 100 kHz mode — 300 ns CB is speci fie d to be
from 10 to 400 pF 400 kHz mode 20 + 0.1CB 300 ns
1 MHz mode(1) — 100 ns
90 TSU:STA ST ART condition
setup time 100 kHz mode 2(TOSC)(BRG + 1) — ms Only relevant for
Repeated START
condition
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
91 THD:STA START condition
hold time 100 kHz mode 2(TOSC)(BRG + 1) — ms After this period the
first clock pulse is
generated
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
106 THD:DAT Data input
hold time 100 kHz mode 0 — ns
400 kHz mode 0 0.9 ms
1 MHz mode(1) TBD — ns
107 TSU:DAT Data input
setup time 100 kHz mode 250 — ns (Note 2)
400 kHz mode 100 — ns
1 MHz mode(1) TBD — ns
92 TSU:STO STOP condition
setup time 100 kHz mode 2(TOSC)(BRG + 1) — ms
400 kHz mode 2(TOSC)(BRG + 1) — ms
1 MHz mode(1) 2(TOSC)(BRG + 1) — ms
109 TAA Output valid from
clock 100 kHz mode — 3500 ns
400 kHz mode — 1000 ns
1 MHz mode(1) ——ns
110 TBUF Bus free time 100 kHz mode 4.7 — ms Time the bus must be
free before a new
transmission can start
400 kHz mode 1.3 — ms
1 MHz mode(1) TBD — ms
D102 CBBus capacitive loading — 400 pF
Note 1: Maximum pin capacitance = 10 pF for all I2C pins.
2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signa l. If such a dev ice does stretc h the LOW peri od of the SCL sign al, it must ou tput the next da ta bit to
the SDA line , parame ter #102 + parame ter #107 = 1000 + 250 = 1250 ns (for 10 0 kHz mode) before the SC L
line is released.
Note: Refer to Figure 21-4 for load conditions.
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
PIC18CXX2
DS39026D-page 260 1999-2013 Microchip Technology Inc.
FIGURE 21-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 21-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 21-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 21-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
121 121
120 122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 21-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid PIC18CXXX — 40 ns
PIC18LCXXX — 100 ns
121 Tckrf Clock out rise time and fall time
(Master mo de) PIC18CXXX — 25 ns
PIC18LCXXX — 50 ns
122 Tdtrf Data out rise time and fall time PIC18CXXX — 25 ns
PIC18LCXXX — 50 ns
125
126
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 21-4 for load conditions.
Param.
No. Symbol Characteristic Min Max Units Conditions
125 TdtV2ckl SYNC RCV (MASTER & SLAVE)
Data hold before CK (DT hold time) 10 — ns
126 TckL2dtl Data hold after CK (DT hold time) 15 — ns
1999-2013 Microchip Technology Inc. DS39026D-page 261
PIC18CXX2
TABLE 21-21: A/D CONVERTER CHARACTERISTICS: PIC18CXX2 (INDUSTRIAL, EXTENDED)
PIC18LCXX2 (INDUSTRIAL)
Param
No. Symbol Characteristic Min Typ Max Units Conditions
A01 NRResolution —
——
—10
10 bit
bit VREF = VDD 3.0V
VREF = VDD 3.0V
A03 EIL Integr al lin eari ty error —
——
—<±1
<±2 LSb
LSb VREF = VDD 3.0V
VREF = VDD 3.0V
A04 EDL Differential linearity error —
——
—<±1
<±2 LSb
LSb VREF = VDD 3.0V
VREF = VDD 3.0V
A05 EFS Full scale error —
——
—<±1
<±1 LSb
LSb VREF = VDD 3.0V
VREF = VDD 3.0V
A06 EOFF Offset error —
——
—<±1
<±1 LSb
LSb VREF = VDD 3.0V
VREF = VDD 3.0V
A10 — Monotonicity guaranteed(3) —VSS VAIN VREF
A20 VREF Reference voltage
(VREFH - VREFL)0V — — V
A20A 3V — — V For 10-bit resolution
A21 VREFH Reference voltage Hi gh AVSS —AVDD + 0.3V V
A22 VREFL Reference voltage Low AVSS -
0.3V —AVDD V
A25 VAIN Analog input voltage AVSS -
0.3V —VREF + 0.3V V
A30 ZAIN Recommended impedance of
analog voltage source ——10.0k
A40 IAD A/D conversion
current (VDD)PIC18CXXX — 180 — A Average current
consum pti on when
A/D is on (Note 1).
PIC18LCXXX — 90 — A
A50 IREF VREF input current (Note 2) 10
—
—
—
1000
10
A
A
During VAIN acquisition.
Based on differential of
VHOLD to VAIN. To charge
CHOLD, see Section 16.0.
During A/D conv ers ion
cycle.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is
se lected as reference input.
2: VSS VAIN VREF
3: The A/D con ve rsi on re sult neve r dec reas es w ith an i ncre as e in the I nput V ol t ag e, and has no mi ss ing co des .
PIC18CXX2
DS39026D-page 262 1999-2013 Microchip Technology Inc.
FIGURE 21-22: A/D CONVERSION TIMING
TABLE 21-22: A/D CONVERSION REQUIREMENTS
Param
No. Symbol Characteristic Min Max Units Conditions
130 TAD A/D clock period PIC18CXXX 1.6 20(5) sTOSC based, VREF 3.0V
PIC18LCXXX 3.0 20(5) sTOSC based, VREF full range
PIC18CXXX 2.0 6.0 s A/D RC mode
PIC18LCXXX 3.0 9.0 s A/D RC mode
131 TCNV Conversion time
(not including acquisition time) (Note 1) 11 12 TAD
132 TACQ Acquisition time (Note 3) 15
10 —
—s
s-40C Temp 125C
0C Temp 125C
135 TSWC Switching Time from convert sample — (Note 4)
136 TAMP Amplifier settli ng tim e (Note 2) 1—s This may be used if the
“new” input voltage has not
changed by more t han 1 LS b
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 16.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
after the co nvers ion (AVDD to A VSS, or AVSS to AVDD). The sourc e imp edanc e (RS) on the input chan nels is
50 .
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
Note 2
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . . . . .
TCY
1999-2013 Microchip Technology Inc. DS39026D-page 263
PIC18CXX2
22.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'min' represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 22-1: TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
FIGURE 22-2: MAXIMU M IDD vs. FOSC OVER VDD (HS MODE)
0
2
4
6
8
10
12
14
16
4 6 8 101214161820222426
FOSC (MH z)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.7V
3.2V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0
2
4
6
8
10
12
14
16
4 6 8 101214161820222426
FOSC (MH z )
IDD
(mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
3.2V
2.7V
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
PIC18CXX2
DS39026D-page 264 1999-2013 Microchip Technology Inc.
FIGURE 22-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
FIGURE 22-4: MAXIMU M IDD vs. FOSC OVER VDD (HS/PLL MODE)
0
5
10
15
20
25
45678910
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.5V
4.0V
3.5V
3.0V
2.5V
Typical: statistical mean @ 25°C
Maximu m: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0
5
10
15
20
25
45678910
FOSC (MHz)
IDD (mA)
5.0V
5.5V
4.5V
4.0V
3.5V
3.0V
2.5V
Typical: statistical mean @ 25°C
Maximu m: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
1999-2013 Microchip Technology Inc. DS39026D-page 265
PIC18CXX2
FIGURE 22-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
FIGURE 22-6: MAXIMU M IDD vs. FOSC OVER VDD (XT MODE)
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (MHz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-4 0° C to 125°C )
Minimum: mean – 3 (-40°C to 125°C)
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FOSC (M Hz)
IDD (mA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
PIC18CXX2
DS39026D-page 266 1999-2013 Microchip Technology Inc.
FIGURE 22-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE)
FIGURE 22-8: MAXIMU M IDD vs. FOSC OVER VDD (LP MODE)
0
20
40
60
80
100
120
140
160
180
200
20 30 40 50 60 70 80 90 100
FOSC (kHz)
IDD (uA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Mini mum: mean – 3 (-40°C to 125°C)
0
50
100
150
200
250
300
20 30 40 50 60 70 80 90 100
FOSC (kHz)
IDD (uA)
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
1999-2013 Microchip Technology Inc. DS39026D-page 267
PIC18CXX2
FIGURE 22-9: TYPICAL AND MAXIMUM IDD vs. VDD
(TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C = 47 pF)
FIGURE 22-10: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 20 pF, 25C)
0
50
100
150
200
250
300
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V )
IDD (uA)
M ax (-40C)
Typ (25C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.53.03.54.04.55.05.5
VDD (V)
Freq (MHz)
3.3k
5.1k
10k
100k
PIC18CXX2
DS39026D-page 268 1999-2013 Microchip Technology Inc.
FIGURE 22-11: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 100 pF, 25C)
FIGURE 22-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R
(RC MODE, C = 300 pF, 25C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
Freq (MHz)
3.3k
5.1k
10k
100k
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.53.03.54.04.55.05.5
VDD (V )
Freq (MHz)
3.3k
5.1k
10k
100k
1999-2013 Microchip Technology Inc. DS39026D-page 269
PIC18CXX2
FIGURE 22-13 : IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
FIGURE 22-14 : IBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.50V - 2.66V)
0.01
0.10
1.00
10.00
100.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V )
IPD (uA)
M ax (125C)
Max (85C)
Typ (25C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0
25
50
75
100
125
150
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
IBOR
(A)
MAX IBOR
(-40C to 125C)
Typ IBOR
(25C)
Indeterminate S t ate
(May be in RES E T or SLEE P
Device in SLEEP
Max imum RESET current - example only
(Depends on osc m ode , o sc freq, tem p , VDD)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Mini mum: mean – 3 (-40°C to 125°C)
PIC18CXX2
DS39026D-page 270 1999-2013 Microchip Technology Inc.
FIGURE 22-15: TYPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE
(-40C TO +125C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2 = 47 pF)
FIGURE 22-16: TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE
(WDT ENABLED)
0
10
20
30
40
50
60
70
80
90
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V )
ITMR1OSC (A)
Max (-40C to 125C)
Ty p (25C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V )
IWDT (A)
Maximum (-40C)
Ty pi cal (25C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
1999-2013 Microchip Technology Inc. DS39026D-page 271
PIC18CXX2
FIGURE 22-17: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)
FIGURE 22-18 : ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 3.0V - 3.2V)
0
10
20
30
40
50
60
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
WDT Period (m s)
Max (125C)
Mi n (-40C)
Typ (25C)
Typical: statistical mean @ 25°C
Maximu m: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0
5
10
15
20
25
30
35
40
45
50
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
ILVD (A)
Typ (25C)
Max ( -40C t o 125C)
Ty p (25C)
LV DIF is set
by hardware
LVDIF can
be c l eared
by fi rm w are
LVDIF i s
unknown
Max
(-40C to 125C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
PIC18CXX2
DS39026D-page 272 1999-2013 Microchip Technology Inc.
FIGURE 22-19 : ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5V - 4.78V)
FIGURE 22-20: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
0
5
10
15
20
25
30
35
40
45
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
ILVD (A)
Typ ( 25C )
Max (125C)
Ty p (25C)
LV DIF i s set
by hardware
LV DIF can
be c leared
by firmware
LV DIF i s
unknown
M ax (125C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 5 10 15 20 25
IOH (-mA )
VOH (V)
Max
(-40C)
Typ
(25C)
Min
(125C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
1999-2013 Microchip Technology Inc. DS39026D-page 273
PIC18CXX2
FIGURE 22-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
FIGURE 22-22: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0 5 10 15 20 25
IOH (-mA)
VOH (V)
Max (-40C)
Ty p (25C)
Mi n (125C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 5 10 15 20 25
IOL (mA)
VOL (V)
Max (-40C to 125C)
Typ (25 C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
PIC18CXX2
DS39026D-page 274 1999-2013 Microchip Technology Inc.
FIGURE 22-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125 C)
FIGURE 22-24: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
0 5 10 15 20 25
IOL (m A)
VOL (V)
M ax (-40C to 125C)
Typ (25C)
Typical: statistical mean @ 25°C
Maximu m: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V )
VIN (V)
VIH Max (125C)
VIH M i n (-40C)
VIL Max (-40C)
VIL Mi n (125C)
Typical: statistical mean @ 25°C
Maximum: mean + 3 (-4 0° C to 125°C )
Minimum: mean – 3 (-40°C to 125°C)
1999-2013 Microchip Technology Inc. DS39026D-page 275
PIC18CXX2
FIGURE 22-25: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO +125C)
FIGURE 22-26: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V )
VIN (V)
Max V TH (-40C)
Min VTH (125C)
Typical: statistical mean @ 25°C
Maxi mum: mean + 3 (-40°C to 125°C)
Minimum: mean – 3 (-40°C to 125°C)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V )
VIN (V)
Max VIH (125C) Min V IH (-40C)
Min VIL (-40C) Max VIL (125C)
Typ ical: statistical mean @ 25°C
Maximum: mean + 3 (-4 0°C to 125°C )
Minimum: mean – 3 (-40°C to 125°C)
PIC18CXX2
DS39026D-page 276 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 277
PIC18CXX2
23.0 PACKAGING INFORMATION
23.1 Package Marking Information
28-Lead SO IC
YYWWNNN
Example
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead PDIP (Skinny DIP) Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
0117017
PIC18C242-I/SP
XXXXXXXXXXXXXXXXXXXX 0110017
PIC18C242-E/SO
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week o f Janu ary 1 i s week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip p art number c annot be marked on one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
PIC18CXX2
DS39026D-page 278 1999-2013 Microchip Technology Inc.
Package Marking Information (Cont’d)
44-Lead TQFP Example
44-Lead PLCC Example
XXXXXXXXXX
XXXXXXXXXX
28- and 40-Lead JW (CERDIP) Example
XXXXXXXXXXXXXXXXXX
40-Lead PDIP Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC18C442-I/P
0112017
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC18C452
-I/JW
0115017
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18C442
-E/PT
0120017
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC18C452
-I/L
0120017
1999-2013 Microchip Technology Inc. DS39026D-page 279
PIC18CXX2
23.2 Package Details
The following sections give the technical details of the
packages.
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
1510515105
Mold Draft Angle Bottom 1510515105
Mold Draft Angle Top 10.928.898.13.430.350.320eBOverall Row S pacing § 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008
c
Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Molded Packag e Thicknes s 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limit s MILLIMETERS
INCHES*Units
2
1
D
n
E1
c
eB
E
p
L
A2
B
B1
A
A1
Notes:
JEDEC Equivalent: MO-095
Drawing No. C04-070
* Controlling Parameter
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/p ackaging
PIC18CXX2
DS39026D-page 280 1999-2013 Microchip Technology Inc.
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Foot Angle Top 048048
1512015120
Mold Draft Angle Bottom 1512015120
Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050
p
Pitch 2828
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
L
c
45
h
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
1999-2013 Microchip Technology Inc. DS39026D-page 281
PIC18CXX2
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
1510515105
Mold Draft Angle Bottom 1510515105
Mold Draft Angle Top 17.2716.5115.75.680.650.620
eB
Overall Row S pacing § 0.560.460.36.022.018.014BLo wer Lea d Width 1.781.270.76.070.050.030B1U pp er Lea d Width 0.380.290.20.015.012.008
c
Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOvera ll Length 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54
.100
p
Pitch 4040
n
Number of P ins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
A2
1
2
D
n
E1
c
eB
E
p
L
B
B1
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC18CXX2
DS39026D-page 282 1999-2013 Microchip Technology Inc.
28-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
7.377.116.86.290.280.270WWindow Diameter 18.0316.7615.49.710.660.610eBOverall Row Spacing § 0.580.510.41.023.020.016BLower Lead Width 1.651.461.27.065.058.050B1Upper Lead Width 0.300.250.20.012.010.008
c
Lead Thickness 3.813.493.18.150.138.125LTip to Seating Plane 37.8537.0836.321.4901.4601.430DOverall Length 13.3613.2113.06.526.520.514
E1
Ceramic Pkg. Width 15.8815.2415.11.625.600.595ESho uld er to Sh ould er W idth 1.520.950.38.060.038.015A1Standoff 4.194.063.94.165.160.155A2Ceramic Package Height 5.725.334.95.225.210.195ATop to Seating Plane 2.54.100
p
Pitch 28
28
n
Numb er of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
E1
W
c
E
eB p
A2
L
B1
B
A1
A
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-103
Drawing No. C04-013
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
1999-2013 Microchip Technology Inc. DS39026D-page 283
PIC18CXX2
40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
9.148.898.64.360.350.340WWind ow Dia meter 18.0316.7615.49.710.660.610eBOverall Row S pacing § 0.580.510.41.023.020.016
B
Lower Lead Width 1.401.331.27.055.053.050B1Upper Lead Width 0.360.280.20.014.011.008
c
Lead Thickness 3.683.563.43.145.140.135LTip to Seating Plane 52.3252.0751.822.0602.0502.040DOverall Length 13.3613.2113.06.526.520.514
E1
Ceramic Pk g. Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 1.521.140.76.060.045.030A1Standoff 4.194.063.94.165.160.155A2Ceramic Package Height 5.725.214.70.225.205.185ATop to Seating Plane 2.54.100
p
Pitch 40
40
n
Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
c
eB
E
p
B1
B
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-103
Drawing No. C04-014
E1
W
A2 A
A1
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC18CXX2
DS39026D-page 284 1999-2013 Microchip Technology Inc.
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
* Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1.140.890.64.045.035.025CHPin 1 Corner Chamfer
1.00.039
(F)
Footprint (Reference)
(F)
A
A1 A2
E
E1
#leads=n1
p
B
D1 D
n
1
2
c
L
Units INCHES MILLIMETERS*
Dim ension Limits MIN NOM MAX MIN NOM MAX
Numb er of Pin s n44 44
Pitch p.031 0.80
Overall Height A .039 .043 .047 1.00 1.10 1.20
Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05
Standoff § A1 .002 .004 .006 0.05 0.10 0.15
Foot Length L .018 .024 .030 0.45 0.60 0.75
Foot A ngle 03.5 7 03.5 7
Overall Width E .463 .472 .482 11.75 12.00 12.25
Overall Length D .463 .472 .482 1 1.75 12.00 12.25
Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10
Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10
Pins per Side n1 11 11
Lead Thickness c.004 .006 .008 0.09 0.15 0.20
Lead Width B . 012 .015 .017 0.30 0. 38 0.44
Mold Draft Angle Top 51015 51015
Mold Draft Angle Bottom 51015 51015
CH x 45
§ Significant Characteristic
Note: For th e mo st c ur re nt pac ka ge d r awi n gs , p l ease se e t he M ic r oc hi p Pack a gi ng Specifi c ati on lo ca te d
at http://www.microchip.com/packaging
1999-2013 Microchip Technology Inc. DS39026D-page 285
PIC18CXX2
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
CH2 x 45CH1 x 45
10501050
Mold Draft Angle Bottom 10501050
Mold Draft Angle Top 0.530.510.33.021.020.013B0.810.740.66.032.029.026B1Upper Lead Width 0.330.270.20.013.011.008
c
Lead Thickness
1111n1Pins per Side
16.0015.7514.99.630.620.590D2Footprint Length 16.0015.7514.99.630.620.590E2Footprint Width 16.6616.5916.51.656.653.650D1Molded Package Length 16.6616.5916.51.656.653.650E1Molded Package Width 17.6517.5317.40.695.690.685DOverall Length 17.6517.5317.40.695.690.685EOverall Width 0.250.130.00.010.005.000
CH2Corner Chamfer (others) 1.271.141.02.050.045.040CH1Corner Chamfer 1 0.860.740.61.034.029.024A3Side 1 Chamfer Height 0.51.020A1Standoff § A2Molded Package Thickness 4.574.394.19.180.173.165AOverall Height
1.27.050
p
Pitch 4444
n
Number of Pins MAXNOMMINMAXNOMMINDime nsion Limits MILLIMETERSINCHES*Units
A2
c
E2
2
D
D1
n
#leads=n1
E
E1
1
p
A3
A
35
B1
B
D2
A1
.145 .153 .160 3.68 3.87 4.06
.028 .035 0.71 0.89
Lower Lead Width
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
§ Significant Characteristic
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
PIC18CXX2
DS39026D-page 286 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 287
PIC18CXX2
APPENDIX A: REVISION HISTORY
Revision A (July 1999)
Original data sheet for PIC18CXX2 family.
Revision B (March 2001)
Added DC and AC characteristics graphs
(Section 22.0).
Revision C (January 2013)
Added a note to each package outline drawing.
APPENDIX B: DEVICE
DIFFERENCES
The differences between the devices listed in this data
sheet are shown in Table 1.
TABLE 1: DEVICE DIFFERENCES
Feature PIC18C242 PIC18C252 PIC18C442 PIC18C452
Program Memory (Kbytes) 16 32 16 32
Data Me mo ry (Bytes) 512 1536 512 1536
A/D Channels 5 5 8 8
Parallel Slave Port (PSP) No No Yes Yes
Package Types 28-pin DIP
28-pin SOIC
28-pin JW
28-pin DIP
28-pin SOIC
28-pin JW
40-pin DI P
44-pin PLCC
44-pin TQFP
40-pin JW
40-pin DIP
44-pin PLCC
44-pin TQFP
40-pin JW
PIC18CXX2
DS39026D-page 288 1999-2013 Microchip Technology Inc.
APPENDIX C: CONVERSION
CONSIDERATIONS
This appendix discusses the considerations for con-
verting from previous versions of a device to the ones
listed in this data sheet. Typically, these changes are
due to the differences in the process technology used.
An example of this type of conversion is from a
PIC16C74A to a PIC16C74B.
Not Applicable
APPENDIX D: MIGRATION FROM
BASELINE TO
ENHANCED DEVICES
This section discusses how to migrate from a Basel ine
device (i.e., PIC16C5X) to an Enhanced MCU device
(i.e., PIC18CXXX).
The following are the list of modifications over the
PIC16C5X mic roc on trol ler fam il y:
Not Currently Av ail able
1999-2013 Microchip Technology Inc. DS39026D-page 289
PIC18CXX2
APPENDIX E: MIGRATION FROM
MID-RANGE TO
ENHANCED DE VICES
A detailed discussion of the differences between the
mid-range MCU devices (i.e., PIC16CXXX) and the
enhanced devices (i.e., PIC18CXXX) is provided in
AN716, “Migrating Designs from PIC16C74A/74B to
PIC18C442.” The changes discussed, while device
specific, are generally applicable to all mid-range to
enhanced device migrations.
This Ap plicatio n Note is availab le as L iterature Nu mber
DS00716.
APPENDIX F: MIGRATION FROM
HIGH-END TO
ENHANCED DEVICES
A detailed discussion of the migration pathway and dif-
ferences between the high-end MCU devices (i.e.,
PIC17CXXX) and the enhanced devices (i.e.,
PIC18CXXX) is provided in AN726, “PIC17CXXX to
PIC18CXXX Migration.” This Application Note is avail-
able as Literature Number DS00726.
PIC18CXX2
DS39026D-page 290 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 291
PIC18CXX2
INDEX
A
A/D ................................................................................... 165
A/D Converte r Fla g (A DIF Bit) ........ ...... ............. ......16 7
A/D Converter Interrup t, Configuring .......................168
ADCON0 Register ....................................................165
ADCON1 Register . ...........................................165, 166
ADRES Register . .............................................165, 167
Analog Port Pins ..................................................89, 90
Analog Port Pins, Configu r in g ................... ...............170
Associ a te d Re g i sters ...................... ....................... ..172
Block Diag ram .............. ....................... ............. ...... ..167
Block Diagram, Analog Input Model .........................168
Configuring the Module ............................................168
Conversion Clock (TAD) ........................................... 170
Conversion Status (GO/DONE Bit) ..... ........... ...... ....167
Conversions ............................................................. 171
Converter Characteristics ........................................261
Equations .................................................................169
Sampling Requirements .......................... .... ....... .. ....168
Sampli n g Time .................................. ............. ...... ....16 9
Special Event Trigger (CCP) ............................110, 171
Timing Dia g ram .............. ............. ...... .......................26 2
Absolute Maximum Ratings .............................................235
ACKSTAT ........................................................................139
ADCON0 Register ............................................................165
GO/DONE Bit ...........................................................167
ADCON1 Register ....................................................165, 166
ADDLW ............................................................................ 193
ADDWF ............................................................................193
ADDWFC .........................................................................194
ADRES Register ......................................................165, 167
Analog-to-Digital Converter. See A/D
ANDLW ............................................................................ 194
ANDWF ............................................................................195
Assembler
MPASM Assembler ..................................................229
B
Baud Rate Generator .......................................................136
BC .................................................................................... 195
BCF ..................................................................................196
BF ....................................................................................139
Block Diagrams
A/D Converte r ........ ...... ............. ...... ............ .............167
Analog Input Model ..................................................168
Baud Rate Generator ...............................................136
Capture Mode Operation ........................ .. ....... .. .... ..109
Compare Mode Operation ............................... .. .... ..110
Low Voltage Detect
Exter n al R e fe rence So u rce .............. .. .. ............174
Internal Reference Source ...............................174
MSSP
I2C Mode ..........................................................128
SPI Mode .........................................................121
On-Chip Rese t Circuit ...... ............. ............ ............. ....25
Parallel Slave Port (PORTD and PORTE) .................90
PORTA
RA3:RA0 and RA5 Port Pins .............................77
RA4/T0CKI Pin ................... ............ ....... ............78
RA6 Pin ..............................................................78
PORTB
RB3 Pi n .. ...... .. ............................. . ..................... 81
RB3:RB0 Port Pins ............................................ 81
RB7:RB4 Port Pins ............................................ 80
PORTC (Peripheral Output Override) ........................ 83
PORTD (I/O Mode) .................................................... 85
PORTE (I/O Mode) .................................................... 87
PWM Operation (Simplified) .................................... 112
SSP (SPI Mode) . .......... ..... ................... ........ ........... 121
Timer1 ....................................................................... 98
Timer1 (16-bit R/W Mode) ............................... .... ...... 98
Timer2 ..................................................................... 102
Timer3 ..................................................................... 104
Timer3 (16-bit R/W Mode) ................ ............. .... .... .. 104
USART
Asynchronous Receive .................................... 157
Asynchronous Tra nsmit ................................... 155
Watchdog Timer ........................... .... .. ......... .... .. .... .. 184
BN .................................................................................... 196
BNC ................................................................................. 197
BNOV .............................................................................. 198
BNZ ................................................................................. 198
BOR. See Brown-out Reset
BOV ................................................................................. 201
BRA ................................................................................. 199
BRG. See Baud Rate Generator
Brow n - o u t Reset (BO R ) .... ......................................... 26, 17 9
Timing Diagram ....................................................... 248
BSF ......................... .......... ......... ..................................... . 199
BTFSC ............................................................................. 200
BTFSS ............................................................................. 200
BTG ................................................................................. 201
Bus Collision During a Repeated START Condition ........ 147
Bus Collision During a START Condition ........................ 145
Bus Collision During a STOP Condition .......................... 148
BZ .................................................................................... 202
C
CALL ...... ........ ..... ........ ........ ..... ........ ........ ..... ........ ........ ... 202
Capture (CCP Module) ............................... ......... .... .... .... 109
Associated Registers ............................................... 111
Block Diagram ......................................................... 109
CCP Pin Configuration ............................................ 109
CCP R 1 H :C CPR1L R e g i st e r s .... .. ......................... ... 109
Softwar e In terrupt ............... ...... ...... ....................... .. 109
Timer1 Mode Selection . ........................................... 109
Capture/Compare/PWM (CCP) ............ ............. .............. 107
Capture Mode. See Capture
CCP1 ....................................................................... 108
CCPR1H Register ........ ................................... 108
CCPR1L Register ............................................ 108
CCP1CON and CCP2CON Registers ..................... 107
CCP2 ....................................................................... 108
CCPR2H Register ........ ................................... 108
CCPR2L Register ............................................ 108
Compare Mode. See Compare
Interaction of Two CCP Modules ............................. 108
PWM Mode. See PWM
Time r R e so u r ces ...... .. ..... .. .................. . ............ .. ..... 1 0 8
Timing Diagram ....................................................... 250
Cloc ki n g Scheme .... ...... .. ............................. . ..................... 39
CLRF ............................................................................... 203
CLRWDT ......................................................................... 203
PIC18CXX2
DS39026D-page 292 1999-2013 Microchip Technology Inc.
Code Examples
16 x 16 Signed Multiply Routine ................................62
16 x 16 Unsigned Multiply Routine ............................62
8 x 8 Signed Multiply Routine ..................... .... .. ....... ..61
8 x 8 Unsigned Multiply Routine ................................61
Changing Between Capture Prescalers ...................109
Fast Register Stack ....................................................39
Initializing PORTA ......................................................77
Initializing PORTB ......................................................80
Initializing PORTC ......................................................83
Initializing PORTD ......................................................85
Initializing PORTE ......................................................87
Loading the SSPBUF Register ................................122
Saving STATUS, WREG and BSR Registers
in RAM ....................... ...... ....................... ...........75
Code Protection .......................................................179, 186
COMF ...............................................................................204
Compare (CCP Module) ...................................................110
Associ a te d Re g i sters ..... ................ ........................ ..111
Block Diag ram .................. ............ ....... ............ ....... ..110
CCP Pin Configuration .............................................110
CCPR1H:CCPR1L Registers ...................................110
Softwa re In terrupt ..... ....... ............ ....... ............ ....... ..110
Special Event Trigger .........................99, 105, 110, 171
Timer1 Mode Selection ............................................110
Configuration Bits .............................................................179
Context Saving During Interrupts .......................................75
Example Code ...........................................................75
Conversi o n Co n side rations .......... ............. ............ ...........288
CPFSEQ ..........................................................................204
CPFSGT ...........................................................................205
CPFSLT ...........................................................................205
D
Data Memory ......................................................................42
General Purpose Registers ........................................42
Special Function Registers ........................................42
DAW .................................................................................206
DC Characteristics ...................................................237, 240
DECF ...............................................................................206
DECFSNZ ........................................................................207
DECFSZ ...........................................................................207
Device Differences ...........................................................287
Direct Add ressing ....................... ...... ....................... ...........51
E
Electrical Characteristics ..................................................235
Errata ...................................................................................5
F
Firmware Instructions .......................................................187
G
General Call Address Sequence . .....................................133
General Call Address Support .........................................133
GOTO ...............................................................................208
I
I/O Ports .................. ....... ...... ............................................ .. 77
I2C (SSP Module) ............................................................ 128
ACK Pulse ........... ............ ...... ....... ...... ............. 12 8 , 129
Addressing ............................................................... 129
Block Diag ram ................... ............. ............ ....... ......128
Read/Write Bit Information (R/W Bit) ....................... 129
Reception ................................................................ 129
Serial Clock (RC3/SCK/SCL) ................................... 129
Slave Mode ............................................. .... ........... .. 128
Timing Dia g ram, Data .......................................... .... 257
Timing Diagram, START/STOP Bits ........................ 256
Transmission ........................................................... 129
I2C Master Mode Reception ............................................ 139
I2C Master Mode Repeated START Condition ................ 138
I2C Module
Acknowledge Sequence Timing .............................. 142
Baud Rate Generator
Block Diagram
Baud Rate Generator ...................................... 136
BRG Reset Due to SDA Collision ............................ 146
BRG Timing ............................................................. 136
Bus Collision
Acknowledge ................................................... 144
Repeated START Condition .......................... .. 147
Repeated START Condition Timing
(Case 1) ................................................... 147
Repeated START Condition Timing
(Case 2) ................................................... 147
START Condition ............................................. 145
START Condition Timing ......................... 145, 146
STOP Condition ............................................... 148
STOP Condition Timing (Case 1) .................... 148
STOP Condition Timing (Case 2) .................... 148
Tran s mit Timing ............ .. ................. .. ........... .. . 144
Bus Collision Timing ................................. ......... ...... 144
Clock Arbitration ...................................................... 143
Clock Arbitration Timing (Master Transmit) .. ........... 143
General Call Address Support ................................. 133
Master Mode 7-bit Reception Timing ................. .. .... 141
Master Mode Operation ........................................... 135
Master Mode START Condition .............. .. ......... .... .. 137
Master Mode Transmission ..................................... 139
Master Mode Transmit Sequence ............................ 135
Mult i - Ma ster Mo d e ................ .. ........... .. ................. .. . 144
Repeat START Condition Timing ........................ .. .. 138
STOP Condition Receive or Transmit Timing .......... 143
STOP Condition Timing ........................................... 142
Wave forms for 7-b i t R e c e p t i o n .. .. ...... .. ................. .. . 130
Waveforms for 7-bit Transmission ........................... 130
ICEPIC In-Circuit Emulator .............................................. 230
ID Locations ........................................... .................. 179, 186
INCF ................................................................................ 208
INCFSZ ............................................................................ 209
In-C i r cu i t Se rial Prog ramm i n g (IC SP) .. .................... 1 7 9 , 1 8 6
Indirect Addressing ............................................................ 51
FSR Register ............................................................. 50
INFSNZ ............................................................................209
Instruction Cycle ................................................................ 39
Instr uction Fl o w /Pipe l i n i n g ...... .. ........... .. ............ .. .............. 40
Instruction Format ............................................................ 189
1999-2013 Microchip Technology Inc. DS39026D-page 293
PIC18CXX2
Instruction Set ..................................................................187
ADDLW .................................................................... 193
ADDWF ....................................................................193
ADDWFC .................................................................194
ANDLW .................................................................... 194
ANDWF ....................................................................195
BC ............................................................................ 195
BCF ..........................................................................196
BN ............................................................................ 196
BNC .........................................................................197
BNOV .......................................................................198
BNZ ..........................................................................198
BOV .........................................................................201
BRA ..........................................................................199
BSF .......................................................................... 199
BTFSC .....................................................................200
BTFSS .....................................................................200
BTG ..........................................................................201
BZ ............................................................................202
CALL ........................................................................ 202
CLRF ........................................................................203
CLRWDT ..................................................................203
COMF ......................................................................204
CPFSEQ .................................................................. 204
CPFSGT ..................................................................205
CPFSLT ................................................................... 205
DAW .........................................................................206
DECF .......................................................................206
DECFSNZ ................................................................ 207
DECFSZ ...................................................................207
GOTO ......................................................................208
INCF .........................................................................208
INCFSZ .................................................................... 209
INFSNZ .................................................................... 209
IORLW .....................................................................210
IORWF ..................................................................... 210
LFSR ........................................................................211
MOVF .......................................................................211
MOVFF ....................................................................212
MOVLB ....................................................................212
MOVLW ...................................................................213
MOVWF ................................................................... 213
MULLW .................................................................... 214
MULWF ....................................................................214
NEGF ....................................................................... 215
NOP .........................................................................215
RCALL .....................................................................217
RESET ..................................................................... 217
RETFIE ....................................................................218
RETLW ....................................................................218
RETURN .................................................................. 219
RLCF ........................................................................219
RLNCF ..................................................................... 220
RRCF ....................................................................... 220
RRNCF ....................................................................221
SETF ........................................................................221
SLEEP .....................................................................222
SUBFWB ..................................................................222
SUBLW ....................................................................223
SUBWF .................................................................... 223
SUBWFB ..................................................................224
SWAPF ....................................................................224
TBLRD ..................................................................... 225
TBLWT .....................................................................226
TSTFSZ ...................................................................227
XORLW ................................................................... 227
XORWF ................................................................... 228
Summary Table ....................................................... 190
INT Interrup t ( RB0 /INT). See Interrupt Sources
INTCON Register
RBIF Bit .................................. ...... ....................... ...... 80
INTC O N R e g i s t e r s ........ .. ................. .. ................. .. ............ . 6 5
Inter-Integrated Circuit. See I2C
Internal Program Memo ry
Read/Writes ............................................................... 57
Inte rr u p t So u r ces .... ....................... .. ................. .. ....... 63, 17 9
A/D Conversion Complete ...... ............ ..................... 168
Capture Complete (CCP) ........................................ 109
Compare Complete (CCP) ...................................... 110
INT0 ........................................................................... 75
Interrupt-on-Change (RB7:RB4 ) ............................... 80
PORTB, on Change ................................................. .. 75
RB0/ INT Pin, Exte rn a l ..... .. ............................. .. ......... 75
SSP Receive/Transmit Complete ............................ 115
TMR0 ......................................................................... 75
TMR0 Overflow .......................................................... 95
TMR1 Overf low ........... .. ........... .. .......... 97, 99 , 103 , 1 0 5
TMR2 to PR 2 M atch ....... ......................................... 102
TMR2 to PR 2 M atch (PWM) ............................ 101, 1 12
USART Receive/Transmit Complete ....................... 149
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ............................... .... .. 109
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) ................................. 167
CCP1 Flag (CCP1IF Bit) .................................. 109, 110
Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ....... 80
IORLW ............................................................................. 210
IORWF ............................................................................. 210
IPR Registers ....................... ....................... ....................... 72
K
KEELOQ Evaluation and Programming Tools ................... 232
L
LFSR ............................................................................... 211
Long Write
and Interrupts . ........................................................... 59
Operation ................................................................... 58
Sequence of Events ............................................ ...... 58
Unex p e cted T e rm i n a t i o n ..... ............ .. ................. .. ..... 5 9
Low Vo l ta g e Dete ct ...... ............................. .. . ...... .. ........... 1 73
Block Diagrams
Exter n al R e feren ce So u rce ............................. 174
Inte rn a l R e fe rence So u rce ......... .. .................... 174
Conv e rter Ch a ra cteri stics ..................... .. ............ .. ... 242
Effects of a RESET ................... ...... ....... ...... ............ 177
Operation ................................................................. 176
Curre nt Con s u mptio n .. ...... .. ................. .. ......... 177
Duri ng SL EEP .... .. ............. ........ ...................... 17 7
Reference Voltage Set Point ........................... 177
LVD. See Low Voltage Detect.
PIC18CXX2
DS39026D-page 294 1999-2013 Microchip Technology Inc.
M
Master Synchronous Serial Port (MSSP). See SSP.
Memory Organization
Data Memor y ........ ....... ...... ............ ....... ............ ....... ..42
Program Memory .......................................................35
Migration from Baseline to Enhanced Devices ................288
MOVF ...............................................................................211
MOVFF .............................................................................212
MOVLB .............................................................................212
MOVLW ............................................................................213
MOVWF ...........................................................................213
MPLAB C17 and MPLAB C18 C Compilers .....................229
MPLAB ICD In-Circuit Debugger ......................................231
MPLAB ICE High Performance Universal
In-C ircuit Emula to r w i th M PLAB ID E .... .. ............ .. ....230
MPLAB Integrated Development
Environ ment Softwa re ...... ...... ...... ....................... .....229
MPLINK Obje c t Linker/MPL IB Objec t Librarian ...............230
MULLW ............................................................................214
Multi-Master Mode . ..........................................................144
MULWF ............................................................................ 214
N
NEGF ...............................................................................215
NOP .................................................................................215
O
On-Chip Reset Circuit
Block Diag ram .................. ............ ....... ............ ....... ....25
OPCODE Fiel d Descr i p tions ............ ............. ............ .......188
OPTION_REG Register
PS2:PS0 Bits .............................................................95
PSA Bit .......................................................................95
T0CS Bit .....................................................................95
T0SE Bit .....................................................................95
Oscillator Configuration ....................................................179
Oscillator Configurations ....................................................17
HS ..............................................................................17
HS + PLL ....................................................................17
LP ...............................................................................17
RC ........................................................................17, 18
RCIO ..........................................................................17
XT ..............................................................................17
Oscillator, Timer1 ................................... ......97, 99, 103, 105
Oscillat o r, WDT ..... ............................... ............. ...............183
P
Packaging ........................................................................277
Paralle l Sla ve Port (PSP) ....... ...... ............................. ...85, 90
Associ a te d Re g i sters ..... ................ ........................ ....91
Block Diag ram .................. ............ ....... ............ ....... ....90
RE0/RD/AN5 Pin ..................................................89, 90
RE1/WR/AN6 Pin .................................................89, 90
RE2/CS/AN7 Pin .......... ...... ...... ...... ....... ...... ...... ...89 , 90
Read Waveforms .......................................................91
Select (P SPMODE Bit) .. ................ ....... ...............85, 90
Timing Dia g ram ................................... ............ ....... ..251
Write Waveforms .......................................................90
PICDEM 1 Low Cost PIC MCU
Demonstration Board ...............................................231
PICDEM 17 Demonstra tion Board ..... ..............................232
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ...............................................231
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ...............................................232
PICSTART Plus Entry Level Development Syste m ......... 231
PIE Registers ..................................................................... 70
Pin Functions
MCLR/VPP ........................................................... 10, 13
OSC1/CLKIN .......................................................10, 13
OSC2/CLKOUT ................................................... 10, 13
RA0/ AN0 .. ........ ....... ........ ........ ..... ........ ........ ....... . 10 , 13
RA1/ AN1 .. ........ ....... ........ ........ ..... ........ ........ ....... . 10 , 13
RA2/ AN2 .. ........ ....... ........ ........ ..... ........ ........ ....... . 10 , 13
RA3/AN3/VREF ..................................................... 10, 13
RA4/T0CKI .......................................................... 10, 13
RA5/AN4/SS ........................................................ 10, 13
RB0/INT ............................................................... 11, 14
RB1 .. .......... ......................... ......... ........................ 11, 14
RB2 .. .......... ......................... ......... ........................ 11, 14
RB3 .. .......... ......................... ......... ........................ 11, 14
RB4 .. .......... ......................... ......... ........................ 11, 14
RB5 .. .......... ......................... ......... ........................ 11, 14
RB6 .. .......... ......................... ......... ........................ 11, 14
RB7 .. .......... ......................... ......... ........................ 11, 14
RC0/T1OSO/T1CKI ............................................. 12, 15
RC1/T1OSI/CCP2 ................................................ 12, 15
RC2/CCP1 ........................................................... 12, 15
RC3/SCK/SCL ..................................................... 12, 15
RC4/SDI/SDA ...................................................... 12, 15
RC5/SDO ............................................................. 12, 15
RC6/TX/CK .......................................................... 12, 15
RC7/RX/DT .......................................................... 12, 15
RD0/PSP0 ................................................................. 16
RD1/PSP1 ................................................................. 16
RD2/PSP2 ................................................................. 16
RD3/PSP3 ................................................................. 16
RD4/PSP4 ................................................................. 16
RD5/PSP5 ................................................................. 16
RD6/PSP6 ................................................................. 16
RD7/PSP7 ................................................................. 16
RE0/RD/AN5 .............................................................. 16
RE1/WR/AN6 .............................................................16
RE2/CS/AN7 .............................................................. 16
VDD ...................................................................... 12, 16
VSS ...................................................................... 12, 16
PIR Registers ......................... ............................. ....... ........ 68
Pointer, FSR ...................................................................... 50
POR. See Power-on Reset.
PORTA
Associated Registers ................................................. 79
Initialization ................................................................ 77
PORTA Register ........................................................ 77
RA3:RA0 and RA5 Port Pins ..................................... 77
RA4/T0CKI Pin ........ ...... ............. ............ ............. ...... 78
RA6 Pin ..................................................................... 78
TRISA Register .................................. ........................ 77
PORTB
Associated Registers ................................................. 82
Initialization ................................................................ 80
PORTB Register ........................................................ 80
RB0/INT Pin , External ...... ...... ............. ...... ................. 75
RB3 Pin ..................................................................... 81
RB3:RB0 Por t Pins .. ...... ...... ....... ...... ....................... .. 81
RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) .......... 80
RB7:RB4 Por t Pins .. ...... ...... ....... ...... ....................... .. 80
TRISB Register .................................. ........................ 80
1999-2013 Microchip Technology Inc. DS39026D-page 295
PIC18CXX2
PORTC
Associ a te d Re g i sters ...................... ....................... ....84
Block Diagram (Peripheral Output Override) .............83
Initialization ..........................................................83, 85
PORTC Register ........................................................83
RC3/SCK/SCL Pin ................. ............. .....................129
RC7/RX/DT Pin ........................................................151
TRISC Register ................ ...... ............. ...... .........83, 149
PORTD ..............................................................................90
Associ a te d Re g i sters ...................... ....................... ....86
Block Diagram (I/O Mode) ................ .... ...... ........... ....85
Parallel Slave Port (PSP) Function ............................85
PORTD Register ........................................................85
TRISD Register .......... ............ ....... ............ ....... ..........85
PORTE
Analog Port Pins ..................................................89, 90
Associ a te d Re gisters ................ ...... ...... ............. ...... ..89
Block Diagram (I/O Mode) ................ .... ...... ........... ....87
Initialization ................................................................ 87
PORTE Register ........................................................87
PSP Mode Select (PS PM ODE Bit) ......................85, 90
RE0/RD/AN5 Pin ..................................................89, 90
RE1/WR/AN6 Pin .................................................89, 90
RE2/CS/AN7 Pin ................ ....... ...... ...... ...... ....... ..89, 90
TRISE Register ....................................................87, 88
Postscaler, WDT
Assignment (PSA Bit ) .. ................. ...... .......................9 5
Rate Select (PS2:PS0 Bits) .......................................95
Switching Between Timer0 and WDT ........................95
Power-down Mode. See SLEEP.
Power-on Reset (POR) ..............................................26, 179
Oscillator Start-up Timer (OST) .........................26, 179
Power-up Timer (PWRT) ....... ............. ............. ..26, 179
Time-out Sequence ................................. .... ......... .... ..26
Time-out Sequence on Power-up ............. ......... ..32, 33
Timing Dia g ram .............. ............. ...... .......................24 8
Presca le r, Capture .. ....... ...... ....................... ............. ...... ..109
Presca le r, Timer0 ............... ............ ....... ....................... ......95
Assignment (PSA Bit ) .. ................. ...... .......................9 5
Rate Select (PS2:PS0 Bits) .......................................95
Switching Between Timer0 and WDT ........................95
Presca le r, Timer1 ............... ............ ....... ....................... ......98
Presca le r, Timer2 ............... ............ ....... ....................... ....112
PRO MATE II U n i ve rsal Pr o g ra mmer .. ................. .. .. .......231
Product Identification System ..........................................301
Program Counter
PCL Register ..............................................................39
PCLATH Register .................. ............. ...... .................39
Program Memory ...............................................................35
Inter rupt Vecto r ........ ................. ...... ...... ...... ....... ...... ..35
RESET Vector ............ ...... ....................... ....... ...... ......3 5
Program Verification ........................................................186
Programming, Device Instructions ...................................187
PSP.See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module).
PWM (CCP Module) ........................................................112
Associ a te d Re g i sters ...................... ....................... ..113
Block Diag ram .............. ....................... ............. ...... ..112
CCPR1H:CCPR1L Registers ...................................112
Duty Cycle ................ ............................. ...... .............1 1 2
Example Frequencies/Resolutions ..........................113
Output Dia g ram .............. ............. ...... ............. ...... ....112
Period .......................................................................112
Setup fo r PWM Operation ............. ............ ....... ...... ..113
TMR2 to PR2 Match ........................................101, 112
Q
Q Clock ... ............. ...... ............ ............. ............. ............ .... 112
R
RAM. See Data Me mory.
RCALL ............................................................................. 217
RCON Register .......................... .................................. 53, 56
RCSTA Register
SPEN Bit .................................................................. 149
Register File .... ............. ...... ............. ............ ............. ...... .... 42
Registers
ADCON0 (A/D Contro l 0 ) ...... ...... ............................. 165
ADCON1 (A/D Contro l 1 ) ...... ...... ............................. 166
CCP1CON and CCP2CON
(Capture/Compare/PWM Control) ................... 107
CONFIG1H (Configuration 1 High) .......................... 180
CON FIG1L (C o n figur a tion 1 Lo w ) ... ........... .. ...... .. ... 180
CONFIG2H (Configuration 2 High) .......................... 181
CON FIG2L (C o n figur a tion 2 Lo w ) ... ........... .. ...... .. ... 181
CONFIG3H (Configuration 3 High) .......................... 182
CON FIG4L (C o n figur a tion 4 Lo w ) ... ........... .. ...... .. ... 182
Flag ...................................................................... 68, 69
INTCON (Interrupt Control) ....................................... 65
INTCON2 (Interrupt Control 2) .................................. 66
INTCON3 (Interrupt Control 3) .................................. 67
IPR1 (Peripheral Interrupt Priority 1) ......................... 72
IPR2 (Peripheral Interrupt Priority 2) ......................... 73
LVDCON (LVD Control) ........................................... 175
PIE2 (Peripheral Interrupt Enable 1) ......................... 70
PIE2 (Peripheral Interrupt Enable 2) ......................... 71
PIR1 (Peripheral Interrupt Request 1) ....................... 68
PIR2 (Peripheral Interrupt Request 2) ....................... 69
RCO N (R e g i s t e r Control ) ... ...... .. ................. .. ............ . 7 4
RCO N (R ESET Co n tro l ) .. .. ......................... ......... 53, 56
RCSTA (Receive Status and Control) ..................... 150
SSPCON1 (SSP Control 1) ..................................... 118
SSPCON2 (SSP Control 2) ..................................... 120
SSPSTAT (SSP Status) .......................................... 116
STATUS .................................................................... 52
STKPTR (Stack Pointer) ............................................ 38
Summary ................................................................... 46
T0CON (Timer0 Control) ................................... ........ 93
T1CON (Timer1 Control) ................................... ........ 97
T2CON (Timer2 Control) ................................... ...... 101
T3CON (Timer3 Control) ................................... ...... 103
TRISE ........................................................................ 88
TXSTA (Transmit Status and Control) ..................... 149
RESET ............................................................... 25, 179, 217
Timing Diagram ....................................................... 248
RETFIE ............................................................................ 218
RETLW ............................................................................ 218
RETURN .......................................................................... 219
Revision History ............................................................... 287
RLCF ............................................................................... 219
RLNCF ............................................................................. 220
RRCF ............................................................................... 220
RRNCF ............................................................................ 221
PIC18CXX2
DS39026D-page 296 1999-2013 Microchip Technology Inc.
S
SCI. See USART.
SCK ..................................................................................121
SDI ...................................................................................121
SDO .................................................................................121
Serial Clock, SCK .............................................................121
Serial Communication Interface. See USART
Serial Data In, SDI ...........................................................121
Serial Data Out, SDO .......................................................121
Serial Peripheral Interface. See SP I
SETF ................................................................................ 221
Slave Select Synchronization ...........................................125
Slave Select, SS ..............................................................121
SLEEP ..............................................................179, 185, 222
Softwa re Simulator (MPLAB SIM ) ............. ...... .................230
Special Event Trigger. See Compare
Speci a l Features of the CPU ....................... ............ ....... ..179
Configuration Registers ...................................180–182
Special Function Registers ................................................42
Map ............................................................................45
SPI Master Mode ............................................................124
Serial Clock ..............................................................121
Serial Data In ...........................................................121
Serial Data Out ........................................................121
Slave Select .............................................................121
SPI Clock .................................................................124
SPI Mode .................................................................121
SPI Master/Slave Connection ..........................................123
SPI Module
Master/Slave Connection .................................. .......123
Slave Mode ..............................................................125
Slave Select Synchronization ..................................125
Slave Synch Timing .................................................125
Slave Ti min g with CKE = 0 ..................... ...... ...........126
Slave Ti min g with CKE = 1 ..................... ...... ...........126
SS ....................................................................................121
SSP .................................................................................. 115
Block Diagram (SPI Mode) ......................................121
I2C Mode. See I2C.
SPI Mode .................................................................121
Associ a te d Re g i sters ........... ............. ...... .........127
Block Diag ram .............. ....................... .............121
SPI Mode. See SP I.
SSPBUF ...................................................................124
SSPCON1 ................................................................ 118
SSPCON2 Register .................................................120
SSPSR .....................................................................124
SSPSTAT .................................................................116
TMR2 Output for Clock Shift . ...........................101, 102
SSP Module
SPI Master Mode .....................................................124
SPI Master./Slave Connection .................................123
SPI Slave Mode .......................................................125
SSPCON1 Register ..........................................................118
SSPOV .............................................................................139
SSPSTAT Register ..........................................................116
R/W Bit .....................................................................129
STATUS Regi ster ............ ....................... ........................ ....52
STKPTR Register ............ ....... ............ ....... ...... ...................38
SUBFWB ..........................................................................222
SUBLW ............................................................................223
SUBWF ............................................................................223
SUBWFB ..........................................................................224
SWAPF ............................................................................224
Synchronous Serial Port. See SSP.
T
TABLAT Regi ster ........... ...... ...... ....................... ....... .......... 57
Table Pointer Operations (Table) ...................................... 57
Table Read Operation, Diagram ........................................ 55
Tab le Write O p e r a t ion, D i a g ra m ... .. ..... .. ...... .. ...... . ...... .. ..... 55
TBLPTR Register ............................................................... 57
TBLRD ............................................................................. 225
TBLWT ............................................................................. 226
Timer0 ................................................................................93
Clock Source Edge Select (T0SE Bit ) ....................... 95
Clock Source Select (T0CS Bit) ................................. 95
Overflow In terrupt ...... ...... ...... ....... ............ ....... .......... 95
Prescaler. See Prescaler, Timer0
T0CON Registe r ...... ................................... ............. .. 93
Timing Dia g ram ................... ............. ............. ...... .... 249
Timer1 ................................................................................97
Block Diag ram ................... ............. ............ ....... ........98
Block Diagram (16-bit R/W Mode) ............................. 98
Oscillator .............................................. 97, 99, 103, 105
Overflow In terrupt ...... ...... .................... 97, 99, 103, 105
Prescaler. .................................................................. 98
Special Event Trigger (CCP) ..................... 99, 105, 110
T1CON Registe r ...... ................................... ............. .. 97
Timing Dia g ram ................... ............. ............. ...... .... 249
TMR1H Register ................................................ 97, 103
TMR1L Register ................................................. 97, 103
Timer2 .............................................................................. 101
Associated Registers ............................................... 102
Block Diag ram ................... ............. ............ ....... ......102
Postscaler. See Postscaler, Timer2.
PR2 Register ................................................... 101, 112
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ...............................................101, 102
T2CON Registe r ...... ................................... ............. 101
TMR2 Register .........................................................101
TMR2 to PR 2 M atch Interrupt . ..... .. .. ...... .. 101, 102, 112
Timer3 .............................................................................. 103
Associated Registers ............................................... 105
Block Diag ram ................... ............. ............ ....... ......104
Block Diagram (16-bit R/W Mode) ........................... 104
T3CON Registe r ...... ................................... ............. 103
Timing Diagrams
Acknowledge Sequence Timing .............................. 142
Baud Rate Generator with Clock Arbitration ............ 136
BRG Reset Due to SDA Collision ............................ 146
Bus Collision
START Condition Timing ................................. 145
Bus Collision During a Repeated START
Condition (Case 1) ........................................... 147
Bus Collision During a Repeated START
Condition (Case2) ............................................ 147
Bus Collision During a START Condition
(SCL = 0) ........... ............ ............. ............. ........146
Bus Collision During a STOP Condition .................. 148
Bus Collision for Transmit and Acknowledge .......... 144
I2C Bus Data ............................................................ 259
I2C Master Mode First START Bit Timing ................ 137
I2C Master Mode Reception Timing ......................... 141
I2C Master Mode Transmission Timing ................... 140
Master Mode Transmit Clock Arbitration ................. 143
Repeat START Condition ................................ .. .... .. 138
Slave Synchronization ............................................. 125
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram . ........................ 124
SPI Mode Timing (Slave Mode with CKE = 0) ......... 126
SPI Mode Timing (Slave Mode with CKE = 1) ......... 126
1999-2013 Microchip Technology Inc. DS39026D-page 297
PIC18CXX2
STOP Condition Receive or Transmit ......................143
Time-out Sequence on Power-up ............. ......... ..32, 33
USART Asynch ronous Mas ter Transm ission ...........156
USART Asynchronous Reception ............................158
USART Synchronous Reception ..............................161
USART Synchronous Transmission ........................160
Wake - u p from SLEEP via In terrup t ..........................186
Timing Diagrams and Specifications ................................246
A/D Conversion .......... ............ ....... ............ ...............262
Brown-out Reset (BOR) ...........................................248
Capture/Compare/PWM (CCP) ................................250
CLKOUT and I/O ......................................................247
External Clock ..........................................................246
I2C Bus Data ............................................................257
I2C Bus START/STOP Bits ......................................256
Oscillator Start-up Timer (OST) ...............................248
Paral l e l Sla ve Port (PSP) ............ ...... .......................25 1
Power-up Timer (PWRT) ....... .............................. ....248
RESET ..................................................................... 248
Timer0 and Timer1 ...................................................249
USART Synchronous Receive
(Master/Slave) .................................................260
USART SynchronousTransmission
(Master/Slave) .................................................260
Watchdog Timer (WDT) ....... ............... ...... ...............248
TRISE Register ..................................................................87
PSPMODE Bit ......................................................85, 90
TSTFSZ ...........................................................................227
Two-Word Instruc tions
Example Cases ..........................................................41
TXSTA Register
BRGH Bit .................................................................151
U
Universal Synchronous Asynchronous Receiver
Transmitter. See USART.
USART .............................................................................149
Asynchronous Mode ................................................155
Associated Registers, Receive ........................158
Associ a te d Re g i sters, Trans mit ............... ...... ..156
Master Transmission .......................................156
Receive Block Diagram ...................................157
Receiver ...........................................................157
Reception .........................................................158
Transmit Block Diagr a m ......... ............ ....... ......155
Transmitter .......................................................155
Baud Rate Generator (BRG) . .................................. 151
Associ a te d Re gisters ................ ................... .... 151
Baud Rate Error, Calculating ........................... 151
Baud Rate Formula ......................................... 151
Baud Rates, Asynchronous Mode
(BRGH = 0) .............................................. 153
Baud Rates, Asynchronous Mode
(BRGH = 1) .............................................. 154
Baud Rates, Synchronous Mode ................... .. 152
High Baud Rate Select (BRGH Bit) ................. 151
Sampling ......................................................... 151
RCSTA Regist e r .. ...... ....... ............ ............. ...... ........ 150
Serial Port Enable (SPEN Bit) ................................. 149
Synchronous Master Mode ...................................... 159
Associated Registers, Reception ............... .... .. 161
Associ a te d Re gisters, Tran smit ....................... 159
Reception ........................................................ 161
Timing Diagram, Synchronous Receive .......... 260
Timing Diagram, Synchronous
Transmission ........................................... 260
Transmission ................................................... 160
Associated Registers ............................... 159
Synchronous Slave Mode .................................... .... 162
Associa te d Re gisters, Receive ........................ 163
Associ a te d Re gisters, Tran smit ....................... 162
Reception ........................................................ 163
Transmission ................................................... 162
TXSTA Register ....................................................... 149
W
Wake-up from SLEEP .............................................. 179, 185
Timing Diagram ....................................................... 186
Usin g In t e r ru p ts ............ .. ................. .. ........... .. ......... 185
Watchdog Timer (WDT) ........................................... 179, 183
Associated Registers ............................................... 184
Block Diagram ......................................................... 184
Postscaler ................................................................ 184
Programming Considerations .................................. 183
RC Os c i l lator ...... ...... .. ........... .. ................. .. ............ . 1 8 3
Time-out Period ....................................................... 183
Timing Diagram ....................................................... 248
Waveform for General Call Address Seq uence ............... 133
WCOL .............................................................. 137, 139, 142
WCOL Status Flag ........................................................... 137
WDT ................................................................................ 183
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 227
XORWF ........................................................................... 228
PIC18CXX2
DS39026D-page 298 1999-2013 Microchip Technology Inc.
NOTES:
1999-2013 Microchip Technology Inc. DS39026D-page 299
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DS39026D
1. What ar e the best features of this document ?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
1999-2013 Microchip Technology Inc. DS39026D-page 301
PIC18CXX2
PIC18CXX2 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device PIC18CXX2(1), PIC18CXX2T(2);
VDD range 4.2V to 5.5V
PIC18LCXX2(1), PIC18LCXX2T(2);
VDD range 2.5V to 5.5V
Temperature
Range I= -40C to +85C (Industrial)
E= -40C to +125C (Extended)
Package JW = Windowed CERDIP(3)
PT = TQFP (Thin Quad Flatpack)
SO = SOIC
SP = Skinny plastic dip
P=PDIP
L=PLCC
Pattern QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC18LC452 - I/P 301 = Industrial temp.,
PDIP package, 4 MHz, Extended VDD
limits, QTP pattern #301.
b) PIC18LC242 - I/SO = Industrial temp.,
SOIC package, Extended VDD limits.
c) PIC18C442 - E/P = Extended temp. ,
PDIP package, 40MHz, normal VDD
limits.
Note 1: C = Standard Voltage range
LC = Wide Voltage Range
2: T = in tape and reel - SOIC,
PLCC, and TQFP
packages only.
3: JW Devices are UV erasable and can
be programmed to any device configu-
ration. JW Devices meet the electrical
requirement of each oscillator type
(including LC devices).
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microc hip sales office
2. The Microchip Worldwide Site (www.microchip.com)
PIC18CXX2
DS39026D-page 302 1999-2013 Microchip Technology Inc.
1999-2013 Microchip Technology Inc. DS39026D-page 303
Information contained in this publication regarding device
applications a nd t he lik e is provided only for yo ur conve nience
and may be superseded by updates . It is y our respo nsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip T echnology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI-TIDE , In - Circuit Serial
Programm ing, ICSP, Mindi, MiWi, MPASM, MPF, MP LAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co . & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1999-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769676
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCU s and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS39026D-page 304 1999-2013 Microchip Technology Inc.
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11/29/12
