RAD5A4
RECONFIGURABLE ARITHMETIC DATAPATH DEVICE
DESCRIPTION AND SPECIFICATIONS
MARCH 1997
INFINITE TECHNOLOGY CORPORATION
RAD5A4
Reconfigurable Arithmetic Datapath
ii March 1997 Infinite Technology Corporation
Phone: 972-437-7800
Quality Assurance
Our quality system focuses on high quality components and the best possible service for our customers.
The RAD5A4 has been designed to optimize arithmetic performance.
© 1995, 1996, 1997 Infinite Technology Corporation, Inc.
Infinite Technology Corporation, Richardson, Texas, reserves the right to make changes in its products
without notice in order to improve design or performance characteristics.
Trademarks
RAD ™ is a tra dem ar k of Inf inite T ec hnology Corpor ation, Ric hardson, T ex as .
RAD w are™ is a tra dem ark of Infi nite T echnolog y Corpora tion, Richa rdson, T ex as.
Reconf igur able A rithm e tic Da tapath™ is a trade m ark of I nfinite Te chnolog y Corporation, R ichar dson, T exa s.
RAD5A4
Reconfigurable Arithmetic Datapath Description & Specifications
Infinite Technology Corporation March 1997 iii
Phone: 972-437-7800
RAD5A4 DATA BOOK
Contents
Product Status 2
Part Number Description 3
High-Speed Accelerator f or Algorithms 4
Ar chi t ect ure Description 12
RAD5A4 Configuration 64
Device Specifications 89
Revision History 128
Terms and Definitions 129
Appendix 137
MacroSequencer programming information is found in the MacroSequencer
Programming Manual in this book. PLA programming and configuration file
generation is found in the RADware for Windows Manual. Simulation
information is found in the RAD VHDL Simulation Guide in this book.
Typical applications using RAD5A4 devices are described in various RAD
Notes which contain Application descriptions and implementations, Execution
Results, and Example MacroSequencer assembly programs.
RAD5A4
Description & Specifications Reconfigurable Arithmetic Datapath
iv March 1997 Infinite Technology Corporation
Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description & Specifications
Infinite Technology Corporation March 1997 v
Phone: 972-437-7800
TABLE OF CONTENTS
PRODUCT STATUS 2
PART NUMBER DESCRIPTION 3
HIGH-SPEED ACCELERATOR FOR DATA STREAM ALGORITHMS 4
HIGH-PERFORMANCE MULTIPLY-ACCUMULATE..............................................4
MULTIPLE OPERATIONS PER CLOCK CYCLE.....................................................4
DATA STREAM PROCESSING ...............................................................................5
RAD5A4 COMPONENTS......................................................................................5
RAD5A4 PERFORMANCE....................................................................................6
IMAGING APPLICATIONS .............................................................................................................................7
ARITHMETIC ACCELERATOR APPLICATIONS.................................................................................................7
RAD5A4 AS A COPROCESSOR ....................................................................................................................8
RAD5A4 IN MATRIX PROCESSING .............................................................................................................8
RAD5A4 FOR VIDEO FILTERING ................................................................................................................9
FFT NOISE FILTERING................................................................................................................................9
EASE OF IMPLEMENTATION..............................................................................10
DESIGN TOOLS .........................................................................................................................................11
IN-CIRCUIT RECONFIGURABILITY . . .GREAT TIME-TO-MARKET..................11
ARCHITECTURE DESCRIPTION 12
RAD5A4 DATA BUS..........................................................................................15
RAD5A4 CONTROL BUS...................................................................................15
INPUT CLOCKS...................................................................................................17
MACROSEQUENCER DESCRIPTION...................................................................18
MACROSEQUENCER ARITHMETIC DATAPATH.................................................19
INPUT REGISTERS .....................................................................................................................................21
INPUT SELECTOR ......................................................................................................................................22
MULTIPLIER-ACCUMULATOR ....................................................................................................................23
ADDER .....................................................................................................................................................25
SHIFTER ...................................................................................................................................................28
LOGIC UNIT..............................................................................................................................................30
1-PORT MEMORY .....................................................................................................................................31
3-PORT MEMORY .....................................................................................................................................32
Smart Indexing ................................................................................................................................... 33
OUTPUT SELECTOR ...................................................................................................................................35
I/O INTERFACE.........................................................................................................................................37
MACROSEQUENCER DATAPATH CONTROLLER ...............................................38
COMPONENTS...........................................................................................................................................38
CONTROL SIGNALS ................................................................................................................................... 40
RAD5A4
Description & Specifications Reconfigurable Arithmetic Datapath
vi March 1997 Infinite Technology Corporation
Phone: 972-437-7800
STATUS SIGNALS ...................................................................................................................................... 42
ADDER STATUS SIGNALS ..........................................................................................................................42
PROGRAM COUNTER.................................................................................................................................43
BRANCH OPERATIONS...............................................................................................................................44
LONG INSTRUCTION WORD REGISTER ....................................................................................................... 44
INSTRUCTION MEMORY ............................................................................................................................44
COUNTER0 AND COUNTER1......................................................................................................................44
STACK......................................................................................................................................................45
INDEX REGISTERS..................................................................................................................................... 46
MACROSEQUENCER CONFIGURATION BITS.....................................................48
RAD5A4 DUAL PLA DESCRIPTION.................................................................49
PLA INPUT SELECTORS ............................................................................................................................51
MINTERM GENERATOR .............................................................................................................................53
AND ARRAYS..........................................................................................................................................53
AND ARRAY FUNCTION GENERATOR .......................................................................................................54
FIXED OR ARRAYS...................................................................................................................................56
CONTROL OR ARRAY...............................................................................................................................58
CTRLREG REGISTER .................................................................................................................................60
OUTPUT OR ARRAY .................................................................................................................................61
OUTPUT REGISTER.................................................................................................................................... 63
PLAI/O BUFFERS..................................................................................................................................... 63
RAD5A4 CONFIGURATION 64
CONFIGURATION CONTROL PIN DESCRIPTION................................................65
RAD5A4 CONFIGURATION MODES..................................................................66
NORMAL OPERATING MODE: PGM0 = PGM1 = LOW............................................................................66
PASSIVE CONFIGURATION MODE: PGM0 OR PGM1 = HIGH, THE OTHER LOW......................................66
ACTIVE CONFIGURATION MODE: PGM0 = PGM1 = HIGH.....................................................................67
CONFIGURING A RAD5A4 DEVICE ..................................................................67
CONFIGURATION WITH POSITIVE HANDSHAKING SIGNALS ............................68
CONFIGURATION TIMING..................................................................................69
CONFIGURATION SUMMARY......................................................................................................................75
MINIMIZING CONFIGURATION TIME...........................................................................................................78
CONFIGURATION WITHOUT HANDSHAKING ................................................................................................80
TIME TO CONFIGURE THE RAD5A4.................................................................83
PLACLK PU LSES PER MEMORY CONFIGURED..........................................................................................83
Reading the PLACLK Pulses for Configuration Table.......................................................................84
PLACLK PU LSES FOR DEVICE CONFIGURATION.......................................................................................85
DEVICE CONFIGURATION TIME .................................................................................................................86
MULTIPLE RAD5A4 DEVICE CONFIGURATION...............................................87
CONFIGURATION DATA WORD COUNTER........................................................88
DEVICE SPECIFICATIONS 89
PIN LIST.............................................................................................................91
ABSOLUTE MAXIMUM RATINGS .......................................................................93
RAD5A4
Reconfigurable Arithmetic Datapath Description & Specifications
Infinite Technology Corporation March 1997 vii
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TTL-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION)..............94
5 V CMOS-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION).....99
3.3 V CMOS-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION)104
TIMING DIAGRAMS..........................................................................................109
AC MEASUREMENT DIAGRAM OF THE LOAD CIRCUIT FOR OUTPUT .........................................................111
TRANSITIONING BETWEEN ACTIVE AND NORMAL OPERATING MODES .......112
WAVEFORMS ..........................................................................................................................................113
PIN DIAGRAM ..................................................................................................114
RAD5A4 PIN DESCRIPTION...........................................................................115
POWER SUPPLY PINS ..............................................................................................................................115
MACROSEQUENCER PINS........................................................................................................................116
BUS 4 INPUT PINS...................................................................................................................................118
PLA PINS...............................................................................................................................................119
CONFIGURATION PINS.............................................................................................................................120
SCAN PINS..............................................................................................................................................121
PACKAGE CHARACTERISTICS .........................................................................122
POWER DISSIPATION VERSUS CLOCK FREQUENCY ..................................................................................122
THERMAL CHARACTERISTICS ..................................................................................................................124
PACKAGE MECHANICAL DETAILS..................................................................126
THIN QUAD FLAT PACK (TQFP), 176 PINS .............................................................................................126
POWER TQFP, 176 PINS.........................................................................................................................127
REVISION HISTORY 128
TERMS & DEFINITIONS 129
ACRONYMS ......................................................................................................129
GLOSSARY........................................................................................................130
APPENDIX 137
TABLE OF SIGNAL NAMES...............................................................................137
MACROSEQUENCER LONG INSTRUCTION WORD ..........................................142
Multiplexers......................................................................................................................................142
Assembly Operations........................................................................................................................145
LIW SETTING SUMMARY........................................................................................................................152
JTAG SCAN CIRCUITRY.................................................................................155
BOUNDARY SCAN PATH MAP..................................................................................................................156
Instruction Register...........................................................................................................................160
Device Identification Register Specification ....................................................................................161
RAD5A4
Description & Specifications Reconfigurable Arithmetic Datapath
viii March 1997 Infinite Technology Corporation
Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Description & Specifications
Infinite Technology Corporation March 1997 1
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TABLE OF FIGURES
Figure
Number
Figure Name
Page Number
1 Part Number Description 3
2 Simplified RAD5A4 Operational Block Diagram 5
3 Video Filter Application 7
4 RAD5A4 as a Coprocessor 8
5 Matrix Processing 8
6 Reconfigurable Video Filter 9
7 FFT Noise Filter 9
8 Programming the RAD5A4 10
9 Simplified RAD5A4 Data Flow Block Diagram 13
10 MacroSequencer 18
11 MacroSequencer Datapath Block Diagram 20
12 MacroSequencer Input Registers 21
13 MacroSequencer Input Selector 22
14 Multiplier-Accumulator 23
15 Adder 26
16 Shifter 29
17 Logic Unit 30
18 1-port Memory 32
19 3-port Memory 32
20 3-port Memory Index Pointers 34
21 Output Selector 21
22 I/O Interface 22
23 MacroSequencer Datapath Controller 39
24 Dual PLA Block Diagram 49
25 PLA Input Selector 52
26 Product Terms 54
27 Function Generator 54
28 Fixed OR0 Block Diagram 56
29 Fixed OR0 Schematic 57
30 Fixed OR1 Block Diagram 57
31 Fixed OR1 Schematic 58
32 Control OR 59
33 Control OR Simplified Schematic 60
34 Control Register 61
35 Output OR 62
36 Output OR Simplified Schematic 63
37 Output OR Register 63
38 PLAI/O Buffers
RAD5A4
Description & Specifications Reconfigurable Arithmetic Datapath
2 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
Figure
Number
Figure Name
Page Number
39 Configuration Timing - Initial Portion 70
40 Configuration Timing - Mid-Cycle Portion 70
41 Configuration Timing - Continue Portion 71
42 Configuration Timing - Halt Portion 71
43 Configuration Timing with Invalid Preamble 74
44 Minimizing Configuration Timing - Mid-Cycle Portion 78
45 Detailed Configuration Timing - Mid-Cycle Portion 79
46 Synchronous Configuration Timing - Initial Portion 80
47 Synchronous Configuration Timing - Mid-Cycle Portion 81
48 Synchronous Configuration Timing - Continue Portion 81
49 Synchronous Configuration Timing - Halt Portion 82
50 Multiple RAD5A4 Configuration 87
51 Configuration Data Word Counter 88
RAD5A4
Reconfigurable Arithmetic Datapath Description & Specifications
Infinite Technology Corporation March 1997 1
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RAD5A4
RECONFIGURABLE ARITHMETIC DATAPATH DEVICE
DATAPATH SOLUTIONS . . .
SMALLER, FASTER, SOONER
INFINITE TECHNOLOGY CORPORATION
RAD5A4
Description & Specifications Reconfigurable Arithmetic Datapath
2 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
Product Status
Infinite Technology Corporation uses various product status markings to designate phases of documentation
as it relates to the products. The markings appear at the beginning of each d ata sheet. The following Data
Sheet Classification definitions explain the status of the specifications presented in this Data Book.
Definitions
Da t a S h e e t C l a s s i fi c a t io n Product Status Definition
Objective Specification Forma tive or
In Design
This data sheet reflects the target design specifications for
product dev elopm ent. Specif ications m ay chang e in any
ma nner w ithout notice.
Preliminary Specification
Preproduction
Product
This da ta sheet r efle cts prelim inary data ba sed on
engineering samples. Characterization tests have not been
comple ted on some param eters. Supplem entary data w ill be
published upon av ailability . Specif ication c hanges m ay be
ma de at any tim e without notic e to impr ove the de sign and
supply the best pos sible produc t.
Production Specification
Full Production This data she et refle cts Final Specif ications. Inf inite
Tec hnology Corporation re serve s the rig ht to mak e chang es
in its products w ithout notice in order to im prove de sign or
performance characteristics.
table 1
RAD5A4
Reconfigurable Arithmetic Datapath Description & Specifications
Infinite Technology Corporation March 1997 3
Phone: 972-437-7800
Part Number Description
Part number ordering information for ITC devices is shown in the following diagram. For information on
specific package, speed, o perating temperat ure combinations, and in t erface type, refer to indivi dual device
data sheets in this data book, or contact ITC Marketing at (214) 437-7800.
RAD 5A4 - 100 T C Q 176
Device Family
RAD = Reconfigurable Arithmetic
Datapath
Interface Type
Device Number
5A4 = 5 internal data buses / 4
MacroSequencers
T = 5 V TTL
C = 5 V CMOS
V = 3.3 V CMOS
Operating Clock Frequency
Designation in MHz
Operating Temperature Range
C = Commercial (0° to +70°C)
Device Package Type
Q = Thin plastic quad flat pack (TQFP)
H = Power TQFP
-100 = 100 MHz (5V only)
-70 = 70 MHz (5V only)
-60 = 60 MHz
-40 = 40 MHz
Pin Count
176 = 176 pins
figure 1
Device Type Operating Clock
Frequency
(MHz)
Interface
Type Operating
Tem perature
Range
Device
Package
Type
Number of
Pins
RAD5A4 -70, -100 T, C C Q,H 176
-40, -60 V
table 2
RAD5A4
Reconfigurable Arithmetic Datapath
4 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Device
High-Speed Accelerator for Data Stream Algorithms
The RAD5A4 is a high speed accelerator for data stream algorithms. It contains four
independent 16- bit fi xe d-point progr am m able proce ss ors ca lled Ma croSe quence rs
that togethe r exe cute Multiple Instructions on Multiple Data paths (MIMD). T he
MacroSe quence rs m a y opera te inde pendently or com bined f or ev en g rea ter
perf orm anc e in those sy st em s re quiring rea l-tim e ope ration.
High-Performance M ultiply-Accumulate
Operating at 100 MHz and 75-100% multiplier efficiency across a wide range
of appli cat ions, the RAD5A4 MacroSeq uencer architecture provides:
• One 16 by 8 multiply-accumulate (MAC) per clock cycle
• Up to 400 Million 16 by 8-bit MACs per second or
• Up to 200 Million 16 by 16-bit MACs per second
Multiplier efficiency is enhanced with local I/O Registers, 1-port and 3-port
Memories using smart Index Registers. The multiplier’s accumulator is 48 b its
to support extended filter and linear transform computations.
Multiple Operations per Clock Cycle
Each RAD5A4 MacroSequencer is designed with a Long Instruction Word (LIW)
architec ture e nabling m ultiple ope rations per c lock cy cle . Independe nt operation
fie lds in the L IW control the Macr oSequenc er’s data m em ories , 16-bit adde r,
multiplier-accumulator, logic unit, shifter, and I/O registers so they m ay be used
sim ultaneous ly with br anch c ontrol. The pipelined a rchitec ture a llow s up to sev en
operations of the execution units during each clock cycle.
• 3 - 7 Operations per clock cycle per MacroSequencer
• 300 - 700 Million operations per second per
MacroSequencer
• 1 to 2 Billion operations per second per RAD5A4
The RAD5A4 LIW architecture optimizes performance allowing algorith ms
to be implemented with a small number of long instruction words. Each
MacroSequencer holds thirty-two LIWs, each capable of 3-7 operati ons.
RAD5A4
Reconfigurable Arithmetic Datapath
Infinite Technology Corporation March 1997 5
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Data Stream Processing
The RAD5A4 provid es a cost effective, quick time-to-market solutio n
for High Speed Data Stream requirements in imaging and simulation
applications such as Video, Real-time Custom Array, Parallel Processor,
Medical and Photo Manipulation.
Math Algorithm Output Data
Stream
RAD5A4
Input Data
Stream
The RAD5A4 takes one or more input data streams, applies high-speed
arithmetic algorithms, and outputs one or more data streams.
RAD5A4 Components
The heart of the RAD5A4 consists of the four MacroSequencers which are
supported by:
• five global 16-bit buses,
• connections to 64 I/O pins and 16 input pins,
• a built-in Dual PLA with 8 I/O pins and 8 input pins,
• five independent clocks which drive four MacroSequencers and the Dual
PLA at clock rates up to 100 MHz.
Simplified RAD5A4 Operational Block Diagram
Control Bus
Bus0 to 3
Dual
PLA
PLAI/O[7:0]
MS3I/O[15:0]
MS1I/O[15:0]
Bus4IN[15:0]
Macro-
Sequencer
3
Macro-
Sequencer
1
PLAIN[7:0]
MS2I/O[15:0]
MS0I/O[15:0]
Macro-
Sequencer
2
Macro-
Sequencer
0
Bus 4
figure 2
RAD5A4
Reconfigurable Arithmetic Datapath
6 March 1997 Infinite Technology Corporation
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PLA
The RAD5A4 contains a Dual PLA which may be used for initiating stream
processes, output enable signal generation, and gl ue interface. The Dual PLA
is often referred to simply as the PLA.
Package
The RAD5A4 is available in the 176-pin 24 x 24 mm plastic Thin Quad Flat
Pack (TQFP) and Power TQFP packages.
RAD5A4 Performance
The RAD5A4 accelerates arith metic algorithms such as:
• Discrete Cosine Transform (DCT)
• Inverse Discrete Cosine Transform (IDCT)
• Finite Impulse Filter (FIR) filter at video speeds
• Fast Fourier Transform (FFT) analysis
• Array processing
• Convolution
• Linear transformations
• Signal processing and formatting
• Process control
For example, these speeds are typical of RAD5A4 performance:
Algorithm No. of
RAD5A4s Data Stream
Speed
1024 complex 16-bit FFT* 1 205 µs
5 by 5 Convolution 1 70 ns
3 by 3 Convolution 1 30 ns
8 pt DCT (8 bit) 1 110 ns
8 pt IDCT (8 bit) 1 100 ns
2-D DCT (8 bit) 8 220 ns
2-D IDCT (8 bit) 8 200 ns
16 Tap FIR 1 80 ns
64 Tap FIR 1 320 ns
YUV to RGB Color Space Conversion 1 30 ns
table 3
* Computation of inner most loop only. Refer to FFT RAD Note.
RAD5A4
Reconfigurable Arithmetic Datapath
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Imaging Applications
Imaging applications require many multiply-accumulates and benefit from
greater performance. The RAD5A4 improves these imaging applicatio ns:
• Video filter
• Multi-media image scaling and image functions
• Medical instrumentation
• Photo manipulation
• Satellite
• Radar
• Sonar
Math Algorithm
RAD5A4
Video
Input
A/D
R
G
B
Video Filter Application
3-
Channel
D/A
figure 3
Arithmetic Accelerator Applications
• Communications (Linear transformations)
• Digital Compression
• Robotics
• FPGA Coprocessor
• DSP Coprocessor
• Avionics
• Encryption
• 2D and 3D Digital Filtering
• FFT Noise Filtering
RAD5A4
Reconfigurable Arithmetic Datapath
8 March 1997 Infinite Technology Corporation
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RAD5A4 as a Coprocessor
Math Algorithm Output Data Stream
RAD5A4
Input Data Stream
Micro-Computer
DSP
FPGA
RAD5A4 as a Coprocessor
figure 4
RAD5A4 in Matrix Processing
RAD5A4 devices may be combined into blocks of any number of
MacroSequencers for larger algorithms.
RAD5A4
FPGA
Memory
Data and Control Buses
Output Data Stream
Input
Data Stream
Matrix Processing
FPGA
Control
figure 5
One or more FPGAs, DSPs, or other microprocessors may be used for
interfacing to the Buses.
RAD5A4
Reconfigurable Arithmetic Datapath
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RAD5A4 for Video Filtering
NTSC is an in t erl aced video protoco l which requi res a frame buffer for 2-
dimensional applications. In less complex applications, a frame buffer may not
be necessary.
RAD5A4
Video
Filter
FPGA
Switch
Matrix
D/A
Video
Encoder
A/D
Video
Decoder
NTSC /
PAL
Input
Enhanced
NTSC / PAL
Ouput
Reconfigurable Video Filter
Frame
Buffer
figure 6
FFT Noise Filtering
FFT
Transform to
frequency domain
and separate low
frequency noise
from signal
RAD5A4
Time domain
input with low
frequency noise
R
G
B
Noise Removal in Video and Audio
Optional
Filter
Inverse FFT
From frequency
to time domain
RAD5A4
Filtered time
domain output
with noise
reduction
figure 7
RAD5A4
Reconfigurable Arithmetic Datapath
10 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
Ease of Implementation
Applications development is simplified with the following features:
• Programming is readily implemented using RADware design tools.
• Predictable timing for arithmetic algorithms.
• Example PLA configurations are predefined in the RADware design tool s.
• 5 V TTL, 5V and 3.3 V CMOS in terface
• Rapid Reconfiguration in less than 150 µs
Each MacroSequencer is programmed using the RAD5A4 assembly language.
It is a hardware oriented instruction set with only fourteen Datapath operations
and sixteen Controller operations. Each operation performs multiple low-level
operations. Most operations may be executed during each clock cycle allowing
multiple operations per cycle for high performance and efficient processing.
The D ual PLA is progra m m ed us ing a s ubse t of the VHDL la nguag e. T he
MacroSe quence r inst ruction code and PLA s ource code m a y be c rea ted in a ny text
editor. These PLA and MacroSequencer source files are then compiled using a
VHDL compiler and RAD5A4 assem bler and combined by RAD5A4 software to
produce a conf igura tion file . A ve ctor f ile is produced f or VH DL s im ulation. T hese
files are used to configure the RAD5A4 device and for simulation.
When programming RAD devices, the design is separated into:
• Arithmetic Algorithms to be programmed into the MacroSequencers and
• Test Vectors and
• Process initiation and response, handshake, and protocol logic to be
programmed into the Dual PLA.
.vec
Test Vectors
.msa
MacroSequencer
Source Code
RADware
Combines Source Files to create
Configuration File and Simulation File
.cfg
Configuration File
.sim
Simulation File
.vhd
VHDL Design File
figure 8
RAD5A4
Reconfigurable Arithmetic Datapath
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Phone: 972-437-7800
Several standard configurations that bypass the PLA are provided within the
RAD software package. These options will program the PLA to do nothing
while con necting the MacroSequencers to external p i ns.
Dual PLA or External Control Signals
MacroSequencers may execute independently in two ways: Each
MacroSequencer or pair may execute independently from each other with
programs initiated from either the Dual PLA or the external control pins.
Design Tools The RAD5A4 is fully supported by ITC’s RADware™ system. This system
contai ns a VHDL compiler for programming th e PLA, the MacroSequencer
assembler, and the RAD5A4 Fitter which will combine the compiled files to
produce reports, a configuration file to program the RAD5A4 and a vector file
to use with the VHDL model and a simulator.
A VHD L m ode l and te st-benc h is prov ided f or tes ting and de bugg ing a pplica tions.
This VH DL m odel ca n be use d w ith Vanta ge or Model T ec hnology VHD L
sim ulators for r unning te st ve ctor s and v erif y ing desi gn oper ation.
The RADware™ system is offered with DOS or Windows interface.
In-Circuit Reconfigurability . . .Great Time-to-Market
The RAD5A4 is the first in a family of Reconfigurable Arithmetic Datapath
(RAD) devices design ed specifically for use in datapath applications that
demand high-speed arithmetic operations on a data stream. The RAD5A4 can
be reconfigured at any time in less than 150 µs.
FPGAs and CPLDs are inefficient solutions for arithmetic and datapath
appli cations. RAD5A4 devices specifically addr ess t hese performance and
density issues while retaining the flexibility and time-to-market benefits of
other programmable devices.
The low im plem e ntation cos t and hig h arithm etic perf orm anc e of RA D5A 4 dev ice s
provide signif ica nt advanta ges for c omputa tionally intensiv e applic ations.
RAD5A4 devices offer the simplicity of a digital filter, the dynamic flexibility
of a DSP, and the speed of a cust om ASIC.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
12 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath Device
High Speed Accelerator for Data Stream Algorithms
Architecture Description
The RAD5A4 is composed of an array of four 16-bit fixed-point processors,
called MacroSequencers, that can be individually initiated either by using the
Dual PLA-based built-in periphery logic or directly from the control pins.
Five 16-bit data buses connect the MacroSequencers and 80 pins to allow data
to be shared and passed according to design needs. In ad dition each pair o f
MacroSequencers is coupled directly by two private 16-bit buses. These
private b uses allow each pair of MacroSequencers to be paired together for
additional data sharing.
The he art of the R A D5A 4 are the f our Mac roSeque nce rs w hich a re s upported by :
• Five global 16-bit buses, (bus0 to 4),
• Connections to 64 I/O pins (MS0I/O[15:0], MS1I/O[15:0] , MS2I/O[15:0],
MS3I/O[15:0]) and 16 input pins (BUS4IN[15:0]),
• Five independent clocks which drive the PLA and 4 MacroSequencers at
clock rates up to 100 MHz.
• A built-in Dual PLA.
MacroSequencers
Each RAD5A4 MacroS equencer is d esi gned with a Long Instruction Word
(LIW) architecture enabling multiple operations per clock cycle. Independent
operation fields in the LIW control the MacroSequencer’s data memories, 16-
bit adder, multiplier-accumulator, logic un it, shifter, and I/O registers so they
may be used simultaneously with branch control. The pipelined architecture
allows up to seven operations of th e execution units during each cycle.
The RAD5A4 LIW architecture optimizes performance allowing algorith ms to
be implemented with a small number of long instruction words. Each
MacroSequencer may be configured to operate independently, or can be paired
for some 32-bit arithmetic operations.
MacroSequencer0, 1, 2, and 3 are referred to as MacroSequencer(n) or MSn
where the n specifies the respective MacroSequencer number.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 13
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The data flow to and from the MacroSequencers is shown here:
Simplified RAD5A4 Control and Data Flow Diagram
Control Bus
PLAI/O[7:0]
MS3I/O[15:0]
MS1I/O[15:0]
BUS4IN[15:0]
Macro-
Sequencer
3
PLAIN[7:0]
MS2I/O[15:0]
MS0I/O[15:0]
Macro-
Sequencer
2
Bus4
Dual
PLA
MSPair32
Macro-
Sequencer
0
Bus0
Bus1
Bus2
Bus3
Macro-
Sequencer
1
16
16
16
16
16
16
16
16
32
16
8
8
8
8
12
MSn Direct
Control and
Status Pins
8
20
MSPair23
MSPair10
MSPair01
figure 9
Built-In Glue Logic
A prog ram m able Dua l PLA is built into the devic e to initiate processes in the
MacroSequencers and provide glue logic interface capabilities. The PLA I/O[7:0]
pins can be conf igure d individua lly as input only or output only pins. T hese ca n be
used for external interface control. Process initiation and response m a y be prov ided
exte rnally vi a input pins dire ctly to the MacroSe quenc ers or it m ay be pr ovided by
the progr am m able PLA via the contr ol bus.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
14 March 1997 Infinite Technology Corporation
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Operation Modes
The R AD 5A 4 operate s in eithe r a nor m al oper ating m ode or a c onf igura tion m ode.
• The RAD5A4 is configured during the Active Configuration mode which
allows each Macro Sequencer’s instructio n memory and Data Memories and
Dual PLA memory to be programmed.
• In the Normal Operating mode, the RAD5A4 MacroSequencers concurrently
execute the Long Instruction Words (LIWs) programmed into each
MacroSe quence r’s ins truction m e m ory .
• The Passive Configuration mode disables the device I/O pins and disables
the device from being configured, so that other RAD5A4s in the same circuit
may be configured.
Paired MacroSequencer Operational Support
MacroSequencers may be used individually for 16-bit operations or in pairs fo r
standard 32-bit addition, subtraction, and logic operations. When pairing, the
MacroSequencers are not interchangeable. MacroSequencers 0 and 1 form one
pair, and MacroSequencers 2 and 3 form the other pair. The least significant
sixteen bits are processed by MacroSequencers 0 and 2. A summary of this
information is listed here:
Paired MacroSequencers
First Pair Second Pair
MacroSequencer number 0 1 2 3
Least significant 16-bits √
√
Most significant 16-bits √ √
Paired MacroSequencer 1 0 3 2
table 4
Paired MacroSequencer Bus Names
Each pair of MacroSequencers have two private data buses between them
labeled MSPair(nm) and MSPair(mn) where the first n or m references the
MacroSequencer that sources the data, and the second n or m references the
recipien t MacroSeq uencer. The n refers to the current M acroSequencer, and the
m refers to the other MacroSequencer in the pair. The source of the data is from
the Out R egB signal of th e MacroSequencer(m). The four data buses between
paired MacroSequencers are:
Name of Data buse s between
Paired MacroS equencers From
MacroSequencer To
MacroSequencer
MSPair01 0 1
MSPair10 1 0
MSPair23 2 3
MSPair32 3 2
table 5
RAD5A4
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RAD5A4 Data Bus
The RAD5A4 Data Bus is composed of five global 16-bit data buses that can
be simultan eously accessed by all of the MacroSequencers.
Four of the buses, bus0, bus1, bus2, and bus3, are associated with
MacroSequencer0, 1, 2, and 3 respectively. The fifth bus, bus4, always
receives data from BUS4IN[15:0] pi ns.
Data bus0, bus1, bus2, and bus3 receive data from either Macro Sequencer
output registers or from MacroSequencer I/O pins.
Each MacroSequencer has input access from all of the buses. However, each
MacroSequencer may only place data o nto its respective busn from its output
register, OutRegA or onto its MSnI/O pins.
Busn may receive inputs from either MSnI/O[15:0] pins or from the output
register, OutRegA of MacroSequ encer(n).
Input/Output between the busn and MSnI/O[15:0] pins are determined by
configurati on bit s and instruction memory in each MacroSequencer and
MSnOE and oepla[n].
RAD5A4 Control Bus
The Control Bus is used to communicate control, status, and output enable
information between the MacroSequen cer and the PLA or external
MacroSequencer pins.
Control Signals
Two control signals sent to the MacroSequ encer are described i n the
MacroSeq uencer Datapath Contro l ler section. They are used t o:
• Initiate one of two available LIW sequences,
• Continue execution of the LIW sequence, or
• Acknowledge the MacroSequencer status flags by resetting the send and
await state bits.
MacroSequencer(n)’s Configuration bit 5 determines whether the control
signals are from th e MSnCTRL[1:0] pins or from the PLA0 CtrlReg[2n+1:2n]
signals. Configuration bits may be selected using the RADware design tools.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
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Status Signals
The MacroSequencer always executes th e LIW in the LIW Register on every
clock cycle. The Await and Send status signals from t he MacroSequencer are
described in the MacroSequencer Datapath Controller section and indicate:
• The Program Counter is sequencing.
• The MacroSequencer is i n the send state, an d it has executed a specific LIW.
The Program Counter is continuing to sequence.
• The MacroSequencer is i n the await state, and it h as executed a specific
LIW. The Program Counter is not continuing to sequence, and it is awaiting
further commands before resuming.
Two status signals, Send and Await, sent from the MacroSequencer(n)s are
output both to the MSnAWAIT and MSnSEND pin outputs and to the Dual
PLA input selectors.
The MSn direct control pins shown in the Simplified RAD5A4 Control and
Data Flow diagram (figure 8) are the cont rol interface sign al s whi ch connect
directly between t he pins and each M acroSequencer. These signals
(MSnAwait, MSnSend, MSnCTRL[1:0], and MSnOE) are includ ed in the table
of MacroSeq uencer Cont rol Interface Signal s (t able 6).
Output Enable
The output enable circuitry for MacroSequencer(n) is described in the Output
Selection description and allows for output enable to be:
• From the Dual PLA oepla[n] outputs or from MacroSequencer(n) output
enable MSnOE pins.
• Always output
• Always input (the power up condition)
• Optionally inverted.
MacroSequencer Control Interface Signals
The following table lists the names of the control, status, and output enable
signals that interface with t he MacroSequencers.
MacroSequencer Status Signals Control Sig nal s Output Enable
To Pins &
Dual PLA From Pins From
Dual PLA From Pins From
Dual PLA
MacroSequencer0 MS0AWAIT,
MS0SEND MS0CTRL[1:0] PLACtrl0[1:0] MS0OE oepla[0]
MacroSequencer1 MS1AWAIT,
MS1SEND MS1CTRL[1:0] PLACtrl1[3:2] MS1OE oepla[1]
MacroSequencer2 MS2AWAIT,
MS2SEND MS2CTRL[1:0] PLACtrl2[5:4] MS2OE oepla[2]
MacroSequencer3 MS3AWAIT,
MS3SEND MS3CTRL[1:0] PLACtrl3[7:6] MS3OE oepla[3]
table 6
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
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Input Clocks
Five input clocks are provided to allow the RAD5A4 to process multiple data
streams at different transmissio n speeds. There is one clo ck for each
MacroSequencer, and a separate clock for the PLA. Each MacroSequencer can
operate on separate data paths at different rates. The clock signals can be
connected, for synchronization between the four MacroSequencers and the
Dual PLA.
The PLA clock (PLACLK) is used for Active Configuration Mode.
System Constraints
The MacroSequencers an d PLA change stat es on the ri sing edge of th ei r
respective clock signals.
Signals between the Du al PLA and the MacroSeq uencers are resynchronized at
the receiving MacroSequencer or Dual PLA.
Techniques should be employed to reduce timing skew wh ich may occur due to
printed circuit board layout.
When using the RAD5A4 at high clock frequencies, data should be loaded and
captured synchronously with proper set-up and hold times. The I/O bandwidth
on MSnI/O[15:0] pins and BUS4IN[15:0] is one-half of the MacroSequencer
clock frequency.
• Data to be input should be asserted on the pins for one MacroSequencer
clock period before the data is to be captured in a MacroSequencer’s
registers.
• Data to be output on these pins should be asserted one MacroSequencer
clock period before the data is to be captured by external circuitry.
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MacroSequencer Description
Each MacroSequencer is identical and composed of two functional blocks, the
Arithmetic Datapath, and the Datapath Controller. The 3-port and 1-port
memories are accessed by the arithmetic data pat h. The instruction memory, 3-
port and 1-port memories may be loaded during Active Configuration Mode.
Datapath
Controller
Arithmetic
Datapath
3-Port Memory
1-Port Memory
Instruction Memory
Control
Signals Status Signals
LIW Control bits
Adder Status bits:
Equal, Overflow, Sign
bus0, bus1,
bus2, bus3, bus4,
MSPair
mn
MacroSequencer (
n
)
Data In
bus
n
MSPair
nm
Data I/O Interface
423
6 x 16 1 x 16
26
MS
n
CTRL[1:0]
PLACtrl
n
[1:0]
MS
n
OE
oepla[
n
]
MSnI/O[15:0]
2 x 16
MS
n
Await
MS
n
Send
figure 10
The control signals may initiate one of two programmed LIW sequences in
instruction memory in normal operating mode. Once a sequence begins, it will
run, or loop indefinitely until stopped by the control signals. An await state
programmed into the LIW sequence will stop the Program Counter from
continuing to increment.
The LIW sequences are a combination of data steering, data processing, and
branching operations. Each M acroSequ encer may execute a combination of
branch, memory access, logic, shift, add, su btract, multiply-accumulate, and
input / output operations on each cl ock cycle.
The instruction memory can be reloaded dynamically at any time by transitioning
to Activ e Configuration Mode which will a lso initializ e all re g iste rs in the e ntire
device.
MacroSequencer0, 1, 2, and 3 are referred to as MacroSequencer(n) or MSn
where the n specifies the respective MacroSequencer number.
RAD5A4
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Macr oSequencer Arithmetic Datapath
The MacroSequencer Arithmetic Datapath is a p i pelined st ructure where dat a i s
processed in stages.
There are nin e basic elements in the MacroS equencer Arithmetic Datapath. Six
of these are data processing functions and the other three are data steering
functions. The data processing elements include:
• Multiplier-Accumulator (MAC),
• Adder,
• Shifter,
• Logic Unit,
• 3-port Data Memory, and
• 1-port Data Memory.
The data steering functions include the:
• Input Register block to capture any two inputs,
• Input Selec tor f or se lecting any thre e oper ands f or da ta proc ess ing el em ents , and
• Output Register block to select which two of the data processing elements
are stored .
The processor core contains four parallel data processing units: the Multiplier-
Accumulator (MAC), Adder, Logic Unit, and Shifter. Each data processing
unit runs independently of the others allowing the execution of multiple
operations per cycle.
Inputs to MacroSequencer(n) include:
• Direct access to si xt een I/O pin s (MSnI/O[15:0]).
• Five 16-bit internal buses (bus0, bus1, bus2, bus3, and bus4) where busn
may be co nnected to MSnI/O[15:0] or the output register, OutRegA from
MacroSequencer(n). Bus4 is always connected to BUS4IN[15:0] and is
shared b et ween t he MacroSequencers and the Dual PLA.
• The Paired MacroSequencer 16-bit bus MSPair(mn) from
MacroSequencer(m)’s OutR egB t o MacroSeq uencer(n)’s Input Register.
RAD5A4
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1-Port
Memory
MAC
Adder
Logic
Unit
Shifter
Output Selector
Input Selectors
Input Registers
bus0
bus1
bus2
bus3
bus4
Constant
MS
n
I/O
OutRegB
MacroSequencer (
n
) Datapath Block Diagram
Register
3-Port
Memory
InRegB
InRegA
'0'
mem0
mem2
mem1
InBusA
InBusB
InBusC
MultOutA,B
Adder Status
MSPairnm
bus
n
OutRegA
I/O Interface
MSPairmn
figure 11
Each of these data processing functions in the MacroSequencer Datapath Block
Diagram is discussed individually in the following sections. They are
controlled by the operation fields in the MacroSequencer’s LIW Register.
In the MacroSequencer discussions that follow, the terms ‘external’ and
‘intern al ’ do not refer to signals external and internal to the RAD5A4 device,
but only to signals external and internal to an individual MacroSequencer.
Relevant LIW Register control bits are shown in MacroSequencer Arithmetic
Datapath data processing functions. They are defined in the RAD5A4 Long
Instruction Word Appendix.
RAD5A4
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Input Registers The 16-bit input registers are named InRegA and InRegB. There are six
external inputs and one internal input available to the Input Registers.
InRegA
InRegB
bus0
bus1
bus2
bus3
bus4
MacroSequencer (
n
) Input Registers
Register
Constant
16
16
16
16
16
16
16
16
16
LIW[4:2]
LIW[7:5]
MSPairmn
figure 12
There are several possible input selections for each MacroSequ encer
Input Register:
• Five 16-bit internal buses (bus0, bus1, bus2, bus3, and bus4)
• The 16-bit bus from the partner MacroSequencer(m)’s OutRegB in each
pair labeled MSPair(nm), and
• A Constant (0-65535) generated from LIW Register bits LIW[43:28].
The Constant introduces 16-bit constants into any calculation. The constant of
the MacroSequen cer shares intern al signals with the MacroSeq uencer
Controller as well as the MAC, the Shifter, and the Logic Unit. Since the
Constant field of the LIW is shared, care must be taken to insure that overlap of
these sign al s does no t occur. The RAD5A4 Assembler detects and reports any
overlap problems.
Related Assembly Operations:
Syntax Allo wed values for ar guments
in <src>,<dest> <src>: bus0, bus1, bus2, bus3, bus4, pair, 0-
65535
<dest>: inrega, inregb
table 7
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
22 March 1997 Infinite Technology Corporation
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The pair parameter selects MSPair(mn) which is from OutRegB of the other
member of the pair of MacroSequencers. When no operation occurs, the input
register holds its data.
Resource Conflicts:
When using a constant value, there is a conflict with the MAC, Logic Unit,
Shifter, and some Datapath Controller instructions.
Input Selector The Input Selector generates the InBusA, InBusB, and InBusC signals. Data
on these buses are in dependent. There are cont rols on InBusB to en able the
number zero to be used and to invert the selected result. InBusA and InBusB
are available t o the MAC, Adder, and Logic Units. InBusC is available o nly to
the Shifter.
MacroSequencer Input Selector
InRegA
OutRegA
OutRegB
mem1
'0'
InRegB
InBusA
InBusB
InBusC
mem2
mem0
16
16
16
16
16
16
16
16
16
16
16
LIW[12:10]
LIW[13]
LIW[14]
LIW[9:8]
figure 13
Inputs to the Input Selector include:
• InRegA and InRegB from the Input Register,
• OutRegA and OutRegB from the Output Register,
• Mem1 and mem2 from the 3-port Memory read ports 1 and 2 respectively,
• Mem0 from the 1-port Memory read port, and
• Constant ‘0’ which is generated in the Input Selector and does not involve
LIW Register bits LIW[43:28].
Control signals from the MacroSequencer Controller determine which three of
the eight possible inputs are used and whether InBusB is inverted or not. The
Input Selector is automatically controlled by RADware assembly language
operations for the Multiplier, Adder, Shifter, and Logic Unit and does not
require separate programming.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
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The input selections are controlled by the same assembly operations used by
the MAC, Adder, Logic Unit and Shifter.
Multiplier-Accumulator
The Multiplier-Accumulator (MAC) is a three-stage, 16 by 8 mu ltiplier capable
of producing a full 32-bit product of a 16 by 16 multiply every two cycles. The
architecture allows the next multiply to begin in the first stages before the result
is output from the last stage so that once the pipeline is loaded, a 16 by 8 result
(24-bit product) is generated every clock cycle.
InBusA
InBusB
16 x 8 bit Multiplier
48 bit Accumulator
To Adder:
16 by 8 Multiplier - Accumulator
Register
mem0
OutRegB MultOutA
MultOutB
16
16
16
16
24
8
16
48
48
16
16
8
Operand A
Operand B
LIW[47,44]
LIW[42:41]
LIW[43,40]
24 16
16
16
16
figure 14
Input Stage
The MAC input stage loads operands A and B and assures proper byte
alignment for the multiplier. The multiplier input multiplexers serve
two purposes:
1) They align the high or low bytes from operand B for the multiplier which
allows 16 by 8 or 16 by 16 multiply operations; and
2) They allow the inputs to be selected from three different sources for each
operand:
a) Operand A is selected from the 1-port memory, InBusA, or operand A
from the previous cycle.
b) Operand B is selected from the high byte of OutRegB, InBusB, or the least
significant byte of the previous operand B.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
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Related Assembly Operations:
Syntax Allo wed values for ar guments
mult1 <srca>, <srcb> <srca>: inrega, outrega, outregb, mem1, mem0
<srcb>: inregb, outrega, outregb, mem2, mem0,
0
mult1 hold table 8
Resource Conflicts:
Using the mem0 or outregb arguments makes InBusA and In BusB available for
other assembly operations. A mult1 hold operation holds operand A and moves
the low byte of operand B to the Multiplier stage input.
Multiplier Stage
The Multiplier produces a 24-bit product from the registered 16-bit operand A
and either the most significant byte (8-bits) or the least significant byte of
operand B.
Accumulator Stage
The thir d stage aligns and accumulat es the product. Controls in the
accumulator al l ow the product to be multiplied by:
• 1 when <weight> is low, or
• 28 when <weight> is high.
The result is then:
• Added to the result i n the accumulat or when <enable> is acc,
• Placed in the accumulator replacing any previous value when <enable> is clr, or
• Held in the accumulato r in lieu of a mult3 operation.
A mult3 operation must follow two cycles after a mult1 operation. The
accumulator holds it s data when no mult3 is used.
The accumulator output divides the 48 - bit output i nto four 16-bit parts called
low (bits[15:0]), mid (bits[31:16]), high (bits [47:32]) and norm (bits[30:15]).
The low, mid, and high bits are used in conversion. Select norm when only the
top 16 bits of a signed multiplication result is required.
Related Assembly Operations:
Syntax Allo wed values for ar guments
mult3 <weight>, enable> <weight>: high, low
<enable>: clr, acc
add1 mult, <pos> <pos>: low, mid, high, norm
table 9
Cycles per Multiply
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
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The num ber of cy c les re quired f or Multiplies and MA Cs ar e show n in these tables .
Cycles B etween New Multipli es
Multiply Accuracy Cycles
16 by 8 16 bits 1
24 bits 2
16 by 16 16 bits 2
32 bits 3
table 10
Cycles Between New M ultiply - Accumulates of n Products
Multiply Accuracy Cycles
16 bits n
16 by 8 32 bits n + 1
48 bits n + 2
16 bits 2n
16 by 16 32 bits 2n + 1
48 bits 2n + 2
table 11
The MAC internal format is converted to standard integer format by the Adder.
For this reason, all multiply and multiply-accumulate outputs must go through
the Adder.
If a 16 by 8 bit MAC is desired, n ew operands are lo aded every cycle. The
Multiplier results in a 24-bit product which is then accumulated in t he third
stage to a 4- bit result. This allows at least 224 multiply-accumulate operations
before overflow.
If only the upper 16 bits of a 24-bit result are required, the lower 8 bits may be
discarded. If more than on e 16-bit word is extracted , the accumulated result
must be extracted in a specific order. First the lower 16-bit word is moved to
the Adder, followed in order by the middle 16 bits and then the upper 16 bits.
This allows at least 216 of these 16 by 16-bit multiply-accumulate operations
before overflow will occur.
For a 16 by 16-bit MA C, ne w opera nds m ay be loade d eve ry other cy cl e. Ex am ple
softw a re is in the Mac roSequenc er A s sem bly L ang uag e docum e ntation.
Adder The Adder produces a 16-bit result of a 16 by 16-bit addition, subtraction, or
16-bit data conversion to two’s complement every cycle. The Adder is also
used for equality, less-than and greater-than comparisons. The Adder is a two-
stage structure: the input multiplexers with the first adder stage and the second
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
26 March 1997 Infinite Technology Corporation
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adder stage. The architecture allows th e next adder operatio n to begin in t he
first stage before the result is output from the last stage.
The input mu ltiplexers select one of two sources of data for operation by the
Adder. The operands are selected from either InBusA and InBusB, or from the
Multiplier. Select InBusA and InBusB for simple addition or subtraction and
setting the Adder Status flags. Select the multiplier outputs, MultOutA and
MultOutB, for conversion.
Adder (pipe 1)
Adder
Output Selector
Adder Status Flags:
Equality, Overflow,
Sign
InBusA
InBusB
Register
MultOutA
MultOutB
16
16
16
16 16
16
16 16
16
LIW[15]
Adder (pipe 2)
Carry Out Carry In
4
LIW[16]
config
bit[3:2]
a=b In a=b Out
3
1
figure 15
The first adder st age recei ves the operands and begins the operation. The
second adder stage completes the operation and specifies the output registers in
the Output Selector where the result will be stored. The two adder stages may
be controlled separately for addition and subtraction operations.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
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Related Assembly Operations:
Syntax Allo wed values for ar guments
add1 <oper1>, <oper2> <oper1>: inrega, outrega, outregb, mem1
<oper2>: inregb, outrega, outregb, mem2,
mem0, 0
add1 mult, <pos> <pos>: low, mid, high, norm
add2 [<dest1> [, <dest2>]] <dest1>, <dest2>: outrega, outregb
sub1 <srca>, <srcb> <srca>: inrega, outrega, outregb, mem1
<srcb>: inregb, outrega, outregb, mem2, mem0,
0
sub2 [<dest1> [, <dest2>]] <dest1>, <dest2>: outrega, outregb
table 12
The add1 mult operation is used for data conversion in the Accumulator and
allows InRegA and InRegB to be available for other operations in the same
cycle. The sub1 operation inverts the InBusB selection. If sub2 is used, Carry
In is set to a logical ‘1’.
Adder Configuration Bits / Switches
Configuration bit[3] selects 32-bit or 16-bit addition or subtraction. The 32/16
bit configuration bit is set in the RADware design tools. For successful 32-bit
operation, MacroSequencer1 and/or MacroSequencer3 should have the 32/16-
bit configuration bit set for 32-bit operation. The MacroSequencer0 and
MacroSequencer2 32/16-bit configuration bit should always be set for LOW
for proper operation.
When in 32-bit mode, the a=b Out signal tells the other MacroSequencer in the
pair if Operand A and Operand B are equal. The a=b In signal is input ot the
upper 16 bits.
When MacroSequencer1 is in 32-bit mode, its External Carry In is from the
External Carry Out from MacroSequencer0. When MacroSequencer3 is in 32-
bit mode, its External Carry In is from the External Carry Out from
MacroSe quence r2. Ex ternal Carr y In f or Mac roSeque ncer0 a nd Mac roSeque ncer 2 is
from s pecia lized c ircuitry for addition and s ubtraction c arr ies.
Configuration bit[2] selects whether the operands are signed values or unsigned
values. The signed/unsigned configuration bit is set with directives when
programming the MacroSequencer.
Refer to the MacroSequencer Configuration bits discussion and the Assembler
Directives discussion in the MacroSequencer Programming Section for more
detail.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
28 March 1997 Infinite Technology Corporation
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Adder Status Bits
The Equal, Sign, Overflow, and Carry flags are set two cycles after an addition
operation ( add1 or sub1) occurs and remain in effect f or one clock cycle:
• The Equal flag is set when the two operands are equal during an addition
operation.
• The Overflow flag is set when the result of an addition or subtraction results
in a 16-bit out-of-range value.
• When the adder is configured for unsigned integer arithmetic,
Overflow = Carry. Range = 0 to 65535
• When the adder is configured for signed integer arithmetic, Overflow
= Carry XOR Sign. Range = -32768 to +32767
• The Sign flag is set when the result of an addition or subtraction is a
negative value.
• The Carry flag i ndicates whether a carry value exists.
Conversion
The Adder may be used to convert the data in the Accumulator of the
Multiplier to standard integer formats when inputs are selected from the output
of the MAC. The MAC outputs are shown as MultOutA and MultOutB on the
diagrams.
Since the Accumulator is 48 bits, th e multiplier’s accu mulated resu lt must be
converted in a specific order: lower-middle for 32-bit conversion, and lower-
middle-upper for 48-bit conversion. Once the conversion process is started, it
must continue every cycle until completed. Signed number conversion uses
bits 30:15. Conversion is explained in more detail in the MacroSequencer
Assembly Language examples.
Shifter Shift Mode (type) signals control which Shifter functions are performed:
• Logical Shift Left by n bits (shift low order bits to high order bits). The
data shifted out of the Shifter is lost, and a logical ‘0’ is used to fill the bits
shifted in.
• Logical Shift Right by n bits (shift high order bits to low order bits). The
data shifted out of the Shifter is lost, and a logical ‘0’ is used to fill the bits
shifted in.
• Arithmetic Shift Right by n bit s. This is the same as logical shift right
with the exception that the bits shifted in are filled with Bit[15], the sign bit.
This is equivalent to dividing the number by 2n.
• Rotate Shift Left by n bits. The bits shifted out from the highest ordered
bit are shifted into the lowest ordered bit.
• Normalized Shift Right by 1 bit. All bits are shifted one lower in order.
The lowest bit is lost and the highest b it is replaced by the Overflow Register
bit of the Adder. This is used to scale the number when two 16-bit words are
added to produce a 17-bit result.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 29
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Logical, Arithmetic and Rotate shifts may shift zero to fifteen bits as
determined by the Shift Length control signal.
Shifter
Adder Status
Overflow
InBusC Output
Selector
Shifter
16
16
1
LIW[35:32]
LIW[38:36]
n
type
figure 16
The Shift Mode (type) and the S hift Length (n) controls are shared by the
Constant word; therefore, only one of these functions may be used on any one
cycle. Constant inputs to the MacroSequencer are shown in the
MacroSequencer Datapath Block Diagram.
Related Assembly Operations:
Syntax Allo wed values for ar guments
shift <src>, <type>,<length>,
<dest1> [, <dest2>] <src>: inrega, outrega
<type>: logicleft, logicright, arithmetic,
rotate
<length>: 0-15 or 0x0-0xf
<dest1>, <dest2>: outrega, outregb
shift <src>, normal, <dest1>
[,<dest2>] <src>: inrega, outrega
<dest1>, <dest2>: outrega, outregb
table 13
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
30 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
Logic Unit The Logic Unit is able to perform a bit-by-bit logical function of two 16-bit
vectors for a 16-bit result. All bit positions will have the same function
applied. All sixteen logical functions of 2 bits are supported. The Logic
Function controls determine the function performed.
Logic Unit
InBusA
InBusB
Output
Selector
Logic
Unit
16
16
16
LIW[31:28]
a
b
figure 17
Related Assembly Operations:
Syntax Allo wed values for ar guments
logic <oper>, <dest 1> [, <dest2>] <oper>: 0, 1
<dest1>, <dest2>: outrega, outregb
logic <oper>, <srca>, <d est1>
[,<dest2>] <oper>: nota, a,
<srca>: inrega, outrega, outregb, mem1
<dest1>, <dest2>: outrega, outregb
logic <oper>, <srcb>, <dest1>
[,<dest2>] <oper>: notb, b
<src>: inregb, outrega, outregb, mem2 ,
mem0, 0
<dest1>, <dest2>: outrega, outregb
logic <oper>, <srca>, <srcb>,
<dest1> [, <dest2>] <oper>: nor, notab, anotb, xor, nand,
and, xnor, notaorb, aornotb, or
<srca>: inrega, outrega, outregb, mem1
<srcb>: inrega, outrega, outregb, mem2,
mem0, 0
<dest1>, <dest2>: outrega, outregb
table 14
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 31
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The sixteen logical functions are:
LIW[31:28] Operation Description
0 0 0 0 0 logical ‘0’
1 1 1 1 1 logical ‘1’
0 0 1 1 a a
1 1 0 0 a inverted va lue of a
1 0 1 0 b b
0 1 0 1 b inverted value of b
0 0 0 1 nor A nor B
0 0 1 0 a b not A and B
0 1 0 0 a b A and notB
0 1 1 0 xor A xor B
0 1 1 1 nand A nand B
1 0 0 0 and A and B
1 0 0 1 xnor A xnor B
1 0 1 1 a or b not A or B
1 1 0 1 a or b A or not B
1 1 1 0 or A or B
table 15
The Logic Function control s are shared by the Constant word, the Logic Un it,
the 1-port memory index register operations and the MAC Function. Only one
of these functions may be used on any one cycle.
The output is defined by the LIW bits as follows:
Out[i] = (LIW[28] and not A[i] and not B[i])
or (LIW[29] and A[i] and not B[i])
or (LIW[30] and not A[i] and B[i])
or (LIW[31] and A[i] and B[i])
1-Port Memory The 1-port memory supports single-cycle read and single-cycle write
operations, but not both at the same time.
There are 32 addressable 16-bit memory locations in the 1-Port Memory. A
separate register is provided to store and maintain the result of a read operation
until a new read i s executed.
Read and write operands control whether reading or writing memo ry is
requested. No operation is performed wh en both the Read and Write controls
are inactive. Only one operat i on, read or write, can occur per cycle.
Index register I1P in the Datapath Controller provides the read and write
address to the 1-port memory. The index register may be incremented,
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
32 March 1997 Infinite Technology Corporation
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decremented, or held with each operation. Both th e index operation and the
read or write operation are controlled by the MacroSequencer LIW.
1-Port Memory
OutRegA mem0
32 x 16
RAM
Register
16 16
LIW[1]
1-port Address
LIW[0]
5
figure 18
Related Assembly Operations:
Syntax Allo wed values for ar guments
oneport <oper> <oper>: write, read
table 16
3-Port Memory The 3-port memory is a 16 x 16-bit RAM that supports two read and one write
operation o n each clock cycle. The two read por ts may be us ed independently;
however, data may not be written to the same address as either read address in
the same clock cycle.
3-Port Memory
mem2
Register
mem1
OutRegB 16 x 16
RAM
16
16
16
3-port Read1 Address
3-port Read2 Address
3-port Write Address
4
4
4
LIW[45]
LIW[46]
LIW[46,45,22]
figure 19
Four index registers are associated with t he 3-port memory. Two separate
registers are provided for write indexing: Write Offset (I3PWO) and Write
Index (I3PW). These two registers may be loaded or reset simultaneously or
independently. Write Offset provides a mechanism to offset read index
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 33
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registers from the Write Index by a fixed distance. Increment and Decrement
apply to both write registers so that the offset is maintained. The two Read
Index registers may be independently reset or aligned to the Write Offset.
Related Assembly Operations:
Syntax Al lowed values for arguments
memwrite no arguments
memread1 no arguments
memread2 no arguments
table 17
Each index has separate controls and may be incremented, decremented, or
held after each read or write operat ion.
Syntax Al lowed values for arguments
setindex <value> <value>: 0-31 or 0x0-0x1f
setindex <valuew>, <value1>, <value2> <valuew>: 0-15 or 0x0-0xf
<value1>: 0-15 or 0x0-0xf
<value2>: 0-15 or 0x0-0xf
indexmode <m0>, <mw>, <m1>, <m2> <m0>: none, reset
<mw>: none, resetoffset, resetall
<m1>: none, reset, align
<m2>: none reset, align
indexdirect <d0>, <dw>, <d1>, <d2>
<index> <d0>: none, inc, dec
<dw>: none, inc, dec, rev
<d1>: none, inc, dec, rev
<d2>: none, inc, dec, rev
<index>: readwrite0, write, read1,
read2, all3port
table 18
The setindex operation sets the index to a specified value.
The indexmode operation resets or aligns the index values.
The indexdirect operation controls whether the index values are incremented,
decremented, or held after access.
Smart Indexing
Smart indexing operates multiple memo ry addresses to be accessed. This is
particularly useful when the data is symmetrical. Refer to the DCT and
symmetric filter RAD Notes for detailed examples.
Symmetrical coefficients are accessed b y providin g the Write Offset from the
center of the data and aligning both Read Indices to the Write Offset. The
Read Indices may be separated by a dummy read. Additional simultaneous
reads with o ne index i ncrementing an d the other decrementing allows for
addition or subtraction of data that uses the same or inverted coefficients.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
34 March 1997 Infinite Technology Corporation
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Each index has separate direction controls. Each index may increment or
decrement, an d/or ch ange its di rection. Th e change in each index register’s
address t akes place after a read or write operatio n on the associated port.
3-port Memory Index Pointers
write indexwrite offset
read1 read2
offset
figure 20
Smart indexing is ideal for Filter, and DCT applications where pieces of data
are taken from equal distance away from the center of symmetrical data.
The smart index method used in the 3-port Memory allows symmetrical data to
be multiplied in half the number of cycles that would have normally been
required. Data from both sides can be added together and then multiplied with
the common co efficient.
For example, a 6-tap filter which would normally take 6 multiplies and 7
cycles, can be implemented with a single MacroSequencer and only requires 3
cycles to complete the calculation. An 8-point DCT which normally requires
64 multiplies and 65 cycles can be implemented with a single MacroSequencer
and o nly requires 3 2 clock cycles to co mpl ete the calcu l ation.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 35
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Output Selector The Output Selector controls the state of output registers OutRegA and
OutRegB and controls the stat e of the MSnI/O[15:0] bus pins.
Output Selector
Input
Selector
OutRegA
Logic Unit
Adder
Shifter
Input
Selector
MS
n
I/O[15:0]
OutRegB
Register
InRegB
16
16
16
16
16
16 16
16
LIW[18:17]
LIW[21:19]
figure 21
The Output Selector multiplexes five 16-bit bu ses and places the results on two
16-bit output registers which drive two on-chip buses and the MacroSequencer
I/O pins. The Output registers may be held for
multiple cycles.
Inputs
The out put selector receives inputs from the:
• Adder,
• Logic Unit,
• Shifter,
• InRegB, and
• MacroSeq uencer I/O MSnI/O[15:0] pins.
Outputs
The output selector places outputs for OutRegA and Ou tRegB.
Output Register A, OutRegA, is available to the:
• Input Selector,
• Write port of the 1-port memory,
• MSnI/O pins, and
• Busn input from MacroSequencer(n) OutRegA.
Data placed on busn is availabl e to the o t her three Macro Sequencers.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
36 March 1997 Infinite Technology Corporation
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Output Register B, OutRegB, is available to the:
• Write port of the 3-port memory,
• Input Selector,
• MAC, and
• Paired MacroSequencer bus MSPair(nm) where:
− OutRegB from MacroSequencer0 is the source for MSPair01.
− OutRegB from MacroSequencer1 is the source for MSPair10.
− OutRegB from MacroSequencer2 is the source for MSPair23.
− OutRegB from MacroSequencer3 is the source for MSPair32.
Related Assembly Operations:
Syntax Allo wed values for ar guments
move no arguments; moves th e val ue of
InRegB to OutRegB
in pins, outregb no arguments; moves the value of the
MSnI/O pins to OutRegB
table 19
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 37
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I/O Interface Th e I/ O Interface selection for each MacroSequ encer determines:
• Input source for data busn and
• The output enable configuration.
MS
n
OE
oepla[
n
]
'1'
OE
MS
n
I/O[15:0]
Port
config
bit[7:6]
config
bit[4]
bus
n
16
16
1
1
16
MS
n
I/O[15:0]
MacroSequencer I/O Interface
To Output Selector
OutRegA
config
bit[8]
(Output)
(Input)
16
16
figure 22
The I/O Interface diagram for the o utput enable circui try represents the
equivalent of the output enable selection for configuration bits 6, 7, and 8 in
the normal operating mode. These MacroSequencer configuration bit
selections are made in the RADware design tools.
Busn Selection
The input data on busn is selected from th e MSnI/O[15:0] pins or the OutRegA
output of MacroSequencer(n) by configuration bit 4.
When Macro Sequencer(n)’s associated b usn is connected to the OutRegA
signal, the MacroSequencer still has input access to the MSnI/O pins via the
Output Selector.
Output Enable Control
Output Enable to the MSnI/O pins is controlled by configuration bit selections.
Inputs to the output enable control circuitry include the MSnOE pin for
MacroSequencer(n) and the oepla[n] signal.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
38 March 1997 Infinite Technology Corporation
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Macr oSequencer Datapath Controller
The MacroSequencer Datapath Controller contains and executes one of two
sequences of Long Instruction Words (LIWs) that may be configured into
instruction memory. The Datapath Controller generates LIW bits which
control the MacroSequencer Arithmetic Datapath. It also generates the values
for the 1-port and 3-port index registers.
The controller accepts control si gnals from the P LA PLACtrl(n)[1:0] signals or
external MS nCTRL pins which initiates one of two possible LIW sequences. It
outputs Send and Await status signals to the PLA and to external MSnSEND
and MSnAWAIT pins.
The Datapath Controller operation is determined by MacroSequencer the
contents of its LIW register and the two control signals.
Components Each MacroS equencer Controller contains t he following elements:
• Program Counter (PC),
• LIW Register which holds the currentl y executing LIW,
• 32 by 48-bit reprogrammable Instruction Memory,
• Two loop counters: Counter0 and Counter1,
• Return Stack for ‘calls’ which holds 4 return addresses, and
• Index Registers for the 1-port and 3-port memories.
Inputs include:
• Controln signals for setting one of the two sequences, or issuing Run and
Continue commands and
• Adder status bits: Equal, Overflow, and Sign.
Outputs include:
• LIW instruction bits,
• 1-port and 3-port memory addresses, and
• Two single-bit Send and Await Status signals
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 39
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The Datapath Controller is shown in the following diagram.
MacroSequencern Datapath Controller
Stack
Counter 0
Counter 1
Sequence
Controller
LIW Memory
32 x 48
LIW Register
I1p
I3pR1
I3pR2
I3pW
1-Port
Address
3-Port Read1
Address
3-Port Read2
Address
3-Port Write
Address
LIW Control Bits
3
2
2
Control Signals
Adder Status
Status
Signals
I3pWO
PC
9
5
1
4
4
4
5
MSnCTRL
PLACtrln
Configuration
Bit 5
Register
2
2Control
7 17
55
2
52
2
16
16
16
16
11
4
4
48 42
22
48
figure 23
The D atapa th Controller is a synchronous pipelined st ructure . A 48-bit instruc tion is
fetc hed f rom ins truction m e m ory at the addre ss g ene rate d by the prog ra m counter
and registered into the LIW register in one clock cycle. The actions occurring during
the next clock cycle are determined by the contents of the LIW register from the
previous clock cycle. Meanwhile, the next instruction is being read from memory
and the contents of the LIW register is changed for the next clock cycle so that
instructions are executed every clock cycle.
Because of the synchr onous pipelined structure, the Datapath Controller will
always execute the next i nstructi on before branch o perations are executed.
The program counter may be initiated by control signals. It increments or
branches to the address of the LIW to be executed n ext.
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The Adder status signals, Stack and two Counter elements in the Datapath
Controller support the program counter. Their support roles are:
• The Adder status bits report the value of the Equal, Overflow, and Sign, for
use in branch operations.
• The Stack contains return addr esses.
• Counter0 a nd Counter 1 hold down loop- counter va lues f or br anch ope rations .
The five index registers hold write, read, and write offset addresses for the 1-
port and 3-port memories. Th e write offset register (I3PWO) is used for
alignment of the two read index registers, and it holds the value of an offset
distance from the 3-port memory write index for the two read indices.
Each of the Datapa th Controller Block Diagra m e lem ents is desc ribed in deta il.
Control Signals Th e MSn Direct Control and Status pins shown in the Simplified RAD5A4
Control and Data F l ow diagram (figure 8) are the control and status in terface
signals which conn ect directly between the pins and each M acroSequencer.
The direct control si gnals are MSnCTRL[1:0], and MSnOE, an d the di rect
status si gnals are MSnAWAIT and M SnSEND. These are listed in the tabl e of
MacroSeq uencer Control Interface Sign als (table 6). Alternatively, the
MacroSequencers may use contro l signals from the Du al PLA. The Dual PLA
also receives the MacroSequencer stat us signals.
Two Control si gnals for each Macro Sequencer specify one of four control
commands. They are selected from either t he MSnCTRL[1:0] pins or from the
two PLACtrln signals.
The control state of the MacroSequencer on the next clock cycle is determined by the
state of the abov e c om ponents a nd the st ate of the se PL AC trln[1:0] s i gn a ls .
The four control states includ e:
SetSequence0
SetSequence0 sets and holds the Program Counter to ‘0’ and resets the Send
and Await state registers to ‘0’ without initializing any other registers in the
MacroSequencer. Two clock cycles after the SetSequence0 is received, th e
Datapath Controller will execute LIW 0 every clock cycle. The Program
Counter does not change until a Run or Continue command is received.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
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SetSequence2
SetSequence2 sets and holds the Program Counter to ‘2’ and resets the Send
and Await state registers to ‘0’ without initializing any other registers in the
MacroSequencer. Two clock cycles after the SetSequence2 is received, th e
Datapath Controller will execute LIW 2 every clock cycle. The Program
Counter does not change until a Run or Continue command is received.
Run
Run permits normal operation of the Datapath Controller. The Run command
should be asserted every cycle during normal operation except when resetting
the Send and/or Await flags, or initiating an LIW sequence with SetSequence0
or SetSequence2.
Continue
Continue resets both the Send and Await status signals and permits normal
operation. If the Await State was asserted, the Program Counter will resume
normal operation on the next cycle.
If an await operation is encountered while the Continue command is in effect,
the Continue command will apply, and the await operation will not halt the
Program Counter, nor will the Await status register be set to a ‘1’. Therefore,
the Continue command should be changed to a Run command after two clock
cycles. If a send operation is encountered while the Continue command is in
effect, the Continue command will apply, and the Send status register will not
be set to a ‘1’.
About the Commands
The fo llowing table summarizes the four command options for Controln[1:0]
which may be from PLACtrln or from MSnCTRL pins:
Controln
[1:0] Command Description
0 0 Run Normal Operating Condition
0 1 Continue Reset Send and Await registers.
1 0 SetSequence0 The Program Counter is set to ‘0’.
Resets the Send and Await registers.
This must be asserted for at least two cycles.
1 1 SetSequence2 The Program Counter is set to ‘2’.
Resets the Send and Await registers.
This must be asserted for at least two cycles.
table 20
By allowing two sequence starting point s, each MacroS equencer can be
programmed to perform two algorithms without reloading.
The two PLACtrln signals are synchroni zed within t he MacroSequencer. The
two MSnCTRL pin signals are not synchronized within the MacroSequencer;
therefore, consideration for timing requirements is necessary.
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Architecture Description Reconfigurable Arithmetic Datapath
42 March 1997 Infinite Technology Corporation
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Status Signals T here are two single-bit registered status signals that notify the external pins and the
PLA when the MacroSequencer has reached a predetermined point in its sequence of
operations. They are the Await and Send status signals. Both of the Status signals
and their registers are reset to ‘0’ in any of these conditions:
• During Power On Reset,
• Active configuration of any part of the RAD5A4,
• During Control States: SetSequence0, SetSequence2, or Continue.
Related Assembly Operations:
Syntax Allo wed values for ar guments
await no arguments
send no arguments
table 21
When an await operation is asserted from the LIW register, the MacroSequencer
executes th e next inst ruction , and rep eat s execution of that n ext instruction
until a Con tinue or SetSequence command is received. The await instruction
stops the Program Counter from continuing to change and sets the Await status
signal and register to ‘1’. A Continue command resets the Await status signal
and register to ‘0’ allowing the Program Counter to resume.
A send operation only sets the Send status signal and register to ‘1’. Execution
of the sequence continues. The Program Counter is not stopped. A Continue
comm and w ill re set the Send sta tus signal a nd registe r to ‘0’.
Statu s signals are resynchronized in the Dual PLA with the PLACLK.
Adder Status Signals
The A dde r sta tus bits, Equa l, Ove rf low , and Sig n are provide d for
conditional jum ps.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 43
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Program Counter The Program Counter is a 5-bit register which changes state based upon a
number of conditions. The program counter may be incremented, loaded
directly, or set to ‘0’ or ‘2’.
The three kinds of LIW operations which affect the MacroSequencer Program
Counter explicitly are:
• Branch operations,
• SetSequence0 and SetSequence2 commands, and
• Await operation.
The Program Counter is set to zero ‘0’:
• During power-on Reset,
• During Active configuration of any part of the RAD5A4 ,
• During the SetSequence0 command,
• When the Program Counter reaches the valu e ‘31’, and the previou s LIW d id
not contain a branch to another address, or
• Upon the execution of a branch operation to address ‘0’.
Control Signal Effects:
The Controln[1:0] signals are used to reset the program counter to either
‘0’ or ‘2 ’ at any time with either SetSequence0 or SetSequence2 respect ively.
A Run command begins and maintains execution by the program counter
according to the LIW.
A Continue command resumes the program counter operation after an Await
state and resets the Send and Await registers to ‘0’ on the next rising clock
edge. A Continue command after a Send operation resets the Send register to
‘0’ on the next rising clock edge.
Status Signal Effects:
The Await status register is set to ‘1’ and the Program Counter stops on the
next clock cycle after an await operation is encountered. A Continue command
resets the Send and Await registers and permits the Program Counter to
resume.
The Send status register i s set to ‘1’ o n the next clock cycle after a send
operation. A Continue command is required to reset the Send register. A Send
operation does not effect the Program Counter.
RAD5A4
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44 March 1997 Infinite Technology Corporation
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Branch Operations
The LIW register may contain one Branch operation at a time. Conditional
Branches should not be performed during the SetSequence commands to insure
predictable conditions.
Branch Operation Assembly Instruction Result in the Program Counter
Unconditional branch jump <address> Program Counter is set to <address>.
Branch on loop Counter0
or loop Counter1 not
equal to ‘0’
jumpcounter0 <address>
jumpcounter1 <address> Program Counter is set to <address> if the
respective loop counter has a non-zero value.
The respective loop counter will then be
decremented in the next clock cycle.
Branch on an Adder
status condition: Equal,
Overflow, Sign
jumpequal <address>
jumpoverflow <address>
jumpsign <add r ess>
Program Counter is set to <address> if the Adder
status bits agree with the branch cond ition .
Call subroutine call <address> The current address plus ‘1’ in the Program
Counter is pushed onto the Stack. The contents
of the Program Counter on the next clock cycle
will be set to the address in the LIW.
Return from subroutine
operation return The address from the top of the Stack is popped
into the Program Counter.
table 22
Long Instruction Word Register
The purpos e of the 48-bit LIW Re g i st e r is to hold the conte nts of the
current LIW to be executed. Its bits are directly connected to elements
in the datapa th.
The LIW register is load ed with the contents of the instruction memory point ed
to by the Program Counter before the Program Counter is updated. The effect
of that i nstruction is calculated during the next clock cycle.
Instruction Memory
The Instruction memory consists of thirty-two words of 48-bit RAM configured
according to th e MacroSequencer assembly language program.
The Instruction memory is not initialized during Power On Reset. For
reliability, the LIW RAM must be configured before MacroSequencer
execution begins.
Bit fields in the LIW Registers control datapath operations and program flow.
They are described in detail in the LIW Appendix.
Counter0 and Counter1
There are two 5-bit loop counters labeled Counter0 and Counter1. Both loop
counters are filled with ‘0’s during Power On Reset and active configuration of
any component in the RAD5A4.
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
Infinite Technology Corporation March 1997 45
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Counter0 and Counter1 may be loaded by the setcounter0 and setcounter1
operations respectively. The jumpcounter0 and jumpcounter1 operations will
decrement the respective counter on the next clock cycle until the Counter
value reaches ‘0’.
The SetSequence0 and SetSequence2 control signals do not alter or reset the
loop counters. Therefore, the counters should be initialized with setcounter0
and setcounter1 operations before they are referenced in the program.
Related Assembly Operations:
Syntax Allo wed values for ar guments
jumpcounter0 <address> <address>: 0-31 or 0x0-0x1f or label
jumpcounter1 <address> <address>: 0-31 or 0x0-0x1f or label
setcounter0 <value> <value>: 0-31 or 0x0-0x1f
setcounter1 <value> <value>: 0-31 or 0x0-0x1f
table 23
Stack The Stack holds return addresses. It contains four 5-bit registers and a 2-bit
stack pointer. After Power On Reset or the active configuration of any
component in the RAD5A4, the stack pointer and all of the 5-bit registers are
initialized to ‘0’s.
A call performs an unconditional jump after executing the next instruction, and
pushes the return address of the second instruction following the call
into the Stack.
A return operation pops the return address from the Stack and into the Program
Counter.
The call and return operations will repeat and corrupt the Stack if these
operati ons are in t he next LIW after an await operation becau se t he program
counter is held on that address, and the MacroSequencer repeats execution of
the LIW in that address.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
46 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
Related Assembly Operations:
Syntax Allo wed values for ar guments
call <address> <address>: 0-31 or 0x0-0x1f or label
return no arguments
table 24
Index Registers The LIW Register controls the five index registers which are used for data memory
addres s ge nera tion. One inde x r egi ster holds the 1- port m em ory a ddres s. T he other
four inde x re gis ter s hold 3-port m e m ory addr ess infor m ation.
During Power On Reset or the active configuration of any component in the
RAD5A4, all index register bits are reset t o ‘0’s. The control states, Run,
Continue, SetSequence0 or SetSequence2 do not affect the index registers.
During each clock cycle that a memory access is performed, that memory
address can be loaded, in cremented, decremented or held depending upon the
control b it settings in each index register.
Related Assembly Operations:
Syntax Allo wed values for ar guments
setindex <value> <value>: 0-31 or 0x0-0x1f
setindex <valuew>, <value1>, <value2> <valuew>: 0-15 or 0x0-0xf
<value1>: 0-15 or 0x0-0xf
<value2>: 0-15 or 0x0-0xf
indexmode <m0>, <mw>, <m1>, <m2> <m0>: none, reset
<mw>: none, resetoffset, resetall
<m1>: none, reset, align
<m2>: none reset, align
indexdirect <d0>, <dw>, <d1>, <d2>
<index> <d0>: none, inc, dec
<dw>: none, inc, dec, rev
<d1>: none, inc, dec, rev
<d2>: none, inc, dec, rev
<index>: readwrite0, write, read1,
read2, all3port
table 25
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
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Index Register Components
Each index register contains an address register and a control regi st er that
provide:
• Index Control bits which include:
• Two index direction bits
• A load enable bit
• Index memory address bits where:
• The 1-port Index address is five bits.
• The 3-port Read1 Index address is four bits.
• The 3-port Read2 Index address is four bits.
• The 3-port Write Offset address is four bits.
• The 3-port Write Index address is four bits.
The 3-port read index control registers also contain a load-write-offset (ldwo)
bit, which enables loading from the write offset register.
The index direction can be set by the assembly language to:
• increment (count_up=1 and count_down=0),
• decrement (count_up=0 and count_down=1), or
• hold its value (count_up=0 and count_down=0).
The effects of the control bits on the address bits are set by the software and are
listed in this table:
Index Control Bits
Count_
up Count_
down Load
Enable
(lden)
Load Write
Offset (ldwo)
Effect
1-por t Index
X X 1 n/a allows a value to be loaded into
address[4:0]
0 0 0 n/a value of address[4:0] is held
0 1 0 n/a post-decrements address[4:0]
1 0 0 n/a post-increments address[4:0]
3-por t Read1 and Read2 Inde x, 3-por t Write Offset, and 3-port Wri te Index
X X 1 0 allows a value to be loaded into
address[3:0]
0 0 0 0 value of address[3:0] is held
0 1 0 0 post-decrements address[3:0]
1 0 0 0 post-increments address[3:0]
X X X 1 Address is set to the value of the Write
Index address less the Write Offset
address
table 26
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The Index Register bits are shown in this table:
Index Register Control Register Bits
Description
Nam e count_
up count_
down Load
Enable
(lden)
Load Write
Offset
(ldwo)
Address
Register
Bits
1-port Index I1p √ √ √ adr[4:0]
3-port Read1 Index I3pR1 √ √ √ √ adr[3:0]
3-port Read2 Index I3pR2 √ √ √ √ adr[3:0]
3-port Write Offset I3pWO √ √ √ adr[3:0]
3-port Write Index I3pW √ √ √ adr[3:0]
table 27
Macr oSequencer Configurati on Bits
In each MacroSequencer there are nine programmable configurat i on bit s. They
are listed in the table below. The three signed/unsigned bits are set with
directives when programming the MacroSequencer. The other selecti ons are
made in the RADware design tools.
MacroSequencer Configuration Bits
Bit Functional
Block Function If Bit = 0 If Bit = 1
0 Multiplier Mult operand A sign A is unsigned. A is signed.
1 Multiplier Mult operand B sign B is unsigned. B is signed.
2 Adder Signed / Unsigned Bit Unsigned Add Signed Add
3 Adder 32/16 Bit 16 bit Datapath mode 32 bit Datapath mode
4 Data Bus
Connections Sel ect OutRegA or
MSnI/O pins fo r
MacroSequencer busn
inputs
Busn inputs are from
OutRegA of
MacroSequencer(n)
Busn inputs are from
MSnI/O pins
5 Datapath
Controller Control[1:0] source select Control[1:0] from
MSnCTRL[1:0] pin s Control[1:0] from
PLA0 CtrlPLAn[1:0]
7:6 I/O Interface Outp ut Enabl e S elect or ‘1’ [00]: OE is from MSnOE pin
[01]: OE is from PLA
[1x]: OE is ‘1’
8 I/O Interface OE Po larity Select OE = OE OE = OE
‘1’ - logical one, ‘0’ - logical zero table 28
The configuration bits are configured with the instruction memory, where bits 0
through 8 of the 16-bit program data word are the nine configuration bits listed
above. They are placed automatically by the RADware design t ools.
RAD5A4
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RAD5A4 Dual PLA Description
The RAD5A4 Dual PLA contains two in-circuit programmable, 32 input by 34
product term PLAs. PLA0 may serve as a state machine to coordinate the
MacroSequencer array operation with external devices. PLA1 may be used for
random interface logic. The Dual PLA may perform peripheral logic or control
functions based upon the state of BUS4IN, PLAIN and PLAI/O bus states and
the Control bus.
16
8 8 8
Input Selector
AND Array 0
34 x 32
Fixed OR 0
Control OR
Control Registers
8
Input Selector
Output Registers
PLAI/O Buffers
PLAI/O[7:0]
Send Status
BUS4IN[15:0]
Dual PLA Block Diagram
Await Status
PLAI/O[7:0]
OutReg
PLAIN[7:0]
PT0
C0
CtrlReg
14 8
Output OR
FO1
C1
oepla[1]
oepla[3]
oepla[0]
oepla[2]
8
8
8
4
4
16
Minterm Generater
3264
AND Array 1
34 x 32
Fixed OR 1
Minterm Generat er
3264
FO0 PLACtrl0[1:0]
PT1
Register
PLA0
PLA1
OutCom
16A
B
16
16A
B
mt
mt
PLACtrl1[1:0]
PLACtrl2[1:0]
PLACtrl3[1:0]
(Outputs)
(Inputs)
figure 24
The Dual PLA control functions which may be used by any or all of the
MacroSequencers in cl ude:
• Registered control outputs, CtrlReg[7:0], for:
− Initiation of LIW sequences and
− Control response to Send and Await status signals.
• Combinatorial outputs, oepla[3:0] , used to generate Output Enable signals
for the MacroSequencers. Th e oepla[3:0] signals are generated from
individual product terms.
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The CtrlReg[ 7:0] signals may be used in pairs by each of the MacroSequencers
where:
• CtrlReg[1:0] are avai l able as Control0[ 1:0] for MacroSequ encer0.
• CtrlReg[3:2] are avai l able as Control1[ 1:0] for MacroSequ encer1.
• CtrlReg[5:4] are avai l able as Control2[ 1:0] for MacroSequ encer2.
• CtrlReg[7:6] are avai l able as Control3[ 1:0] for MacroSequ encer3.
The R A D5A 4 Dua l PLA and Ma croSe quenc ers should be pr ogra m m ed a t pow er up
and m ay be dynamica lly rec onf igure d at any tim e during ope ration. A c tive
Config uration of the R A D5A 4 forc es a ll reg iste rs in e ve ry com ponent of the
RAD5A 4, including the Dual PLA output and c ontrol reg isters to be initia lized.
Outputs
The PLA0 produces eight CtrlReg output s that can be used as MacroSequencer
control signals where t wo si gnals are availabl e for each MacroSequencer to use
as Control signals. They are also available as feedbacks to both PLA0 and
PLA1.
The CtrlReg[7:0] signals are useful in multi-chip array processor applications
where system control signals are transmitted to each RAD5A4.
PLA1 produces combinatorial or registered I/O outputs for the PLAI/O[7:0]
pins. The fourteen Fixed OR outputs(FO1) from PLA1 are also available to the
Control OR array in the PLA0.
The PLA1 registers are available for feedback to both PLA Input Selectors.
The PLAI/O signal s are useful for single ch ip appl ications requirin g a few
interface/handshake signals, and th ey are useful in multi-chip array processor
application s where system control signals are transmitted to each d evice.
Components
PLA0 consists of :
• Input Selector
• Minterm Generator to the AND Array0
• 34 product terms by 32 inputs AND Array0
• Fixed OR array (Fixed OR0)
• 8 x 16 Programmable OR array (Control OR)
• 8 registers (Contro l Register)
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PLA1 consists of:
• Input Selectors
• Minterm Generator to the AND Array1
• 34 product terms by 32 inputs AND Array1
• 14 Fixed OR nodes with 1 to 4 product terms per node (Fixed OR1)
• 8 x 14 Programmable OR array (Output OR)
• 8 registers (Outp ut Registers)
• Choice of 8 registers or combinatorial outputs (PLAI/O Buffers)
Each element in the RAD5A4 Dual PLA is described in detail.
PLA Input Selectors
The Input Selectors for PLA0 and PLA1 are identical and accept inputs from:
• The Send and Await status signals from each MacroSequencer which are
synchronized nd registered in the Input Selector circuits.
• BUS4IN[15:0] input pins,
• PLAI/O[7:0] pins,
• PLAIN[7:0] pins,
• CtrlReg[7:0] registered signals from the P LA0, and
• OutReg[7:0] registered signals from the PLA1.
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There are two groups of generated signals A[15:0] and B[15:0] which are
output by the PLA Input Selector circuit.
CtrlReg[6,4,2,0]
OutReg[6,4,2,0]
PLA Configuration Bit
(CtrlReg or OutReg)
PLAI/O[6,4,2,0]
Await[3:0]
Register
PLACLK
A[3:0]
CtrlReg[7,5,3,1]
OutReg[7,5,3,1] B[3:0]
A[7:4]
PLA Configuration Bit
(PLAI/O or Await / Send)
PLAI/O[7,5,3,1]
Send[3:0] B[7:4]
BUS4IN[6,4,2,0] A[11:8]
PLAIN[6,4,2,0]
BUS4IN[7,5,3,1]
PLA Input Selector
4
4
4
4
4
B[11:8]
4
PLAIN[7,5,3,1]
A[15:12]
4
B[15:12]
4
figure 25
PLA Configuration bits are set within the RADware design tools when the
Dual PLA is programmed.
RAD5A4
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Minterm Generator
The Minterm generator provides the 16 sets of four minterms of the two
adjacent numbered inputs (A[i] and B[i]) from the Input Selectors to the
AND planes.
There are two 16-bit parallel inputs to the Minterm Generator known as
A[15:0] and B[15:0].
Adjacent inputs, A[i] and B[i], are paired to generate the four possible
minterms for use in the AND array. Instead of routing the conven tional
inverted and non-inverted input signals to the AND array, the four minterms of
the two inputs are routed. The number of lines through the array and the
number of memory signals in the AND array are four per two inputs for each
product term which is the same as a conventional AND array. From each input
pair, A[i] and B[i], minterms are generated as inputs to the AND array.
A[i] & B[i] A[i] & B[i] A[i] & B[i] A[i] & B[i]
Each pair of inputs to the Minterm generator, A[i] and B[i], generate the
following minterm signals for i=0, ..., 15:
• mt[4*i] = A[i] & B[i]
• mt[4*i+1] = A[i] & B[i]
• mt[4*i+2] = A[i] & B[i]
• mt[4*i+3] = A[i] & B[i]
The minterm results, mt[ 63:0] are availabl e to the AND planes.
AND Arrays Each PLA generates 34 product terms of 32 inputs arranged as 16 pairs (A[i],
B[i] ) of signals.
AND array inputs are from the Minterm Generator. The Minterm Generator
translates 16 pairs of A[i] and B[i] signals into 16 groups of four minterms
labeled mt[4i+3:4i]. These 64 minterm signals are then transmitted to each of
the 34 product terms within the AND array.
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Each product term consists of 16 function generators which use four of the
minterm signals to generate any function of the two A[i] and B[i] signals. The
function generator outputs, f(0) to f(15) are the inputs to a 16-input AND gate.
Each 16-input AND gate outputs one of the product term signals.
mt[3:0] mt[7:4] mt[63:60]
. . .
f(0) f(1) f(15) 16-input
AND Gate PT
Product Terms
Function
Generator
Function
Generator
Function
Generator
16
figure 26
AND Array Function Gene rator
Configurat i on of four PLA configuration bits, s0, s1, s2, and s3, within each
function generator d et ermines the functions of each A[i] , B[i] input pair for the
product terms. The relation between the PLA configuration bits, input pairs
and AND-gate inputs are shown in this diagram:
s0
s1
s2
s3
AB AB AB AB
AND Array
Inputs
Function Generator
figure 27
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Memory selections for the sixteen possible input functions are shown in
this truth table:
AB
si0
AB
si1
AB
si2
AB
si3
Resulting Function
0 0 0 0 0, the constant function
0 0 0 1 Ai & Bi
0 0 1 0 Ai & !Bi
0 0 1 1 Ai
0 1 0 0 !Ai & Bi
0 1 0 1 Bi
0 1 1 0
Ai xor Bi
0 1 1 1
Ai or Bi
1 0 0 0 !Ai & !Bi
1 0 0 1
Ai xnor Bi
1 0 1 0 !Bi
1 0 1 1
Ai or !Bi
1 1 0 0 !Ai
1 1 0 1
!Ai or Bi
1 1 1 0
!Ai or !Bi
1 1 1 1 1, the constant function
table 29
Bolded functions are not normally available in PLA structures. The function
generators allow these extra six functions.
The logic formula for product term PT[i] is:
PT[ i] = f[i, 0] & f[i, 1] & f[i,2] & f[i,3]
& f[i ,4] & f[i,5] & f[i,6] & f[i,7]
& f[i,8] & f[i,9] f[i,10] & f[i,11]
& f[i,12] & f[i,13] & f[i,14] & f[i,15]
where f[i,j] represents the generated function signal for the PT[i] and input pair
A[j], B[j] .
Example
The RAD5A4 minterm generator and enhanced product term allow a single
product to cover the same Boolean function that several conventional product
terms would require. Consider the comparison:
A[7:0] = B[7:0]
between the two 8-bit vectors A and B. This one equation requires 256
conventional product terms; but with the RAD5A4 it will fit in exactly one.
This is accomplished by implementing !(A0 XOR B0) . . . !(A 7 XOR B7) directly .
RAD5A4
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56 March 1997 Infinite Technology Corporation
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Fixed OR Arrays Fixed OR 0
The AND Array 0 outputs are summed in sets of four successive signals
to form eight 4-product term signals FO0[7:0] as shown here:
Fixed OR
0
8 x 4
32 8
FO0
Fixed OR 0
PT0
figure 28
where one of the eight Fixed OR 1 outputs is shown here:
d
Fixed OR
Outputs
Fixed OR 0
cba
figure 29
RAD5A4
Reconfigurable Arithmetic Datapath Architecture Description
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Fixed OR 1
The AND Array 1 outputs are summed in sets of one, two and four successive
signals to form fourteen, fixed OR term signals FO1 [13:0]. The AND Array 1
outputs are summed as follows:
• 4 sets of four AND array
• 6 sets of two AND array outputs
• 4 sets of single AND array outputs
Fixed OR
1
4 x 4
6 x 2
4 x 1
32 14
FO1
Fixed OR 1
PT1
figure 30
The detailed product terms are shown in this diagram.
Fixed OR
Outputs
Fixed OR 1
AND Array
Outputs
PT
31
PT
30
FO1
13
FO1
12
FO1
11
FO1
10
FO1
9
FO1
8
FO1
7
FO1
6
FO1
5
FO1
4
FO1
3
FO1
2
FO1
1
FO1
0
PT
29
PT
28
PT
27
PT
26
PT
25
PT
24
PT
23
PT
22
PT
21
PT
20
PT
19
PT
18
PT
17
PT
16
PT
15
PT
14
PT
13
PT
12
PT
11
PT
10
PT
9
PT
8
PT
7
PT
6
PT
5
PT
4
PT
3
PT
2
PT
1
PT
0
figure 31
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
58 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
Control OR Array The Control OR array is a programmable OR array with 22 inputs that produce
eight regist ered in th e Control Register to form the Macro Sequencer Control
signals which are available as inputs to the PLA Input Selector.
The inputs for the Control OR array include FO0[7:0] and FO1[13:0].
Control OR
FO0[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
FO1[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
C0[0] [1] [2] [3] [4] [5] [6] [7]
AND ARRAY 1
AND ARRAY 0
figure 32
The vertical li nes in the above di agram represent a pro grammable OR gate, and
the horizon t al lines represent fixed OR gates. The boxes at th e intersections
show which of the fixed OR terms may be ORed together.
RAD5A4
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Phone: 972-437-7800
Each OR gate input is determined by PLA configuration bits as shown in
this schematic:
s0,j
s1,j
s16,j
FO
0
FO
1
FO
15
C0[i]
Control OR Simplified Schematic
. . .
. . .
. . .
16-input
OR Gate
figure 33
The formula for each Control OR output, C0[ i ] is:
C0[i] = FO1[0] AND s[0,i] OR
FO1[1] AND s[1,i] OR
FO1[2] AND s[2,i] OR
FO1[3] AND s[3,i] OR
FO1[4] AND s[4,i] OR
FO1[5] AND s[5,i] OR
FO1[6] AND s[6,i] OR
FO1[7] AND s[7,i] OR
FO1[8] AND s[8,i] OR
FO1[9] AND s[9,i] OR
FO1[10] AND s[10,i] OR
FO1[11] AND s[11,i] OR
FO1[12] AND s[12,i] OR
FO1[13] AND s[13,i] OR
FO0[j+2] AND s[14,j+2] OR
FO0[j] AND s[15,j] OR
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
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CtrlReg Register The CtrlReg Registers hold the MacroSequencer Control signals produced by
the Contro l OR array.
CtrlReg
8 8
CtrlReg
CtrlReg Register
C0
PLACLK
Register
figure 34
RAD5A4
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Phone: 972-437-7800
Output OR Array The Output OR array is a programmable OR array with fourteen inputs from
the Fixed OR 1 array producing eight combinatorial OutCom[7:0] signals
which may be registered. The Output Registers are available as inputs to the
PLA Input Selector. Both the combinatorial outputs and the registered Outputs
are available t o the PLAI/O Buffers.
The inputs for the Output OR array are the Fixed OR 1 signals which are
labeled FO1. All PLA1 fixed OR terms are available to every programmable
OR term.
Output OR
FO1[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
C1[0] [1] [2] [3] [4] [5] [6] [7]
figure 35
The vertical li nes in the above di agram represent a pro grammable OR gate, and
the horizon t al lines represent fixed OR gates. The boxes at th e intersections
show which of the fixed OR terms may be ORed together.
RAD5A4
Architecture Description Reconfigurable Arithmetic Datapath
62 March 1997 Infinite Technology Corporation
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Each OR gate input is determined by PLA configuration bits as shown in
this schematic:
s0,j
s1,j
s16,j
FO1
0
FO1
1
FO1
13
C1[i]
Output OR Simplified Schematic
. . .
. . .
. . .
14-input
OR Gate
figure 36
The formula for each Output OR outp ut, C1[i] is:
C1[i] = FO1[0] AND s[0,i] OR
FO1[1] AND s[1,i] OR
FO1[2] AND s[2,i] OR
FO1[3] AND s[3,i] OR
FO1[4] AND s[4,i] OR
FO1[5] AND s[5,i] OR
FO1[6] AND s[6,i] OR
FO1[7] AND s[7,i] OR
FO1[8] AND s[8,i] OR
FO1[9] AND s[9,i] OR
FO1[10] AND s[10,i] OR
FO1[11] AND s[11,i] OR
FO1[12] AND s[12,i] OR
FO1[13] AND s[13,i] OR
RAD5A4
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Output Register Th e eight Output Regist ers are used for holding t he signals produ ced by the
Output OR array. The registered signals, OutR eg[7:0], are avail able to the
Input Selectors for both PLA0 and PLA1.
OutReg
8 8
OutReg
OutReg Register
C1
PLACLK
Register
figure 37
PLAI/O Buffers The eight I/O bu ffers select eit her the combinatorial outputs or the registered
outputs from the Output OR array for the PLAI/O pins. The simple schematic
for one buffer is shown here:
PLAI/O
Output
PLAI/O Buffers
Registered C1
OutReg
Combinatorial C1
OutCom
8
8
8
PLA Config. Bits
figure 38
Exactly one config uration bit contr ols w hether com binatoria l or reg iste red outputs
are selected for all of the eight PLAI/O pins. One configuration bit for each pin
determines whether each PLAI/O pin is always an output or always an input.
RAD5A4
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RAD5A4 Configuration
This chapter offers directions for RAD5A4 device configuration of the thirteen
memories in the RAD5A4 that can be programmed. The RAD5A4 is
configured by loading the configuration file into the device.
RAD5A4 Configurable Memories
There are three memories in each of the four MacroSequen cers and a Dual PLA
configurat i on memory. With in each of th e MacroSequencers, there is a:
• MacroSequencer configuration memory,
• 1-port data memory, and
• 3-port data memory.
The Ma croSe quence r L IW m em ory a nd the nine pr ogra m m able c onf igura tion bits
are s upplied toge ther in the Macr oSequenc er c onf igura tion m em ory data pac ket .
The MacroSequencer configuration memory and Dual PLA configuration
memory may only be written during Active Configuration Mode. The 1-port
and 3 - port data memories for each MacroSequencer may be loaded during
Active Configuration and accessed du r ing Normal Operati ng Mode as directed
by each MacroSequencer’s LIW Register.
RAD5A4 Operating Modes
The configuration file is loaded into the RAD5A4 during Active Configuration
Mode. The RAD5A4 may be in one of three operating modes depending on
the logic states of PGM0 and PGM1:
• Normal Operation Mode, the RAD5A4 MacroSequencers concurrently
execute the LIWs, and th e Dual PLA is operation al.
• Active Configuration Mode allows each MacroSequencer’s configurati on
memory and data memories and the Dual PLA configuration memory to
be configured.
• Passive Conf igura tion Mode disa bles the dev ice I/O outputs. This a llow s other
RAD 5A4s sharing the s am e I/ O bus c ircuitry to be conf igur ed indivi dually .
Four configuration pins, named PGM0, PGM1, PRDY, and PACK, are used to
control the operating mode and configuration process. PGM0 and PGM1
control the device operating mode. PRDY and PACK provide a positive
hands hake interface between th e internal RAD5A4 circuitry and the ext ernal
circuitry configuring the device. BUS4IN[15:0] pins are used to input the
configuration data words.
RAD5A4
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This chapter includes the following:
• Configuration control pin descriptions
• Description of Configuration Modes
• Configuration with positive handshaking signals
• Minimizing Configuration Time
• Configuration without handshaking
• Time to Configure the RAD5A4
• Multiple RAD5A4 Configuration
Throughout this chapter the term LOW is used for a logic level ‘0’. The term
HIGH is used to indicate a logic level ‘1’. And an X indicates a ‘don’t care’
which should be set to either a logical ‘0’ or ‘1’.
The l symbol ind i cates the rising edge of the si gnal, and the h symbol
indicates the falling edge of the signal.
Configuration Control Pin Description
Symbol:
PGM0 PGM1 PRDY PACK
No. of Pins 1 1 1 1
Pin Number 174 173 3 4
Type Input Input Input Output
Function: Configuration
Mode0 Configuration
Mode1 Configuration
Ready Configuration
Acknowledge
table 30
PGM0 and PGM1: Configurat ion Mode Pins
The PGM0 and PGM1 pins are used as inputs to determine the operating mode
of the RAD5A4. They are functio nally identical.
• When both pins are HIGH, the RAD5A4 is in Active Configuration Mode.
In thi s mod e, all I/O out puts are in a high-impedance state, and most internal
registers and flip-flops in t he MacroSequencers and Dual PLA are held in an
initialized state. PACK is enabled for output to indicate when the device
may be configured.
• When th ey are bo th LOW, the devi ce is in Normal Operat ing Mode, and al l
I/O pins are under the control of the MacroSequencers and Dual PLA, and
PACK is in a high-i mpedance state. No configuration of the device may
occur.
• When one is LOW and one is HIGH (either one), the device is in a Passive
Configuration Mode, and all I/O outputs and the PACK output are in a high-
impedance state. No configuration of the device may occur.
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PRDY: Configurat ion Ready
During Active Configuration Mode, external circuitry uses the PRDY (l) input
to communicate to th e device to load th e configurati on dat a word present on
BUS4IN[15:0] into the device. PRDY (h) is used to query if the RAD5A4 is
ready for the next configuration data word.
PACK: Configuration Acknowledge
During Active Configuration Mode, PACK (l) is used by the RAD5A4 to
indi cate when the co nfiguration data word has been accept ed and PACK (h) is
used to indicate when a new data word will be accepted.
PLACLK: Conf iguration Clock Signal
During Active Configuration Mode, PLACLK should be connected to a free-
running clock signal as defined in the Electrical Specifications. The RAD5A4
configuration circuitry is rising edge (l) triggered by this clock pulse.
RAD5A4 Configuration Modes
Normal Operating Mode: PGM0 = PGM1 = LOW
Normal Operatin g Mode occurs when PGM0 and PGM1 are set LOW and
maintained LOW. This prevents configuration from occurring, and device I/O
pins will remain active under the control of the MacroSequencers and Dual
PLA. PACK will remain in a high-imp edance state. PGM0 and PGM1 are
asyn chronous inputs and must be maintained in their logic states to prevent
undesired device operation.
PRDY should be set to a known state to minimize power dissipation.
Passive Configuration Mode: PGM0 or PGM1 = HIGH, the other LOW
Passive Configuration Mode occurs when one of PGM0 or PGM1 is HIGH and
the other is LOW. When at least one of PGM0 or PGM1 is HIGH, all I/O
outputs are in a high-imped ence state.
Configuration will not occur in P assive Configuration Mode or Normal
Operating Mode. Passive Configuration Mode allows RAD5A4 devices on a
common bus to be configured one at a time without affecting I/Os to other
RAD5A4 devices in t he system.
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Active Configuration Mode: PGM0 = PGM1 = HIGH.
Only during Active Configuration Mode can the configuration file be loaded
into the RAD5A4 device.
For Active Configuration, PLACLK, PGM0, PGM1, PRDY, PACK, and
BUS4IN[15:0 ] are used as follows:
• PLACLK should be connected to a free running clock signal.
• PGM0 and PGM1 must be held HIGH for active RAD5A4 Configuration.
• BUS4IN[15:0] is used for configuration data word input.
• PRDY input and PACK output work together to provide positive
handshaking signals.
When both PGM0 and PGM1 are HIGH, MacroSequencer and Dual PLA
registers and flip-flops are held in an initialized state.
Once PGM0 and PGM1 are HIGH, and the device is in Active Configuration
Mode, they must remain HIGH until a Configuration Halt state. If one of them
goes LOW, the device will transition out of Active Configuration Mode
resulting in the configuration circuitry internal registers, counters, and flip-
flops resetting to an initialized state.
Configuri ng a RAD5A4 Device
The RAD5A4 is configured by loading the configuration file wh ich may be
generated by the RADware design tools.
The configuration file is divided into 16-bit configuration data words labeled
‘DWn’ where n represents the data word being loaded. The preamble is
represented by DWP. DW0 represents the first configuration data word, and
DWmax represents the last configuration data word. Each memory type
requires a different number of configuration data words.
For example, 9 9 data words are required to l oad the M acroSequencer
configuration memory. The LIW instruction memory requires 96 (32 x 3)
configuration data words (DW0 - DW95). The MacroSequencer configuration
bits are loaded using an additional data word (DW96). Two more data words
(DW97 - DW98) contain reserved bits that complete the MacroSequencer
configuration memory data packet.
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When loading configuration data words into a memory, it is necessary to load
all data words to fill that memory.
Confi gurable
RAD5A4 Memories Number of Data Words
to Load into Memory
DWmax
MacroSequencer configuration memory 99 DW98
MacroSequencer 1-port memory 32 DW31
MacroSequencer 3-port memory 16 DW15
Dual PLA configuration memory 300 DW299
table 31
About the Configuration File
All information needed to configure the RAD5A4 is prepared in a
configuration file by the ITC software tools. Some information about the
configuration file has also been included for reference purposes:
• The configur ation file consists of configuration data packets for each
RAD5A4 memory to be programmed.
• Each configuration data packet consists of one 16-bit preamble data word
that indicates which memory is to be programmed followed by the data to be
loaded into the memory.
• The configuration file is loaded onto the RAD5A4 using 16-bit configuration
data words (DWn).
Configurati on with Positi ve Handshaking Signals
The RAD5A4 has been designed for configuration to occur with positive
handshaking signals by using the PRDY input and PACK output. This pattern
between PRDY and PACK is repeated from Configuration Initialization to
Configuration Halt:
• PRDY (h) is an input to query if RAD5A4 will accept new data.
• PA CK ( h) is an output to advise that the device is ready to receive new data.
• PRDY (l) is an input to indicate when new data is present on pins
BUS4IN[15:0] and ready to be loaded.
• PA CK ( l) is an output used to advise when data is accepted by the device.
PRDY should not be c hange d until PACK ha s cha nged to the sam e sta te as PRDY.
The R A D5A 4 supports sy nchr onous or a sy nchr onous protoc ols. Cha nge s of sta te
for PRDY, PGM0 and PGM1 w ill be de tecte d by the RA D5A 4.
When conf igura tion is com plete, PACK w ill rem a in HIGH indef initely indica ting
that the device will not accept more configuration data. The device may be take n out
of A ctiv e Conf ig uration Mode by tak ing PG M0 and/or PGM1 L OW .
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Configurati on Timing
When loading configuration data words, PACK output will go LOW on the
second PLACLK (l) after PRDY goes LOW, and PACK will go HIGH on the
second PLACLK (l) pulse after PRDY goes HIGH. The shortest time to load
a configuration data word is four P LACLK cycles unless one of these four
conditions occur that require additional PLACLK cycles:
• Configuration Initialization. Additional PLACLK pulses are required.
• Configuration Continue. Additional P LACLK pulses are required.
• Configuration Halt. PACK will not go LOW.
• Invalid preamble. PACK will not go LOW.
The following diagrams depict the relationship between PRDY and PACK in
Active Configuration Mode. The P GM0 and PGM1 pins are referenced as
PGM_a and PGM_b because either pin may be changed first, or they may be
changed at the same time.
All PLACLK pulse timing is with respect to the rising edge of the clock
pulse (l).
Active Configuration begins when PGM0 and PGM1 are set HIGH (tB).
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The timing diagrams that follow depict typical configuration cycle timing
separated into four areas of operation:
• Initial portion,
• Mid-Cycle portion,
• Continue portion, and
• Halt portion.
PRDY
Input
PLACLK
Input
PACK
Output
PGM_a
Input
PGM_b
Input
I/O
Outputs
V
OH
V
IL
V
IL
V
OL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
BUS4IN[15:0]
Inputs
V
IH
V
IL
V
IH
V
IH
Hi-Z
Hi-Z
Configuration Cycle Timing for RAD5A4 - Initial Portion
DWP DW0 DW1
t
B
t
A
t
C
t
D
t
E
t
F
t
G
t
H
t
I
t
J
t
K
t
L
t
M
t
N
t
O
t
P
DW2
figure 39
PRDY
Input
PLACLK
Input
PACK
Output
V
OH
V
IL
V
IL
V
OL
BUS4IN[15:0]
Inputs V
IH
V
IL
V
IH
V
IH
Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion
DWn DWn+1
t
J
t
K
t
I
t
L
t
M
t
O
t
P
t
N
figure 40
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PRDY
Input
PLACLK
Input
PACK
Output
V
OH
V
IL
V
IL
V
OL
BUS4IN[15:0]
Inputs V
IH
V
IL
V
IH
V
IH
Configuration Cycle Timing for RAD5A4 - Continue Portion
DWmax-1 DWmax
t
T
t
U
t
S
DWP
t
E
t
F
t
X
t
V
t
W
t
G
t
H
t
I
figure 41
PRDY
Input
PLACLK
Input
PACK
Output
V
OH
V
IL
V
IL
V
OL
BUS4IN[15:0]
Inputs V
IH
V
IL
V
IH
V
IH
Configuration Cycle Timing for RAD5A4 - Halt Portion
DWmax-1 DWmax
t
T
t
U
t
S
t
Z
t
Y
t
X
t
V
t
W
PGM_a
Input
PGM_b
Input
I/O
Outputs
Hi-Z
Hi-Z V
OH
V
IL
V
IL
V
OL
V
IH
V
IH
figure 42
Between time tB in the Initial portion and time tY in the Halt portion, the states
of PGM_a, PGM_b, and the I/O outputs remain constant, and are not shown in
the Mid-Cycle portion and the Continue portion.
These four timing figures (figures 38 - 41) illustrate RAD5A4 configuration
timing and operation using one example of PRDY response time after PACK
transitions. For this example, a positive handshake exists between the PRDY
signal from extern al circuitr y and the PACK acknowledge signal fro m th e
RAD5A4. PRDY is an asynchronous input signal that is changed between the
first and second PLACLK rising edge after PACK transitions.
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Configuration Initialization
Configuration initialization begins upon entry into the Active Configuration
Mode when the second of PGM0 and PGM1 are set HIGH (tB) and ends when
PACK goes LOW for the first time (tD). PACK goes from a high-impedence
state to HIGH at the beginning of Configuration Initialization (tB) and remains
HIGH during Configuration Initialization.
Configuration Initialization is represented as the time between tB and tD in the
timing diagrams and the configuration summary table, and is represented by
time tBD in the Time to Configure the RAD5A4 discussions.
During Configuration Initialization, PACK output remains HIGH for a
minimum of four PLACLK rising edges after the second of PGM0 and PGM1
are asserted HIGH at time tB. PRDY may be asserted LOW during or before
Configuration Initialization. The time when PACK goes LOW is dependent on
when PRDY is LOW.
• If PRDY is set LOW before the third PLACLK pulse (l) after PACK goes
HIGH (l), then PACK will go LOW (h) on the fourth PLACLK (l) after
PACK goes HIGH (l). This is the quickest method.
• If PRDY is set LOW after the second PLACLK pulse (l) after PACK goes
HIGH (l), then PACK will go LOW (h) on the second PLACLK pulse (l)
after PRDY is set LOW (h).
When PACK goes LOW (tD) at the end of Conf igura tion Initializa tion, the dev ice
will be ready to accept data input on BU S4IN[15:0]. The prea m ble, DW P, should be
present on B US4IN[15:0] bef ore PRDY is set HI GH at tim e tF.
Configuration Continue
Either Configuration Cont inue or Configuration Halt o ccurs at the en d of each
data packet . Bit 7 from each pr eamble (DWP:b7 ) specifies whether th e
accompanying dat a packet is the last one (b7 = 0), or if another data packet
follows (b7 = 1) to continue configuration.
When a Conf igura tion Continue oc curs, PA CK output re m ains H IG H f or a
minimum of six PLACLK periods after receiving the last data word, DWmax, at
time tV. The tim e w hen PACK goes LO W is depende nt on w hen PRDY is L OW .
• If PRDY is set LOW before the fifth PLACLK pulse (l) after PACK goes
HIGH (l), then PACK will go LOW (h) on the sixth PLACLK (l) after
PACK goes HIGH (l). This is the quickest method.
• If PRDY is set LOW after the fourth PLACLK pulse (l) after PACK goes
HIGH (l), then PACK will go LOW (h) on the second PLACLK pulse (l)
after PRDY is set LOW (h).
The preamble, DWP, for the next data packet may be pl aced on BUS 4IN[15:0]
in preparation for configuration of the next memory after PACK goes HGH to
accept DWmax.
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When PACK goes LOW (h) (tX), configuration may continue. If PACK
remains HIGH at time tX, then a Configuration Halt is indicated.
Configuration Halt
Configuration Halt occurs when all data packets in the configuration file have
been loaded. In the halted state, P ACK remains HIGH after time tX regardless
of when PRDY is set LOW until the Active Configuration Mode has been
terminated by setting PGM0 and/or PGM1 to LOW.
The only time the device should enter a Configuration Halt state is wh en the
configuration file is completely loaded. Timing for Configuration Halt is the
same as the timing for Configuration Continue. Configuration Halt is
differentiated from the Configuration Continue by the logic state of PACK after
time tX.
The device should always be in a Configuration Halt before transitioning
PGM0 or PGM1 LOW. During Active Configuration termination, when the
first of pins PGM0 or PGM1 is set LOW (tY), PACK output will go to a high-
impedance state. When the second of pins PGM0 or PGM1 is set LOW(tZ), the
I/O outputs will become active under control of the MacroSequencers and Dual
PLA. PGM0 and PGM1 are referenced as PGM_a and PGM_b because either
pin may be set LOW first, or they may be set LOW at the same time.
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Invalid Preamble (DWP)
If bits six through zero of the preamble (DWP b6:b0) are an allowed option,
the preamble is considered to be valid, and additional data words may be
loaded.
• If the preamble is valid, PACK will go LOW two PLACLK pulses after
PRDY is set LOW (tI) as shown in figure 38.
• Otherwise, the preamble is invalid, and PACK will remain HIGH until
Active Configuration is terminated as shown by time tI in figure 42. PACK
will remain HIGH until Active Configuration Mode is terminated.
PRDY
Input
PLACLK
Input
PACK
Output
PGM_a
Input
PGM_b
Input
I/O
Outputs
V
OH
V
IL
V
IL
V
OL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
BUS4IN[15:0]
Inputs
V
IH
V
IL
V
IH
V
IH
Hi-Z
Hi-Z
Configuration Cycle Timing for RAD5A4 with Invalid Preamble
DWP
t
B
t
A
t
C
t
D
t
E
t
F
t
G
t
H
t
I
figure 43
The RADware software automatically generates the correct preamble for each
memory configured by the configuration file; therefore, the device should not
enter an i nvalid p r eamble state unless it is caused by other factors.
RAD5A4
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Configuration Summary
The following configuration table is a summary of the detailed configuration
steps described in this chapter. The number of PLACLK pulses between signal
changes is not indicated. The time (t_) refers to times shown on Configuration
timing diagrams, figures 38 - 42.
Confi guration Pins
Inputs Outputs
T
ime
Step PGM_a PGM_b PRDY BUS4IN PACK I/Os Operation Description t_
Normal Operation Mode
L
L
X
X
Hi-Z
Active I/O pins are operational
under control of the Dual
PLA and MacroSequencers.
<tA
Passive Configuration Mo de
H L X X Hi-Z Hi-Z Passive Configuration tA
Active Configuration Mode - Initialization
1a H H H or L X H Hi-Z Set both PGM0 and PGM1
High to begin Active
Configuration.
tB
1b H H L X H Hi-Z Set PRDY LOW, if it is not
already LOW. tC
1c H H L X hHi-Z Configuration Initialization
complete tD
Load Preamble
2a H H L DWP L Hi -Z Place preamble on pins
BUS4IN[15:0] if not
already loaded.
tE
2b H H lDWP L Hi-Z Set PRDY HIGH to tell
device that DWP is ready. tF
2c H H H DWP
lHi-Z PACK acknowledges that
preamble is recei ved. tG
2d H H hX H Hi-Z Take PRDY LOW to qu ery
if RAD5A4 will accept new
data.
tH
2e H H L X
hHi-Z When Preamble i s valid,
PACK will go LOW. Go to
step 3a.
tI
table 32
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Confi guration Pins
Inputs Outputs
T
ime
Step PGM_a PGM_b PRDY BUS4IN PACK I/Os Operation Description t_
Load DWn (n = 0,1,2, . . . max -1)
3a H H L DWn L Hi-Z Place next DWn data on
BUS4IN[15:0]. tJ
3b H H lDWn L Hi-Z S et PRDY HIGH to advise
that next data is present. tK
3c H H H DWn lHi-Z PACK acknowledges DWn
data is recei ved. tL
3d H H hX H Hi-Z Take PRDY LOW to query
if RAD5A4 will accept new
data.
tM
3e H H L X hHi-Z P ACK goes LOW to
acknowledge that next data
will be accepted. Repeat
steps 3a - 3e until DWmax.
tN
Load DWmax
4b H H L DWmax L Hi-Z Place DWmax
configuration data word on
BUS4IN[15:0]
tT
4c H H lDWmax L Hi-Z Set PRDY HIGH to advise
that DWmax is present. tU
4d H H H DWmax
lHi-Z PACK acknowledges
DWmax data is received. tV
4e H H hX H Hi-Z Take PRDY LOW to query
if RAD5A4 will accept new
data. Go to 4f or 4g.
tW
Conti nue Active Configuration
4f H H L X hHi-Z If PACK goes LOW, the next
data will be accepted.
Continue configuration of
another memory with step 2a.
tX
table 32
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Confi guration Pins
Inputs Outputs
T
ime
Step PGM_a PGM_b PRDY BUS4IN PACK I/Os Operation Description t_
Halt Active Configuration
4g H H L X H Hi-Z If PACK remains HIGH,
configuration is halted. tX
4h H hL X Hi-Z Hi-Z To terminate active
Configuration, take PGM0
or PGM1 LOW.
tY
Passive Configuration Mo de
L H X X Hi-Z Hi-Z Passive Configuration tY
Normal Operation Mode
L L X X Hi-Z Active Normal operation. >tZ
table 32
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Minimizing Configuration Time
The shortest configuration cycle is four PLACLK pulses per data word in the
Mid-Cycle portion of Active Configuration.
The number of P LACLK pulses req uired to load each data word is dependent
upon how soon PRDY input changes state after PACK output changes state.
The timing examples shown earlier in this chapter illustrate changes in PRDY
between the rising edges of the first and second PLACLK pulses after PACK
output tran sitions. Th i s results in si x PLACLK pulses for each dat a word in the
Mid-Cycle portion of Active Configuration.
To achieve the fastest configuration operations with or without handshaking,
PRDY must transition before the first PLACLK rising edge after PACK output
transitions. PRDY may be taken LOW before the next PLACLK pulse (l)
after PACK goes HIGH, and PRDY may be taken HIGH before the next
PLACLK pulse ( l ) after PACK goes LOW.
A timing diagram showing a minimum of four clock cycles per configuration
data word is shown here. This diagram illustrates asynchronous configuration
with handshaking. The BUS4IN[15:0] data is valid whenever PRDY is HIGH.
PRDY
Input
PLACLK
Input
PACK
Output
V
OH
V
IL
V
IL
V
OL
BUS4IN[15:0]
Inputs V
IH
V
IL
V
IH
V
IH
Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion
DWn DWn+1
t
J
t
K
t
I
t
L
t
M
t
O
t
P
t
N
DWn+2
figure 44
Setup and Hold Timing
The setup and hold timing requirements of the PRDY and BUS4IN[15:0]
inputs with respect to the PLACLK (l) input signal to correctly load
configuration data is shown in figure 44.
During Active Configuration Mode, a PRDY transition is received by the
RAD5A4 on the first PLACLK (l) after the PRDY transition satisfies the
actual setup time. For asynchronous PRDY signals, a PRDY transition that
does not meet the actual setup time on the first PLACLK (l) will be received
on the next PLACLK (l). Synchronous PRDY inputs must satisfy the
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mini mum s etup time (tSU) speci fied in the Electrical Specification s t o be
received by the RAD5A4 on the desired PLACLK rising edge.
The configuration circuitry has been designed so that the data on
BUS4IN[15:0 ] is received by the RAD5A4 one PLACLK (l) after PRDY (l)
input is received by the d evice. This allows BUS4IN[15:0 ] data t o change at
the same time with PRDY (l) and provides for a defined maximum allowed
skew (tSKEW(max)) between PRDY (l) input and input data on BUS4IN[15:0].
The parameter tSKEW(max) is calculated as follows:
tSKEW(max) = PLACLK period + tSU (PRDY) - tSU (BUS4IN[15:0] )
where:
PLACLK period = the period of the PLACLK signal
tSU (PRDY) = minimum setup time for PRDY specified in the
Electrical Specificatio ns, Active Configurat ion
tSU (BUS4IN[15:0]) = minimum setup time for BUS4IN[15:0] specified in the
Electrical Specificatio ns, Active Configurat ion
When using asynchronous configuration, BUS4IN[15:0] transitions should
occur no later than PRDY (l) to assure correct configuration. Asynchronous
configuration should use positive handshaking.
When using synchronous configuration, PRDY and BUS4IN[15:0] transitions
must satisfy the setup and hold time requirements of the Electrical
Specifications fo r the appropriate PLACLK (l) as shown in figure 44.
Synchronous configuration may be used with or without handshaking provided
proper timing is implemented.
BUS4IN[15:0]
Inputs
PRDY
Input
PLACLK
Input
PACK
Output
t
SU
t
SU
t
H
t
SU
t
H
t
H
t
CO
t
CO
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
OH
V
OL
Detailed Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion
DWn
figure 45
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Configuration without Handshaking
It is possible to configure the RAD5A4 without using PACK output signals.
This requires an understanding of the number of PLACLK signals required to
receive and l oad data i nto memory.
To speed configuration, PRDY input from external circuitry may change state
synchronously on the same PLACLK (l) as PACK changes in anticipation of
PACK transitioning. The PRDY signal must not change state until after the
minimum specified hold time (tH) fo llowing PLACLK (l) has been satisfied.
This pr ocedure may be used to minimize configuration time when executing at
a high PLACLK frequency by eliminating the effects of PACK output delay
time, system response time, and PRDY setup time when using the handshaking
protocol.
The timing diagrams in figures 45 - 48 illustrate an example synchronous
system where PRDY and BUS4IN[15:0] inputs are from external registers that
are clocked on the appropriate PLACLK (l) edge. The minimum number of
PLACLK pulses for synchronous configuration is illustrated in these figures
between time tB and time tY . This example uses one PLACLK pulse between
the transitions of PGM_a and PGM_b inputs in both the Initial portion (figure
45) and the Halt portion (figure 48) of the configuration cycle.
PRDY
Input
PLACLK
Input
PACK
Output
PGM_a
Input
PGM_b
Input
I/O
Outputs
V
OH
V
IL
V
IL
V
OL
V
IH
V
IL
V
OH
V
OL
V
IH
V
IL
BUS4IN[15:0]
Inputs
V
IH
V
IL
V
IH
V
IH
Hi-Z
Hi-Z
Synchronous Configuration Cycle Timing for RAD5A4 - Initial Portion
DWP DW0 DW1
t
B
t
A
t
C
t
D
t
E
t
F
t
G
t
H
t
I
t
J
t
K
t
L
t
M
t
N
t
O
t
P
DW2
figure 46
RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
Infinite Technology Corporation March 1997 81
Phone: 972-437-7800
PRDY
Input
PLACLK
Input
PACK
Output
V
OH
V
IL
V
IL
V
OL
BUS4IN[15:0]
Inputs V
IH
V
IL
V
IH
V
IH
Synchronous Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion
DWn DWn+1 DWn+2
t
J
t
K
t
I
t
L
t
M
t
N
t
P
t
O
figure 47
PRDY
Input
PLACLK
Input
PACK
Output
V
OH
V
IL
V
IL
V
OL
BUS4IN[15:0]
Inputs V
IH
V
IL
V
IH
V
IH
Synchronous Configuration Cycle Timing for RAD5A4 - Continue Portion
DWmax
t
X
DWP
t
S
t
V
t
W
t
U
t
T
t
E
t
F
t
G
t
H
figure 48
RAD5A4
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82 March 1997 Infinite Technology Corporation
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PRDY
Input
PLACLK
Input
PACK
Output
V
OH
V
IL
V
IL
V
OL
BUS4IN[15:0]
Inputs
V
IH
V
IL
V
IH
V
IH
Synchronous Configuration Cycle Timing for RAD5A4 - Halt Portio
n
DWmax
t
X
t
Y
t
Z
PGM_b
Input
PGM_a
Input
Hi-Z
Hi-Z
I/O
Outputs
V
OH
V
IL
V
IL
V
OL
V
IH
V
IH
t
T
t
W
t
U
t
S
t
V
figure 49
PRDY is initially set HIGH (tC) at the same time PGM_b is set HIGH (tB) to
start Active Configuration as shown in figure 45. PGM_b is set LOW (tY) at
the same time that tX occurs to end Active Configuration as shown in figure 48.
PACK output transition occurs on the second PLACLK (l) after PRDY
changes state except for tC to tD in figure 45 and time tW to tX in figures 47 and
48 where additional PLACLK pulses are required.
RAD5A4
Reconfigurable Arithmetic Datapath RAD5A4 Configuration
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Time to Configur e the RAD5A4
RAD5A4 devices may be completely reconfigured in less than 150µs. The
exact time required to configure a RAD5A4 device is dependent upon:
• Number of PLACLK pulses per configuration memory which is determined
by the size of the memory and the PRDY response time after PACK changes,
• How many of the memories are programmed, and
• PLACLK rate.
A discussio n of each of th ese factors follows with tables of example cho ices.
PLACLK Pulses per Memory Configured
The number of PLACLK Pulses for each configurati on memory is dependent
upon the PRDY response time after PACK changes.
To minimize configuration time, PRDY can be changed before the rising edge
of the first PLACLK pulse following a change in PACK as shown in figure 43.
However, some systems may require more time before PRDY is chan ged. The
example used in figures 38 - 42 shows PRDY changing asynchronously
between the rising edges of the first and second PLACLK pulses following a
change in PACK.
This table shows the number of complete PLACLK pulses required to
configure each type of RAD5A4 memory using several di fferent PLACLK
delays (tDPR). The time required for Configuration Initialization and
Configuration Continue and Halt are shown separately because they are
independent of the type of memory being configured.
PLACLK Pulses for Configuration
Type of Memory
MacroSequencer M emories Dual PL A
During PLACLK
pulse a fter PACK
changes
PRDY
Delay
MS Config.
Memory
(TDW=100)
1-port
Memory
(TDW=33)
3-port
Memory
(TDW=17)
Config.
Memory
(TDW=301)
Config.
Initialization
Config.
Continue
& Halt
t
DPR t
DV t
DV t
DV t
DV t
BD t
VX
first 0 398 130 66 1202 5 6
second 1 597 195 99 1803 5 6
third 2 796 260 132 2404 5 6
fourth 3 995 325 165 3005 5 6
fifth 4 1194 390 198 3606 6 6
sixth 5 1393 455 231 4207 7 7
seventh 6 1592 520 264 4808 8 8
eighth 7 1791 585 297 5409 9 9
table 33
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Reading the PLACLK Pulses for Configuration Table
TDW
TDW = the total number of data words for each type of memory and includes
the preamble data word.
During PLACLK pulse and PRDY Delay (tDPR)
tDPR = the number of PLACLK rising edges b et ween a change in PACK and the
PRDY response. For example, when PRDY changes before the rising edge of
the first PLACLK pulse following a change in PACK, the PRDY Delay is 0
(tDPR = 0). If PRDY changes between the rising edges of the first and second
PLACLK following a change in PACK, then the PRDY delay is 1 (tDPR = 1).
The example illustrated in figures 38 - 41 uses tDPR = 1. The example illustrated
in figures 45 - 48 uses tDPR = 0.
tDV
tDV = num ber of PLA CL K puls es to loa d a m em ory not inc luding the ex tra c lock
pulses r equired f or a Conf igura tion Continue or Conf igura tion Halt. I n the ex am ple
timing diagra m s show n in this chapter, tDV is the tim e f rom tD to tV.
tDV = (2 + tDPR)*(2 * TDW - 1)
tBD - Configuration Initialization Time
tBD = number of PLACLK periods for Configuration Initialization including the
full PLACLK period in which the second of the two PGM pins are taken
HIGH. In the example timing diagrams shown in this chapter, tBD is the time
from tB to tD.
tBD = (2 + tDPR) if tDPR > 3
tBD = 5 if tDPR < 4 (minimum time)
In the timing diagrams shown in this chapter, time tBC = tDPR.
tVX - Configuration Continue & Halt Time
tVX = number of PLACLK pulses for Configuration Continue and Halt. In the
example timing diagrams shown in this chapter, tVX is the time from tV to tX.
tVX = (2 + tDPR) if tDPR > 4
tVX = 6 if tDPR < 5 (minimum time)
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PLACLK Pulses for Device Configuration
PLACLK Pulses for Configuration
Single Memory Configuration Multiple Memories
MacroSequencer M emories Dual PLA
During
PLACLK pulse
after PACK
PRDY Delay MS Config.
Memory
(TDW=100)
1-port
Memory
(TDW=33)
3-port
Memory
(TDW=17)
Config.
Memory
(TDW=301)
One Macro-
Sequencer
(3
memories)
RAD5A4
(13
memories)
changes tDPR t
BX t
BX t
BX t
BX t
BX t
BX
first 0 409 141 77 1213 617 3661
second 1 608 206 110 1814 914 5450
third 2 807 271 143 2415 1121 7239
fourth 3 1006 336 176 3016 1508 9028
fifth 4 1206 402 210 3618 1806 10818
sixth 5 1407 469 245 4221 2107 12621
seventh 6 1608 536 280 4824 2408 14424
eighth 7 1809 603 315 5427 2709 16227
table 34
tBX - Time from Configuration Initialization to Halt
tBX = number of PLACLK pulses for device configuration. It includes the
number of PLACLK pulses for:
• Configuration Initialization,
• Each configured memory, and
• Applicable Configuration Continues, and
• Configuration Halt
In the example timing diagrams shown in this chapter, tBX is the time from tB to
tX in Configuration Halt.
tBX = tBD + tDV (for each memory) + (tVX * no. of configured memories)
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Device Configuration Time
Device configuration time is a function of the number of PLACLK pulses and
the PLACLK rate.
RAD5A4 Configuration Time (13 memories)
PRDY PLACLK Input Frequency (M Hz)
During PLACLK pulse Delay 5 10 15 20 25
after PACK changes tDPR tAZ (µ
µµ
µs) tAZ (µ
µµ
µs) tAZ (µ
µµ
µs) tAZ (µ
µµ
µs) tAZ (µ
µµ
µs)
first 0 733 366 244 183 147
second 1 1091 545 364 273 218
third 2 1449 724 483 362 290
fourth 3 1807 903 602 452 361
fifth 4 2165 1082 722 541 433
sixth 5 2526 1263 842 631 505
seventh 6 2886 1443 962 722 577
eighth 7 3247 1624 108 812 649
table 35
tAZ - Time for Device Configuration
tAZ includes the number of PLACLK pulses for:
• Configuration Initialization,
• Each configured memory,
• Applicable Configuration Continues, and
• Configuration Halt.
In the exa m ple tim ing dia gram s show n in this c hapter, tAZ is the tim e f rom tA to tZ.
tAZ = tAB + t BX (for all 13 memories) + tXY + tYZ
where these variable assumption s were made:
tAB = time from tA to tB = 1 PLACLK pulse
tXY = time from tX to tY = tDPR
tYZ = time from tY to tZ = 1 PLACLK pulse
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Multiple RAD5A4 Device Configuration
Multiple RAD5A4 devices may be configured as shown in the following
diagram. In this diagram, setting PGM1 HIGH, with all the PGM0s LOW, will
put all of the RAD5A4s in a Passive Configuration Mode. Each RAD5A4 may
be configured one at a time by asserting its PGM0 HIGH. Only one PGM0
may be asserted HIGH at a ti me.
This method permits PRDY and PACK to communicate with the host
controller one device at a time. All RAD5A4 I/O outputs are in high-
impedance st ate when any devices are b eing configured.
.
.
.
RAD5A4_0
PGM0
PGM1
PRDY
PACK
BUS4IN[15:0]
RAD5A4_1
PGM0
PGM1
PRDY
PACK
BUS4IN[15:0]
RAD5A4_n
PGM0
PGM1
PRDY
PACK
BUS4IN[15:0]
Host Controller
PGM0 for device 0
PGM1
PRDY
PACK
BUS4IN[15:0]
PGM0 for device 1
PGM0 for device n
.
.
.
Multiple RAD5A4 Device Configuration
figure 50
RAD5A4
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Configurati on Data Word Counter
Configuration data is loaded serially by 16-bit data words into the RAD5A4
memories beginni ng with DW0 and ending at DWmax for each memory being
configured.
When in Active Configuration Mode, the RAD5A4 updates its internal
configuration data word (DW) counter automatically to place the configurat ion
data in the correct memory location.
The following diagram illustrates how the DW counter relates to the memo ry
addresses. DWP is the preamble and is not stored in RAD5A4 device memory.
Preamble (DWP)
DW0
DW1
DWmax
next Preamble
DW0
DW0 b15 .. b0DW1 b15 .. b0. . .
DWmax . . .
.
.
.
Memory
BUS4IN[15:0]
.
.
.
DW1
figure 51
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
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IRAD5A4
DEVICE SPECIFICATIONS
1. Features
• E ffici ent solution f or appl yi ng custom numerical algorithms t o a hi gh-speed
data stream
• 400 Million 16 x 8 Multiply-Accum ulat e Operat ions per second
• Four 100 MHz 16-bit A ri thmeti c MacroSequencers
• I ntegrated High-Speed programmabl e S tate Machine
• Five shared 16-bit int ernal dat a buses
• 10 ns 16 x 8 Multiply i n each MacroSequencer
• 20 ns 16 x 16 Multiply i n each MacroSequencer
• P redi ctable Datapath Ti ming
• In-Circuit Programmability
Each MacroSequencer offers:
• 1 or 2 dynamicall y l oadabl e ari thmeti c mac ros that may contain nested loops,
conditi onal l ogi c and subroutines
• Concurrent 10 ns Multi pl y-A ccum ul at e, Add, Shi ft and Logic operat i ons
• 48-bit Accumulator in Multiplier-Accumulator
• 200 MByt es/Sec ond Datapath throughput
• Zero-overhead loopi ng
• S mart indexing for effic i ent FIR, II R, FFT, and DCT functions
• 16 c onfigurable I/O pi ns
• 48 general purpose 16-bit memories
à 32 Word Single-I ndexed 1-port Mem ory
à 16 Word Triple-Indexed 3-port Mem ory
• Cascadable archi t ecture for multi-s tage filt eri ng and 32-bi t operations
2. RAD5A4 General Description
A RAD5A4 is a high-speed accelerator for d at a st ream algorithms. It is
composed of four independent 16-bit fixed-point programmable processors
called MacroSequencers that execute multiple instructions on multiple data
paths (MIMD). The RAD5A4 also contains a built-in Dual PLA, five 16-bit
buses, 64 I/O pins, 16 input pins, and five independent clocks which drive the
four MacroSequencers and the Dual PLA at clock rates up to 100 MHz.
RAD5A4
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90 March 1997 Infinite Technology Corporation
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3. Applications
Imaging
• V i deo f i l ter
• Multi -media image scal i ng and i mage functions
• Medic al i nstrumentation
• P hot o manipulat i on
• Satellite
• Radar
• Sonar
Arithmetic Accelerator for:
• Communi cations (Li near t ransform ations)
• Compression
• Robotics
• FP GA Coprocessor
• DS P Coprocessor
4. Ordering and Package Information
Device
Type Speed
(MHz) Interface
Type Temp
Range Package Pin
Count
RAD5A4 -70, -100 T, C C Q,H 176
-40, -60 V
5. Block Diagram
Simplified RAD5A4 Control and Data Flow Diagram
Control Bus
PLAI/O[7:0]
MS3I/O[15:0]
MS1I/O[15:0]
BUS4IN[15:0]
Macro-
Sequencer
3
PLAIN[7:0]
MS2I/O[15:0]
MS0I/O[15:0]
Macro-
Sequencer
2
Bus4
Dual
PLA
MSPair32
Macro-
Sequencer
0
Bus0
Bus1
Bus2
Bus3
Macro-
Sequencer
1
16
16
16
16
16
16
16
16
32
16
8
8
8
8
12
MSn Direct
Control and
Status Pins
8
20
MSPair23
MSPair10
MSPair01
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
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Pin List
Pin Name No. of
Pins Pin Number Pin
Type Function
VDD 12
14, 24, 35, 49, 59,
74, 84, 98, 109,
119, 147, 162
PS Positive Power Supply
VSS 19
5, 11, 19, 29, 30,
40, 54, 64, 69, 79,
93, 103, 104, 114,
122, 128, 130, 152,
157
PS Power Supply: Ground
MacroSequencer0
MS0I/O [15:0]
16 99, 100, 101, 102,
105, 106, 107, 108,
110, 111, 112, 113,
115, 116, 117, 118
I/O Input and output signals of MacroSequencer0
MS0CTRL[1:0] 2 125, 126 I MacroSequencer0 Control Signals
MS0AWAIT 1 120 O MacroSequencer0 Await Signal
MS0SEND 1 121 O MacroSequencer0 Send Signal
MS0OE 1 124 I MacroSequencer0 Output Enable
MS0CLK 1 123 I P o sitive edge clock for MacroSequencer0
MacroSequencer1
MS1I/O[15:0]
16 67, 68, 70, 71, 72, 73,
75, 76, 77, 78, 80, 81,
82, 83, 85, 86
I/O Input and output signals of MacroSequencer1
MS1CTRL[1:0] 2 96, 97 I MacroSequencer1 Control Signals
MS1AWAIT 1 91 O MacroSequencer1 Await Signal
MS1SEND 1 92 O MacroSequencer1 Send Signal
MS1OE 1 95 I MacroSequencer1 Output Enable
MS1CLK 1 94 I Positive edge clock for MacroSequencer1
MacroSequencer2
MS2I/O [15:0]
16 34, 33, 32, 31, 28, 27,
26, 25, 23, 22, 21, 20,
18, 17, 16, 15
I/O Input and output signals of MacroSequencer2
MS2CTRL[1:0] 2 8, 7 I MacroSequencer2 Control Signals
MS2AWAIT 1 13 O MacroSequencer2 Await Signal
MS2SEND 1 12 O MacroSequencer2 Send Signal
MS2OE 1 9 I MacroSequencer2 Output Enable
MS2CLK 1 10 I Positive edge clock for MacroSequencer2
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
92 March 1997 Infinite Technology Corporation
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Pin List Conti nued
Pin Name No. of
Pins Pin Number Pin
Type Function
MacroSequencer3
MS3I/O [15:0]
16 66, 65, 63, 62, 61, 60,
58, 57, 56, 55, 53, 52,
51, 50, 48, 47
I/O Input and output signals of MacroSequencer3
MS3CTRL[1:0] 2 37, 36 I MacroSequencer3 Control Signals
MS3AWAIT 1 42 O MacroSequencer3 Await Signal
MS3SEND 1 41 O MacroSequencer3 Send Signal
MS3OE 1 38 I MacroSequencer3 Output Enable
MS3CLK 1 39 I Positive edge clock for MacroSequencer3
Dual PLA
BUS4IN[15:0] 16 155, 156, 158, 159,
160, 161, 163, 164,
165, 166, 167, 168,
169, 170, 171, 172
I Inputs to the Dual PLA and bus4.
Configuration data inputs in active
configuration mode.
PLAIN[7:0] 8 144, 143, 142, 141,
140, 139, 138, 137 Inputs to the Dual PLA
PLAI/O[7:0] 8 154, 153, 151, 150,
149, 148, 146, 145 I/O I/O o f the Du al PLA
PLACLK 1 6 I Positive edge clock for the Dual PLA and
configuration.
Configuration
PGM0 1 174 I Configuration input
PGM1 1 173 I Configuration input
PRDY 1 3 I Configuration Ready Handshake Signal
PACK 1 4 O Program Acknowledge Handshake Signal
Scan Test
TCK 1 127 I Test Clock Input
TMS 1 136 I Test Mode Select Input
TDI 1 135 I Test Data Input
TDO 1 129 O Test Data Output
RAD5A4
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Absolute Maximum Ratings
Storage Temperature -65°C to +150°C
Ambient Temperature with Power Applied -55°C to +125°C
Junction Temperature -65°C to +150°C
VDD Supply Voltage with Respect to VSS * -0.5V to +7.0V
DC Input Voltage -0.5V to VDD +1.0V
DC Output or I/O Pin Voltage -0.5V to VDD +1.0V
Lead Temperature (Soldering, 10 seconds) 260°C
*All voltages are with respect to the device VSS terminals in this data sheet.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
TTL-Level Interface
94 March 1997 Infinite Technology Corporation
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TTL-Level Interface Options (Pr el iminary Specification)
Recommended Operating Conditions
Symbol Parameter Min Max Unit
VDD Supply voltage 4.75 5.25 V
VIH Input HIGH
Level MS0CLK, MS1CLK, MS2CLK,
MS3C LK, PLACLK 2.4 VDD+0.3 V
Other Inputs 2.0 VDD+0.3 V
VIL Input LOW Level -0.3 0.8 V
TA Ambient Temperature 0 70 °C
Symbol Parameter -70 -100 Unit
Min
M
ax Min
M
ax
fCLOCK Clock Frequency MS0CLK, MS1CLK, MS2CLK,
MS3CLK 0 70 0 100
PLACLK External feedback 0 33 0 43
Normal Mode Internal feedback 0 70 0 100 MHz
See Note 1. No feedback 0 83 0 111
PLACLK Active Configuration 0 20 0 25
tWH High-level Clock
Pulse Width MS0CLK, MS1CLK, MS2CLK,
MS3CLK 6.5 4
ns
PLACLK 6 4
tWL Low-level Clock
Pulse Width MS0CLK, MS1CLK, MS2CLK,
MS3CLK 6.5 4
ns
PLACLK 6 4
Note 1: fCLOCK (external feedback) = 1/(tSU + tCO), where tCO is from the registered PLAI/O output
configuration.
f
CLOCK (internal feedback) is measured usi ng intern al registers and applies to signal paths from
registered outputs within the Dual PLA that are internally connected to the Input Selectors of the
Dual PLA.
f
CLOCK (no feedback) = 1/(tWH + tWL)
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
TTL-Level Interface
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Recommended Operating Conditions (Continued)
Normal Operating Mode
Parameter From To Test -70 -100 Unit
(Input) (Input) C o nditions Min Max Min Ma x
tSU
Setup
Time
MSnI/O[15:0],
MS0CTRL[1:0],
BUS4IN[15:0]
MS0CLK
MSnI/O[15:0],
MS1CTRL[1:0],
BUS4IN[15:0]
MS1CLK
8
6
ns
MSnI/O[15:0],
MS2CTRL[1:0],
BUS4IN[15:0]
MS2CLK
MSnI/O[15:0],
MS3CTRL[1:0],
BUS4IN[15:0]
MS3CLK
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
PLACLK
12
9
ns
tH
Hold
Time
MS0CLK MSnI/O[15:0],
MS0CTRL[1:0],
BUS4IN[15:0]
MS1CLK MSnI/O[15:0],
MS1CTRL[1:0],
BUS4IN[15:0]
4
3
ns
MS2CLK MSnI/O[15:0],
MS2CTRL[1:0],
BUS4IN[15:0]
MS3CLK MSnI/O[15:0],
MS3CTRL[1:0],
BUS4IN[15:0]
PLACLK BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
0 0 ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
TTL-Level Interface
96 March 1997 Infinite Technology Corporation
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Recommended Operating Conditions (Continued)
Active Configuration Mode
Parameter From To Test -70 -100 Unit
(Input) (Input) C o nditions Min Max Min Ma x
tSU PRDY PLACLK 3 2 ns
Setup
Time BUS4IN[15:0] PLACLK 8 6 ns
tH PLACLK PRDY 2 2 ns
Hold
Time PLACLK BUS4IN[15:0] 0 0 ns
DC Characteristics
Symbol Parameter Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage VDD = Min , IOH = -4mA 2.4 V
VOL Output LOW Voltage VDD = Mi n, IOL = 8mA 0.4 V
lIH Input
HIGH
Current
TMS , TDI,
PLACLK,
MSnCLK,
TCK
VDD = Max,
VIN = VDD 10 µA
Other inputs 100 µA
lIL Input LOW
Current TMS, TDI VDD = Max,
VIN = 0 V -100 µA
Other inputs -10 µA
lOZH Off-State Output Current
HIGH VDD = Max,
VOUT = VDD 100 µA
lOZL Off-State Output Current
LOW VDD = Max,
VOUT = 0 V -10 µA
ISC HIGH-State Output Short
Circuit Current VDD = Max, VOUT = 0.5V,
TA = 25°C See Note 2. -30 -135 mA
IDD V
DD Supply Current,
Dynamic VIN = 0V or VDD, VDD = Max,
f = 25MHz, Outputs open mA
IDDS V
DD Supply Current,
Static VIN = 0V or VDD, VDD = Max,
f = 0MHz, Outputs open mA
CIN Input Capacitance TA = 25°C, VDD = 5.0V,
f = 1 MHz 5 pF
COUT Output Capacitance TA = 25°C, VDD = 5.0V,
f = 1 MHz 8 pF
MSnCLK refers to any of MS0CLK, MS1CLK, MS2CLK, or MS3CLK.
Note 2: Only one output should be tested at a time and the duration of the short circuit should not
exceed one second.
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
TTL-Level Interface
Infinite Technology Corporation March 1997 97
Phone: 972-437-7800
AC Characteristics
Normal Operating Mode
Parameter From To Conditions -70 -100 Unit
(Input) (Output) Min Max Min M ax
tCO
Clock to
Output
MS0CLK MS0I/O[15:0],
MS0SEND,
MS0AWAIT
Delay
Time MS1CLK MS1I/O[15:0],
MS1SEND,
MS1AWAIT
25
15
ns
MS2CLK MS2I/O[15:0],
MS2SEND,
MS2AWAIT
MS3CLK MS3I/O[15:0],
MS3SEND,
MS3AWAIT
PLACLK PLAI/O[7:0]
registered
PLAI/O output 18 14 ns
combinatorial
PLAI/O output
See Note 3.
30
24
ns
tPD
Prop.
Delay
Time
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
PLAI/O[7:0] combinatorial
PLAI/O output
24
20
ns
tOE MS0OE MS0I/O[15:0]
Output MS1OE MS1I/O[15:0] 25 20 ns
Enable MS2OE MS2I/O[15:0]
Time MS3OE MS3I/O[15:0]
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
MSnI/O[15:0] Through
Dual PLA
40
33
ns
PLACLK MSnI/O[15:0] See Note 3. 36 30 ns
tOD MS0OE MS0I/O[15:0]
Output MS1OE MS1I/O[15:0] 25 20 ns
Disable MS2OE MS2I/O[15:0]
Time MS3OE MS3I/O[15:0]
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
MSnI/O[15:0] Through
Dual PLA
40
33
ns
PLACLK MSnI/O[15:0] See Note 3. 36 30 ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
Note 3: This applies to signal paths from registered outputs within the Dual PLA that are internally
connected to the Input Selectors of the Dual PLA.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
TTL-Level Interface
98 March 1997 Infinite Technology Corporation
Phone: 972-437-7800
AC Characteristics (Continued)
Configuration Modes
Parameter From To Conditions -70 -100 Unit
(Input) (Output) Min Max Min M ax
tCO
Clock to
Output
Delay
Time
PLACLK PACK Active
Config.
Mode
18
14
ns
tOE PGM0, PGM1 PACK 20 15 ns
Output
Enable
Time
PGM0, PGM1 MSnI/O[15:0],
PLAI/O[7:0]
50
40
ns
tOD PGM0, PGM1 PACK 20 15 ns
Output
Disable
Time
PGM0, PGM1 MSnI/O[15:0],
PLAI/O[7:0]
90
70
ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
5 V CMOS-Level Interface
Infinite Technology Corporation March 1997 99
Phone: 972-437-7800
5 V CMOS-Level Interface Options (Preliminary
Specification)
Recommended Operating Conditions
Symbol Parameter Min Max Unit
VDD Supply voltage 4.75 5.25 V
VIH Input HIGH Level 0.7*VDD V
DD+0.3 V
VIL Input LOW Level -0.3 0.2*VDD V
TA Ambient Temperature 0 70 °C
Symbol Parameter -70 -100 Unit
Min
M
ax Min
M
ax
fCLOCK Clock Frequency MS0CLK, MS1CLK, MS2CLK,
MS3CLK 0 70 0 100
PLACLK External feedback 0 31 0 40
Normal Mode Internal feedback 0 70 0 100 MHz
See Note 1. No feedback 0 83 0 111
PLACLK Active Configuration 0 20 0 25
tWH High-level Clock
Pulse Width MS0CLK, MS1CLK, MS2CLK,
MS3CLK 6.5 4
ns
PLACLK 6 4
tWL Low-level Clock
Pulse Width MS0CLK, MS1CLK, MS2CLK,
MS3CLK 6.5 4
ns
PLACLK 6 4
Note 1: fCLOCK (external feedback) = 1/(tSU + tCO), where tCO is from the registered PLAI/O output
configuration.
f
CLOCK (internal feedback) is measured using internal registers and applies to signal paths from
registered outputs within the Dual PLA that are internally connected to the Input Selectors of the
Dual PLA.
f
CLOCK (no feedback) = 1/(tWH + tWL)
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
5 V CMOS-Level Interface
100 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Recommended Operating Conditions (Continued)
Normal Operating Mode
Parameter From To Test -70 -100 Unit
(Input) (Input) C o nditions Min Max Min Max
tSU
Setup
Time
MSnI/O[15:0],
MS0CTRL[1:0],
BUS4IN[15:0]
MS0CLK
MSnI/O[15:0],
MS1CTRL[1:0],
BUS4IN[15:0]
MS1CLK
8
6
ns
MSnI/O[15:0],
MS2CTRL[1:0],
BUS4IN[15:0]
MS2CLK
MSnI/O[15:0],
MS3CTRL[1:0],
BUS4IN[15:0]
MS3CLK
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
PLACLK
12
9
ns
tH
Hold
Time
MS0CLK MSnI/O[15:0],
MS0CTRL[1:0],
BUS4IN[15:0]
MS1CLK MSnI/O[15:0],
MS1CTRL[1:0],
BUS4IN[15:0]
4
3
ns
MS2CLK MSnI/O[15:0],
MS2CTRL[1:0],
BUS4IN[15:0]
MS3CLK MSnI/O[15:0],
MS3CTRL[1:0],
BUS4IN[15:0]
PLACLK BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
0
0
ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
5 V CMOS-Level Interface
Infinite Technology Corporation March 1997 101
Phone: 972-437-7800
Recommended Operating Conditions (Continued)
Active Configuration Mode
Parameter From To Test -70 -100 Unit
(Input) (Input) Conditions Min Max M in Max
tSU PRDY PLACLK 3 2 ns
Setup
Time BUS4IN[15:0] PLACLK 8 6 ns
tH PLACLK PRDY 2 2 ns
Hold
Time PLACLK BUS4IN[15:0] 0 0 ns
DC Characteristics
Symbol Parameter Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage VDD = Min, IOH = -4mA VDD-0.7 V
V
DD = Min, IOH = -10µA VDD-0.1 V
VOL Output LOW Voltage VDD = M in, IOL = 4mA 0.4 V
V
DD = Min, IOL = 10µA 0.1 V
lIH Input HIGH
Current TMS , TDI,
PLACLK,
MSnCLK,
TCK
VDD = Max,
VIN = VDD 10 µA
Other inputs 100 µA
lIL Input LOW
Current TMS , TDI VDD = M ax,
VIN = 0 V -100 µA
Other inputs -10 µA
lOZH Off-State Output Current
HIGH VDD = Max
VOUT = VDD 100 µA
lOZL Off-State Output Current
LOW VDD = Max
VOUT = 0 V -10 µA
ISC HIGH-State Output Short
Circuit Current VDD = Max, VOUT = 0.5V,
TA = 25°C See Note 2. -30 -135 mA
IDD V
DD Supply Current,
Dynamic VIN = 0V or VDD, V DD = Max,
f = 25MHz, Outputs open mA
IDDS V
DD Supply Current, Static VIN = 0V or VDD, VDD = Max,
f = 0MHz, Outputs open mA
CIN Input Capacitance TA = 25°C, VDD = 5.0V,
f = 1 MHz 5 pF
COUT Output Capacitance TA = 25°C, VDD = 5.0V,
f = 1 MHz 8 pF
MSnCLK refers to any of MS0CLK, MS1CLK, MS2CLK, or MS3CLK.
Note 2: Only one output should be tested at a time and the duration of the short circuit should not
exceed one second.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
5 V CMOS-Level Interface
102 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
AC Characteristics
Normal Operating Mode
Parameter From To Conditions -70 -100 Unit
(Input) (Output) Min Max M in Max
tCO
Clock to
Output
MS0CLK MS0I/O[15:0],
MS0SEND,
MS0AWAIT
Delay
Time MS1CLK MS1I/O[15:0],
MS1SEND,
MS1AWAIT
27
17
ns
MS2CLK MS2I/O[15:0],
MS2SEND,
MS2AWAIT
MS3CLK MS3I/O[15:0],
MS3SEND,
MS3AWAIT
PLACLK PLAI/O[7:0]
registered
PLAI/O output
See Note 3.
20
16
ns
combinatorial
PLAI/O output 32 26 ns
tPD
Prop.
Delay
Time
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
PLAI/O[7:0] combinatorial
PLAI/O output
26 22 ns
tOE MS0OE MS0I/O[15:0]
Output MS1OE MS1I/O[15:0] 27 22 ns
Enable MS2OE MS2I/O[15:0]
Time MS3OE MS3I/O[15:0]
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
MSnI/O[15:0] Through Dual
PLA
42
35
ns
PLACLK MSnI/O[15:0] See Note 3. 38 32 ns
tOD MS0OE MS0I/O[15:0]
Output MS1OE MS1I/O[15:0] 27 22 ns
Disable MS2OE MS2I/O[15:0]
Time MS3OE MS3I/O[15:0]
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
MSnI/O[15:0] Through Dual
PLA
42
35
ns
PLACLK MSnI/O[15:0] See Note 3. 38 32 ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
Note 3: This applies to signal paths from registered outputs within the Dual PLA that are internally
connected to the Input Selectors of the Dual PLA.
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
5 V CMOS-Level Interface
Infinite Technology Corporation March 1997 103
Phone: 972-437-7800
AC Characteristics (Continued)
Configuration Modes
Parameter From To Conditions -70 -100 Unit
(Input) (Output) Min Max Min M ax
tCO
Clock to
Output
Delay
Time
PLACLK PACK Active
Config.
Mode
20
16
ns
tOE PGM0, PGM1 PACK 22 17 ns
Output
Enable
Time
PGM0, PGM1 MSnI/O[15:0],
PLAI/O[7:0]
53
42
ns
tOD PGM0, PGM1 PACK 22 17 ns
Output
Disable
Time
PGM0, PGM1 MSnI/O[15:0],
PLAI/O[7:0]
93
72
ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
3.3 V CMOS-Level Interface
104 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
3.3 V CMOS-Level Interface Options (Preliminary Specification)
Recommended Operating Conditions
Symbol Parameter Min Max Unit
VDD Supply voltage 3.0 3.6 V
VIH Input HIGH Level 0.7*VDD V
DD+0.3 V
VIL Input LOW Level -0.3 0.2*VDD V
TA Ambient Temperature 0 70 °C
Symbol Parameter -40 -60 Unit
Min
M
ax Min
M
ax
fCLOCK Clock Frequency MS0CLK, MS1CLK, MS2CLK,
MS3CLK 0 40 0 60
PLACLK External feedback 0 20 0 25
Normal Mode Internal feedback 0 40 0 60 MHz
See Note 1. No feedback 0 45 0 66
PLACLK Active Configuration 0 10 0 15
tWH High-level Clock
Pulse Width MS0CLK, MS1CLK, MS2CLK,
MS3CLK 11 7.5
ns
PLACLK 10 7.5
tWL Low-level Clock
Pulse Width MS0CLK, MS1CLK, MS2CLK,
MS3CLK 11 7.5
ns
PLACLK 10 7.5
Note 1: fCLOCK (external feedback) = 1/(tSU + tCO), where tCO is from the registered PLAI/O output
configuration.
f
CLOCK (internal feedback) is measured usi ng intern al registers and applies to signal paths from
registered outputs within the Dual PLA that are internally connected to the Input Selectors of the
Dual PLA.
f
CLOCK (no feedback) = 1/(tWH + tWL)
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
3.3 V CMOS-Level Interface
Infinite Technology Corporation March 1997 105
Phone: 972-437-7800
Recommended Operating Conditions (Continued)
Normal Operating Mode
Parameter From To Test -40 -60 Unit
(Input) (Input) C o nditions Min Max Min Max
tSU
Setup
Time
MSnI/O[15:0],
MS0CTRL[1:0],
BUS4IN[15:0]
MS0CLK
MSnI/O[15:0],
MS1CTRL[1:0],
BUS4IN[15:0]
MS1CLK
14
10
ns
MSnI/O[15:0],
MS2CTRL[1:0],
BUS4IN[15:0]
MS2CLK
MSnI/O[15:0],
MS3CTRL[1:0],
BUS4IN[15:0]
MS3CLK
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
PLACLK
20
15
ns
tH
Hold
Time
MS0CLK MSnI/O[15:0],
MS0CTRL[1:0],
BUS4IN[15:0]
MS1CLK MSnI/O[15:0],
MS1CTRL[1:0],
BUS4IN[15:0]
7
5
ns
MS2CLK MSnI/O[15:0],
MS2CTRL[1:0],
BUS4IN[15:0]
MS3CLK MSnI/O[15:0],
MS3CTRL[1:0],
BUS4IN[15:0]
PLACLK BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
0 0 ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
3.3 V CMOS-Level Interface
106 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Recommended Operating Conditions (Continued)
Active Configuration Mode
Parameter From To Test -40 -60 Unit
(Input) (Input) C o nditions Min Max Min Max
tSU PRDY PLACLK 5 3 ns
Setup
Time BUS4IN[15:0] PLACLK 14 10 ns
tH PLACLK PRDY 3 3 ns
Hold
Time PLACLK BUS4IN[15:0] 0 0 ns
DC Characteristics
Symbol Parameter Test Conditions Min Typ Max Unit
VOH Output HIGH Voltage VDD = Min, IOH = -2mA VDD-0.7 V
V
DD = Min, IOH = -10µA VDD-0.1 V
VOL Output LOW Voltage VDD = M in, IOL = 2mA 0.4 V
V
DD = Min, IOL = 10µA 0.1 V
lIH Input HIGH
Current TMS , TDI,
PLACLK,
MSnCLK,
TCK
VDD = Max,
VIN = VDD 10 µA
Other inputs 100 µA
lIL Input LOW
Current TMS , TDI VDD = M ax,
VIN = 0 V -100 µA
Other inputs -10 µA
lOZH Off-State Output Current
HIGH VDD = Max,
VOUT = VDD 100 µA
lOZL Off-State Output Current
LOW VDD = Max,
VOUT = 0 V -10 µA
ISC HIGH-State Output Short
Circuit Current VDD = Max, VOUT = 0.5V,
TA = 25°C See Note 2. -20 -135 mA
IDD V
DD Supply Current,
Dynamic VIN = 0V or VDD, V DD = Max,
f = 25MHz, Outputs open mA
IDDS V
DD Supply Current, Static VIN = 0V or VDD, VDD = Max,
f = 0MHz, Outputs open mA
CIN Input Capacitance TA = 25°C, VDD = 3.3V,
f = 1 MHz 5 pF
COUT Output Capacitance TA = 25°C, VDD = 3.3V,
f = 1 MHz 8 pF
MSnCLK refers to any of MS0CLK, MS1CLK, MS2CLK, or MS3CLK.
Note 2: Only one output should be tested at a time and the duration of the short circuit should not
exceed one second.
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
3.3 V CMOS-Level Interface
Infinite Technology Corporation March 1997 107
Phone: 972-437-7800
AC Characteristics
Normal Operating Mode
Parameter From To Conditions -40 -60 Unit
(Input) (Output) Min Max M in Max
tCO
Clock to
Output
MS0CLK MS0I/O[15:0],
MS0SEND,
MS0AWAIT
Delay
Time MS1CLK MS1I/O[15:0],
MS1SEND,
MS1AWAIT
42
33
ns
MS2CLK MS2I/O[15:0],
MS2SEND,
MS2AWAIT
MS3CLK MS3I/O[15:0],
MS3SEND,
MS3AWAIT
PLACLK PLAI/O[7:0]
registered
PLAI/O output 30 24 ns
combinatorial
PLAI/O output
See Note 3.
50
40
ns
tPD
Prop.
Delay
Time
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
PLAI/O[7:0] combinatorial
PLAI/O output
40
33
ns
tOE MS0OE MS0I/O[15:0]
Output MS1OE MS1I/O[15:0] 42 33 ns
Enable MS2OE MS2I/O[15:0]
Time MS3OE MS3I/O[15:0]
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
MSnI/O[15:0] Through Dual
PLA
67
55
ns
PLACLK MSnI/O[15:0] See Note 3. 60 50 ns
tOD MS0OE MS0I/O[15:0]
Output MS1OE MS1I/O[15:0] 42 33 ns
Disable MS2OE MS2I/O[15:0]
Time MS3OE MS3I/O[15:0]
BUS4IN[15:0],
PLAIN[7:0],
PLAI/O[7:0]
MSnI/O[15:0] Through Dual
PLA
67
55 ns
PLACLK MSnI/O[15:0] See Note 3. 60 50 ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
Note 3: This applies to signal paths from registered outputs within the Dual PLA that are internally
connected to the Input Selectors of the Dual PLA.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
3.3 V CMOS-Level Interface
108 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
AC Characteristics (Continued)
Configuration Modes
Parameter From To Conditions -40 -60 Unit
(Input) (Output) Min Max M in Max
tCO
Clock to
Output
Delay
Time
PLACLK PACK Active
Config.
Mode
30
23
ns
tOE PGM0, PGM1 PACK 33 25 ns
Output
Enable
Time
PGM0, PGM1 MSnI/O[15:0],
PLAI/O[7:0]
100
65
ns
tOD PGM0, PGM1 PACK 33 25 ns
Output
Disable
Time
PGM0, PGM1 MSnI/O[15:0],
PLAI/O[7:0]
140
110
ns
MSnI/O[15:0] refers to any of MS0I/O[15:0] , MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0].
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 109
Phone: 972-437-7800
Timing Di agrams
A common set of t iming diag rams is used for the TTL-le vel, 5 V CMOS-level,
and 3 .3 V CMOS-level interface options of the RAD5A4. Vo l tage levels that
apply to each of the th ree i nterface options are in the table below:
Voltage RAD5A4 Interface Options
TTL 5 V CMOS 3.3 V CMOS
VIH 3.0 V VDD V
DD
VIL 0.0 V 0.0 V 0.0 V
VT 1.5 V 50% VDD 50% VDD
VTHZ VOH - 0.5 V VOH - 0.5 V VOH - 0.3 V
VTLZ VOL + 0.5 V VOL + 0.5 V VOL + 0.3 V
V
IH
V
IL
90%
10%
≤
2ns
Inputs
All Input Signals
≤
2ns
10%
90%
V
IH
V
IL
V
T
t
WL
t
WH
1/f
CLOCK
90%
10%
≤
2ns
Clock Inputs
Clock Inputs
V
T
V
T
≤
2ns
90%
10%
Input or
I/O Input
Clock Input
V
IH
V
T
V
T
V
T
t
SU
t
H
t
SU
& t
H
Setup and Hold Times
V
IL
V
IH
V
IL
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
110 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Timing Diagrams (Continued)
V
OH
V
OL
t
CO
Clock Input
Output
t
CO
Clock to Output Delay Time
V
IH
V
IL
V
T
V
T
V
IH
t
PD
V
OH
V
OL
Input or
I/O Input
Output
t
PD
Propagation Delay Time
V
IL
V
T
V
T
V
T
V
IH
t
OD
t
OE
V
O
H
V
OL
Input or
I/O Inputs
Output
t
OE
& t
OD
Input to Output Enable/Disable Times
from MSnOE, BUS4IN, PLAIN, or PLAI/O
V
IL
V
T
V
TH
Z
V
T
Hi-Z
V
TLZ
V
T
V
T
V
IH
V
OH
V
OL
PLACLK
Input
Output
t
OE
& t
OD
Input to Output Enable/Disable Times
from PLACLK
t
OD
t
OE
Hi-Z
V
IL
V
T
V
T
V
THZ
V
TLZ
V
T
V
T
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 111
Phone: 972-437-7800
Timing Diagrams (Continued)
t
OE
V
T
Hi-Z
PGM_a
Input
t
OE
& t
OD
Input to Output Enable/Disable Times
from PGM0 or PGM1
PGM_b
Input
PACK
Output
I/O
Outputs
t
OD
V
IL
V
IH
V
IL
V
IH
V
OL
V
OH
V
OL
V
OH
Hi-ZHi-Z t
OE
t
OD
V
T
V
T
V
THZ
V
TLZ
V
THZ
V
T
V
T
V
T
V
T
PGM0 and PGM1 are identical inputs and are represented by PGM_a and PGM_b to
allow a single diagram to represent them. PGM_ a represents the first of PGM0 or PGM1
to change states.
AC Measurement Diagram of the Load Circuit for Output
Output load Test
Condition TTL
5
V CMOS 3.3 V
CMOS
VA 3.5 V VDD V
DD
I1 8 mA 4 mA 2 mA
I2 4 mA 4 mA 2 mA
CL t
PD, tCP, tOE 35 pF 35 pF 35 pF
t
DD 5 pF 5 pF 5 pF
Test Output Transition S1 S2
tCO, tPD H → L open open
L → H open open
tOE Z → H open closed
Z → L closed open
tOD H → Z open closed
L → Z closed open
Output
under
test Test Point
V
A
GND
S2
S1
I
1
I
2
C
L
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
112 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Transiti oni ng between Active and Normal Operating Modes
During Active Configuration (PGM0 = PGM1 = HIGH), the Controln[1:0]
circuitry is disabled. The Controln[1 :0] circuitry remains disabled after Active
Configuration ends until the first LOW to HIGH (l) transition of Controln[1]
activates the Controln[1:0] circuitry to the SetSequence0 or SetSequence2
command on the following MSnCLK (l) clock pulse. Once activated , the
Controln[1:0] circuitry will remain active until the next Active Configuration
Mode occurs or power is removed from VDD.
As soon as Active Configuration Mode ends (the first of PGM0 or PGM1 goes
LOW), the MacroSequencer begins execution of LIW0. MacroSequencern will
repeatedly execute LIW0 on each MSnCLK cycle as long as the Controln[1:0]
circuitry is disabled. After activation, the Controln[1:0] circuitry will respond
correctly to each of the four operating commands listed in the t able below:
Controln
[1:0] Command Description
0 0 Run Normal Operating Condition
0 1 Continue Reset Send and Await registers.
1 0 SetSequence0 The Program Counter is set to ‘0’.
Resets the Send and Await registers.
This must be asserted for at l east two cycles.
1 1 SetSequence2 The Program Counter is set to ‘2’.
Resets the Send and Await registers.
This must be asserted for at l east two cycles.
Example MacroSequencer Instructions Programmed for 2 Sequences
; LIW0
jump sequence0 ; somet hing to execute repeat edly, no read or write operations
; LIW 1
indexdirect or indexmode ; operatio ns use d to set up the inde x r eg ister s fo r 1s t seque nce
; LIW 2
indexdirect or indexmode ; operatio ns use d to set up the inde x r eg ister s fo r 2nd s eque nce
;LIW 3 ; continue second sequence of operations
Example MacroSequencer Instructions Programmed for 1 Sequence
; LIW0
indexdirect or indexmode ; something to execute repeatedly, no read or write operations
;LIW 1 ; continue sequence of operations
The index registers must be initialized befo re any read or write operations. The
use of indexdirect and indexmode should precede any read or write operations.
If the 1-port or 3-port memories are not used, then any operation can appear in
LIW0 and/or LIW2 .
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 113
Phone: 972-437-7800
Waveforms Either MSnCtrl[1:0] pins or PLACtrln[1:0] may be used for the Controln[1:0]
MacroSequencer inputs. When using PLACtrln [1:0] signals, allow two clock
cycles for latency. There is no latency with the MSnCtrl[1:0] signals. Under
Dual PLA control, both PLACtrln[1:0] signals are LOW when Active
Configuration ends. Wh en P LACLK and MSnCLK are connected together, a
minimum of two clock cycles will occur after Active Configuration before
Controln[1] will first go HIGH to activate the Controln[1:0] circuitry.
Input Voltage waveforms for transitioning between Active Configuration Mode
and Normal Operating Mode using the MSnCtrl[1:0] pins to provide the
Controln[1:0 ] signal s are shown belo w. PGM0 and PGM1 are referenced as
PGM_a and PGM_b because either pin may change first, or they may be
changed at the same time.
t
REC2
t
REC1
t
SU
V
T
V
T
V
T
V
T
PGM_a
Input
PGM_b
Input
MSnCtrl[1]
Input
MSnCtrl[0]
Input
MSnCLK
Input
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
Operating Mode Transitioning
Hi-Z
I/O
Outputs V
OL
V
OH
t
OE
t
OD
V
THZ
V
TLZ
V
T
V
T
V
T
V
T
V
T
Use tREC1 = tREC2 = 20 ns minimum. All times on this diagram are independent
of MSnCLK frequency within device specifications.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
114 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
(Top View)
NC
NC
PRDY
PACK
VSS
PLACLK
MS2CTRL0
MS2CTRL1
MS2OE
MS2CLK
VSS
MS2SEND
MS2AWAIT
VDD
MS2I/O0
MS2I/O1
MS2I/O2
MS2I/O3
VSS
MS2I/O4
MS2I/O5
MS2I/O6
MS2I/O7
VDD
MS2I/O8
MS2I/O9
MS2I/O10
MS2I/O11
VSS
VSS
MS2I/O12
MS2I/O13
MS2I/O14
MS2I/O15
VDD
MS3CTRL0
MS3CTRL1
MS3OE
MS3CLK
VSS
MS3SEND
MS3AWAIT
NC
NC
NC
NC
MS3I/O0
MS3I/O1
VDD
MS3I/O2
MS3I/O3
MS3I/O4
MS3I/O5
VSS
MS3I/O6
MS3I/O7
MS3I/O8
MS3I/O9
VDD
MS3I/O10
MS3I/O11
MS3I/O12
MS3I/O13
VSS
MS3I/O14
MS3I/O15
MS1I/O15
MS1I/O14
VSS
MS1I/O13
MS1I/O12
MS1I/O11
MS1I/O10
VDD
MS1I/O9
MS1I/O8
MS1I/O7
MS1I/O6
VSS
MS1I/O5
MS1I/O4
MS1I/O3
MS1I/O2
VDD
MS1I/O1
MS1I/O0
NC
NC
NC
NC
VSS
TDO
VSS
TCK
MS0CTRL0
MS0CTRL1
MS0OE
MS0CLK
VSS
MS0SEND
MS0AWAIT
VDD
MS0I/O0
MS0I/O1
MS0I/O2
MS0I/O3
VSS
MS0I/O4
MS0I/O5
MS0I/O6
MS0I/O7
VDD
MS0I/O8
MS0I/O9
MS0I/O10
MS0I/O11
VSS
VSS
MS0I/O12
MS0I/O13
MS0I/O14
MS0I/O15
VDD
MS1CTRL0
MS1CTRL1
MS1OE
MS1CLK
VSS
MS1SEND
MS1AWAIT
NC
NC
PLAI/O7
PLAI/O6
VSS
PLAI/O5
PLAI/O4
PLAI/O3
PLAI/O2
VDD
PLAI/O1
PLAI/O0
PLAIN7
PLAIN6
PLAIN5
PLAIN4
PLAIN3
PLAIN2
PLAIN1
PLAIN0
TMS
TDI
NC
NC
NC
NC
PGM0
PGM1
BUS4IN0
BUS4IN1
BUS4IN2
BUS4IN3
BUS4IN4
BUS4IN5
BUS4IN6
BUS4IN7
BUS4IN8
BUS4IN9
VDD
BUS4IN10
BUS4IN11
BUS4IN12
BUS4IN13
VSS
BUS4IN14
BUS4IN15
NC = No internal connection
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 115
Phone: 972-437-7800
RAD5A4 PIN Description
Foll owing is a complete and detai led listi ng of each of th e RAD5A4 pin
connections sorted by function.
Power Supply Pins
VDD
Symbol Type No. of Pins Pin Number
VDD Positive
Power
Supply
12 14, 24, 35, 49, 59, 74, 84,
98, 109, 119, 147, 162
This device must have all VDD pins connected to insure proper operation.
VSS
Symbol Type No. of Pins Pin Number
VSS Power
Supply:
Ground
19 5, 11, 19, 29, 30, 40, 54,
64, 69, 79, 93, 103, 104,
114, 122, 128, 130, 152,
157
This device must have all VSS pins connected to insure proper operation.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
116 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
MacroSequencer Pins
Pi n Types Summary of MacroSequencer Pins
MS0 MS1 MS2 MS3
I/O Pins:
Symbol MS0I/O[15:0] MS1I/O[15:0] MS2I/O[15:0] MS3I/O[15:0]
No of Pins 16 16 16 16
Pin Numbers 99, 100, 101, 102,
105, 106, 107,
108, 110, 111,
112, 113, 115,
116, 117, 118
67, 68, 70, 71,
72, 73, 75, 76,
77, 78, 80, 81,
82, 83, 85, 86
34, 33, 32, 31,
28, 27, 26, 25,
23, 22, 21, 20,
18, 17, 16, 15
66, 65, 63, 62,
61, 60, 58, 57,
56, 55, 53, 52,
51, 50, 48, 47
Control Pins:
Symbol MS0CTRL[1:0] MS1CTRL[1:0] MS2CTRL[1:0] MS3CTRL[1:0]
No of Pins 2 2 2 2
Pin Numbers 125, 126 96, 97 8, 7 37, 36
AWAIT Pins:
Symbol MS0AWAIT MS1AWAIT MS2AWAIT MS3AWAIT
No of Pins 1 1 1 1
Pin Number 120 91 13 42
SEND Pins:
Symbol MS0SEND MS1SEND MS2SEND MS3SEND
No of Pins 1 1 1 1
Pin Number 121 92 12 41
Output Enable Pins:
Symbol MS0OE MS1OE MS2OE MS3OE
No of Pins 1 1 1 1
Pin Number 124 95 9 38
Clock Pins:
Symbol MS0CLK MS1CLK MS2CLK MS3CLK
No of Pins 1 1 1 1
Pin Number 123 94 10 39
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 117
Phone: 972-437-7800
MacroSequencer I/O Pins
Output signals from the MacroSequencers are multiplexed with the
corresponding MSnI/O input pins to provide the signals for the busns. The
busn inputs may be from either the MacroSequencer(n)’s Output Register,
OutRegA, or from the MSnI/O pins.
MacroSequencer Control I nput Pins
The MacroSequencer Control signal inputs provide direct control to initialize
MacroSequencer(n) operation when the device is configured to use them.
MacroSequencer (n) Control Signals
MSnCTRL
[0] MSnCTRL
[1] Result
0 0 Run
0 1 Continue,
Reset Send and Await signals
1 0 SetSequence0
1 1 SetSequence2
These pins are not used if the MacroSequencer Control Signals are from the
Dual PLA.
MacroSequencer AWAIT Output Pi ns
The Await signal is used by each MacroSequencer(n) to indicate an Await state.
MacroSequencer(n) AWAIT Signal
MSnAWAIT Result
0 Normal Operation of MacroSequencer
1 MacroSequencer has stalled and executes an
instruction repeatedly until a Continue control state
is encountered.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
118 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
MacroSequencer SEND Output Signals
The Send signal is u s ed by each MacroS equencer(n) to indicate a Send state.
MacroSequencer (n) SEND Signal
MSnSEND Result
0 Normal Operation of MacroSequencer
1 Normal Operation continues, but SEND remains a
“1” until a Continue control state is encountered.
MacroSequencer Output Enabl e Input Pins
The MSnOE pins provide direct control of the enable/disable functions for the
MSnI/O outputs when the device is configured to use them. MacroSequencer
configuration bits select whether the MSnOE pins are active-HIGH or active-
LOW.
These pin s are not used if the oepla[n] Signal s are fro m th e Dual PLA.
MacroSequencer Clock Signal s MSnCLK
The MacroSequencer Clock Pins provide positive edge clock signals for the
MacroSequencers. Each MacroSequencer has its own independent clock
signal. Th e MacroSequencer clock pins may be externally tied together t o use
the same clock sources.
Bus 4 Input Pins
Symbol Type No. of Pins Pin Number
BUS4IN[15:0] Input 16 155, 156, 158, 159, 160,
161, 163, 164, 165, 166,
167, 168, 169, 170, 171,
172
During normal operation mode, these pins drive:
• PLA Input Bus4[15:0]
• MacroSequencer data Bus4[15:0]
During active configuration, these pins are used to provide input data for the
configuration process.
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 119
Phone: 972-437-7800
PLA Pins
PLAI/O[7:0]
Symbol Type No. of Pins Pin Number
PLAI/O[7:0] I/O 8 154, 153, 151, 150, 149,
148, 146, 145
Input/Output for Dual PLA. They connect to:
• PLA Input PLAI/O[7:0]
• PLA1 Output Signals : Comb inatorial or Registered Outputs selected by
Configuration Bits
PLAIN[7:0]
Symbol Type No. of Pins Pin Number
PLAIN[7:0] Input 8 144, 143, 142, 141, 140,
139, 138, 137
Inputs to the Dual PLA connecting to PLAIN[7:0]
PLACLK
Symbol Type No. of Pins Pin Number
PLACLK Input 1 6
The PLACLK provides a positive edge clock signal for the Dual PLA and fo r
device configuration.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
120 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Configuration Pins
Symbol:
PGM0 PGM1 PRDY PACK
No. of Pins 1 1 1 1
Pin Number 174 173 3 4
Type Input Input Input Output
Function: Configuration
mode0 Configuration
mode1 Configuration
Ready signal Configuration
Acknowledge
PGM0 and PGM1: Configurat ion Mode Pins
The PGM0 and PGM1 pins are used as inputs to determine the operation mode
of the RAD5A4. They are functio nally identical.
• When both pins are HIGH, the RAD5A4 is in Active Configuration Mode.
In thi s mod e, all I/O out puts are in a high-impedance state, and most internal
registers and flip-flops that are used in normal operation mode are held in an
initialized state. The PACK pin is enabled fo r output.
• When they are bo th LOW, the device and all I/O pins are in Normal
Operating Mode, and PACK is in a high-impedance stat e. No configu r ation
of the device may occur.
• When one is LOW and one is HIGH (either one), the device is in a Passive
Configuration Mode and all I/O outputs and PACK are in a high-imp edance
state. No configuration of the device may occur.
PRDY: Configurat ion Ready Signal
During Active Configuration Mode, external circuitry uses the PRDY input to
indicate when a configuration data word is present on BUS4IN[15:0] pins and
ready to be loaded into the RAD5A4.
PACK: Configuration Acknowledge
During Active Configuration Mode, PACK signals from the RAD5A4 when
the next configuration action may begin.
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 121
Phone: 972-437-7800
Scan Pins
Symbol:
TCK TMS TDI TDO
No. of Pins 1 1 1 1
Pin Number 127 136 135 129
Type Input Input Input Output
Function: Test Clock
Input Test Mode
Select Input Test Data Input Test Data
Output
The IEEE 1149.1a Boundary Scan Protocol provides a low pin count method
for testing systems specified in the IEEE Standard Test Access Port an d
Boundary Scan Architecture, (c) 1993, Institute of Electrical and Electronics
Engineers, Inc., New York, ISBN 1-55937-350-4.
The Boundary Scan Protocol uses a serial protocol involving four special
purpose pins: TDI, TDO, TCK, TMS, which are known as the TAP (Test
Access Port) pins. The TAP pins allow the state of all act ive logic sign als to be
examined and for the state of most registers in the four MacroSequencers to be
examined.
TCK: Test Clock Input
The TCK pin is the test access port clock which serves as the scan protocol clock.
TMS: Test Mode Select I nput
The T MS pin is the test m ode sele ct input. It is sam pled on the rising edg e of TC K.
TDI: Test Data Input
The TDI is sampled on the rising edge of TCK.
TDO: Test Data Output
Changes on TDO occur only on the falling edge of TDK.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
122 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Package Characteristics
Operating clock frequency and package characteristics affect power dissipatio n
and junction temperature.
Power Dissipation Versus Clock Frequency
Power dissipation of a RAD5A4 can vary over a wide range depending on
MacroSequencer specific algorithms, clock frequency, number and frequency
of outputs switching, output loading, supply voltage and interface type.
Graphical representation of power dissipation versus clock frequency for
represent at ive RAD5A4 device applications are shown here:
Estimated RAD 5A4 Power Dissipat ion versus Clock Input
Frequency for Two Typical Applications: TTL-Inter face
0
500
1000
1500
2000
2500
0 20406080100
fCLK - Clock Frequency (MHz)
PD- Power Dissipation (mW)
VDD = 5 V
TA = 25°C
CL = 50 pF
4 MacroSequencers Switching and 32 I/O
Outputs Switching at 25% fCLK Frequency
1 MacroSequencer Switching and 16 I/O
Outputs Switching at 25% fCLK Frequency
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 123
Phone: 972-437-7800
Estimated RAD 5A4 Power Dissipat ion versus Clock Input
Frequency for Two Typical Applications: 5 V CMOS-Inter face
0
500
1000
1500
2000
2500
3000
3500
0 102030405060708090100
fCLK - Clock Frequency - MHz
PD- Power Dissipation (mW)
4 MacroSequencers Switching and 32 I/O
Outputs at Switching at 25% fCLK Frequency
1 MacroSequencer Switching and 16 I/O
Outputs Switching at 25% fCLK Frequency
VDD = 5 V
TA = 25°C
CL = 50 pF
Estimated RAD 5A4 Power Dissipat ion versus Clock Input
Frequency for Typical Applications: 3.3 V C M OS-Inter face
0
100
200
300
400
500
600
700
800
900
0 102030405060
fCLK - Clock Frequency (MHz)
PD- Power Dissipation (mW)
4 MacroSequencers Switching and 32 I/O
Outputs Switching at 25% fCLK Frequency
1 MacroSequencer Switching and 16 I/O
Output Switeching at 25% fCLK Frequency
VDD = 3.3 V
TA = 25°C
CL = 50 pF
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
124 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Thermal Characteristics
Virtual junction temperature of the chip may be estimated using thermal
characterist ics of the devi ce package and the application s system and power
dissipation of the device in the application.
Calculating Junction Temperature
TJ = TA + PD * RθJA
TJ = TC + PD * R θJC
where:
TJ = Virtual junction temperature
TA = Free air (ambient) temperatu r e
TC = Case temperature
PD = Average device power dissipation
RθJA = Junction-to-air (ambient) thermal resistance characteristic
RθJC = Ju nction - to-case thermal resistan ce characteristic
Package Thermal characteristics for RθJA are shown with two different
air-flow rates.
Package
Rθ
θθ
θJC R
θ
θθ
θJA
in still air Rθ
θθ
θJA
300 ft/min
Unit
TQFP 2.2 38 32 °C/W
Power TQFP 0.6 23 20 °C/W
Maximum Power Dissipation
Maximum junction temperature allowable for the RAD5A4 is 150°C.
However, a maximum junction temperature of 140°C is recommended for
continuous operation.
PD = (TJ - TC) / RθJA
where:
PD = Average device power dissipation
TJ = Virtual junction temperature
TC = Case Temperature
RθJA = Junction-to-air (ambient) thermal resistance characteristic
A sample calculation of the maximum power dissipation for a power TQFP
package in still air at recommended operating conditions is as follows:
Max. junction temp (°C) - Max. commercial temp
(°C)
R
θ
JA
(°C/W)
140°C - 70°C
23°C/W 3.04W
==
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 125
Phone: 972-437-7800
Clock Freque ncy Versus Temperature
Switchin g t imes increase as junction temperature increases; therefore maximum
clock frequ ency decreases with increased junction temperatur e. Optimum
device speed performance is achieved when chi p junct ion temperature rise is
minimized for a given application.
Both the TQFP package and t he Power TQFP package h ave identi cal
mechanical d i mensi ons and mechanically may be used int erchangeably. The
TQFP package may be used in lower power and/or lower performance
applications. The Power TQFP package may be used in applications requiring
higher power and/or higher performance. A heat sink may be attached directly
to the metal slug of the Power TQFP package.
RAD5A4
Device Specifications Preliminary Reconfigurable Arithmetic Datapath
126 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Package Mechanical Details
Thin Quad Flat Pack (TQFP), 176 pins
DD1
E
E1
A2
LaA
A1
be
0 - 7°
Top View
E
2
D
2
PIN 1
Identification
89
88
45
44
1
176
133
132
Symbol Minimum Nominal Maximum Unit Notes
A 1.60 mm
A1 0.05 0.15 mm
A2 1.35 1.40 1.45 mm
D 26.00 BSC mm
D1 24.00 BSC mm
E 26.00 BSC mm
E1 24.00 BSC mm
L 0.45 0.60 0.75 mm
e 0.50 BSC mm Lead pitch
b 0.17 0.22 0.27 mm Lead width
a 0.09 0.16 mm Lead thickness
This package conforms to JEDEC specification MO-136, variation BV.
RAD5A4
Reconfigurable Arithmetic Datapath Preliminary Device Specifications
Infinite Technology Corporation March 1997 127
Phone: 972-437-7800
Power TQFP, 176 pins
DD1
E
E1
A2
LaA
A1
be
3.127 x 45° CHAMFER
4 PLACES
PIN 1
Identification
89
88
Hy
Hx
0 - 7°
E
2
D
2
Top View
45
44
1
176
133
132
~
Embedded Heat Sink
Symbol Minimum Nominal Maximum Unit Notes
A 1.60 mm
A1 0.05 0.15 mm
A2 1.35 1.40 1.45 mm
D 26.00 BSC mm
D1 24.00 BSC mm
E 26.00 BSC mm
E1 24.00 BSC mm
Hx 19.00 REF 19.40 REF 20.00 REF mm
Hy 19.00 REF 19.40 REF 20.00 REF mm
L 0.45 0.60 0.75 mm
e 0.50 BSC mm Leadpitch
b 0.17 0.22 0.27 mm Lead width
a 0.09 0.16 mm Lead thickness
This package conforms to JEDEC specification MO-136, variation BV.
RAD5A4
Revision History Reconfigurable Arithmetic Datapath
128 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Revision History
This data book replaces:
RAD5A4 Data Book May 1996
RAD5A4 Data Book March 1996
RAD5A4 Data Book February 1996
RAD5A4 Data Book January 1996
RAD5A4 Data Book December 1995
RAD5A4 Data sheet April 1995
RAD5A4
Reconfigurable Arithmetic Datapath Terms & Definitions
Infinite Technology Corporation March 1997 129
Phone: 972-437-7800
Terms & Definitions
Acronyms, terms, and definitions useful in RAD5A4 discussions will be listed
in this chapter.
Acronyms
Acronym Meaning
DW Data word
DWP Preamble data word
DWmax Last d at a word in a dat a packet
High-Z High-Impedance
MIMD Multiple Instructions Multiple Datapath
PLA Programmable Logic Array
InRegA Input Register A
InRegB Input Register B
InRegC Input Register C
LIW Long Instruction Word
MAC Multiply-Accumulate or Multiplier-Accumu lator
MIMD Multiple Instructions on Multiple Data pa ths
MS MacroSequencer
RAD5A4
Terms and Definitions Reconfigurable Arithmetic Datapath
130 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Glossary
A
Active Configuration Mode
Device can be configured in this mode.
PGM0 and PGM1 are HIGH.
Adder Status Signals
Equal, Overflow, Sign,and Carry Status bits
from the Adder provided for conditional
branches.
Algorithm
A sequence of arithmetic and control
functions.
AND Array
Array of AND gates. There are two AND
arrays in the Dual PLA which produce 34
product terms.
Arithmetic Datapath
This term refers to the arithmetic related
elements in the MacroSequencers su ch as the
Multiplier-Accumulator, Shifter, Adder, and
Logic unit.
Asynchronous hand-shaking
Hand-shaking protocol useful when
configuring the RAD5A4 where inputs are
not synchronized with a clock signal.
B
Boundary Scan Path
This is the Scan P ath which relates to the pins
of the RAD5A4. It contains registers
capturing not only the pins, but also output
enable information.
Branch Operations
The MacroSequencer Datapath Controller
supports the following branch operations:
call, return, jump, jumpcounter0,
jumpcounter1, jumpequal, jumpoverflow and
jumpsign. These operations may either
unconditionally or conditionally alter the
state of the Program Counter.
bus0,1,2,3,4
The R AD 5A 4 posses ses f ive 16 bit buses whic h
are tied directly to pins. These buses are known
as bus0, bus1, bus2, bus3, and bus4. The first
four buses also directly connect to the
MacroSequencers. They connect to the pins and
MacroSequencers as follows:
• bus0 connects to MS0I/O and
MacroSequencer 0.
• bus1 connects to MS1I/O and
MacroSequencer 1.
• bus2 connects to MS2I/O and
MacroSequencer 2.
• bus3 connects to MS3I/O and
MacroSequencer 3.
• bus4 connects to BUS4IN.
BUS4IN[15:0]
Bus4 pins to the RAD5A4.
Bypass Register
This is a 1 bit serial register whose purpose is
to bypass the Boundary and other internal
scan paths of the chip.
C
Concurrent processing
This is the simultaneous operation of
processing units ( ie: adder MAC Shifter,
Contro l et c.).
Configuration Bits
There are MacroSequencer and PLA
programmable configuration bits.
Configuration Continue
Configuration status that occurs at the end of
a data packet after the last data word has been
load ed and before the next data packet may
be loaded.
Configuration Data Packet
Set of configuration data words to program a
memory in th e RAD5A4
Configuration Data Wor d
16-bit data words comprising a configuration
data p acket.
RAD5A4
Reconfigurable Arithmetic Datapath Terms and Definitions
Infinite Technology Corporation March 1997 131
Phone: 972-437-7800
Configuration Data Word Counter
Used internally by the RAD5A4 to load the
configuration data words into the correct
memory locations.
Configuration File
File generated by RADware software for
configuring the RAD5A4. When this file is
loaded into the RAD5A4 it is configured.
Configuration Halt
Configuration status that occurs at the end of
a data packet after the last data word has been
loaded from the configuration file.
Configuration Initialization
Configurat ion status that o ccurs at the
beginning of Active Configuration Mode
before the configuration file is loaded.
Configuration Memories
RAD5A4 memories th at can be con figured or
programmed. They include the Dual PLA
memory, and a LIW, 3-port, and 1-port
memory in each of the 4 Macro S equencers.
Constant Input
see intern al signal
Continue
Command sent to the MacroSequencer
Datapath Controller from either external pins
or th e Dual PLA cont rol signals. The
Continue command resets the Send and
Await status signals and allows the program
counter to operate under control of the LIW
sequence.
Control Bus
RAD5A4 internal b us for contro l signals such
as the Send and Await sign als.
Control OR
In the Dual PLA, the Control OR is an OR
array that can produce the control signals to
the Macro Sequencers.
Convolution
Given two discrete time input streams A[ ]
and B[ ], a convolution may be defined as an
output stream C[ ] where
Ck An Bn k
n
[] []* [ ]=−
=−∞
∞
å
The Finite Impulse Response version of this
becomes
Ck An Bn k
nkM
Nk
[] []* [ ]=−
=−
+
å
Counter0, Counter1
These are counters used for loops in the
MacroSequencer Controller.
Note: the above two are the same.
Count down
This is a single bit registe r in the Control
com ponent of each Index Register of the
MacroSe quence r’s Da tapath C ontroller. If it
contains a ‘1’, then the a ddress com ponent w ill
decrement every time its associated mem ory
access port is accessed. If both Count_up and
Count_down c ontain ‘ 0’, the a ddres s is he ld. It
is illega l f or both Count_up and Count_dow n to
both contain ‘ 1’.
Count up
This is a single bit registe r in the Control
com ponent of each Index Register of the
MacroSe quence r’s Da tapath C ontroller. If it
contains a ‘1’, then the a ddress com ponent w ill
increment every time its associated mem ory
access port is accessed. If both Count_up and
Count_down c ontain ‘ 0’, the a ddres s is he ld. It
is illega l f or both Count_up and Count_dow n to
both contain ‘ 1’.
D
Data Bus
Five buses used for carrying data to and from
the MacroSequencers named bus0, bus1,
bus2, bus3, and bus4.
Data Memory
Data Memory is the memory withi n each
RAD5A4 MacroSequencer which may be
used to store data. It is composed of the 1-
port and 3-port Memories.
See also 1-port Memory, 3-port Memory,
Index Register and MacroSequencer entries.
Datapath Controller
Located in each MacroSequencer, a datapath
controller contains the LIW memory,
sequences through the instructions, and
produces LIW control bits for the
MacroSequencer Arithmetic Datapath.
RAD5A4
Terms and Definitions Reconfigurable Arithmetic Datapath
132 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
E
External Signals
There are 7 external input buses; bus0 - bus4
, MSnIO pins and MSPair(nm).
F
Filter
Filters will refer specifically to Finite Impulse
Response (FIR) Filters. These are digital
filters which operate upon a single input data
stream and generate a single output data
stream. They successively operate on a fixed
number of data stream elements in generating
each successive element of the output stream.
Consider a one dimensional FIR filter: Let
A[0,...] represent the input stream data and
B[0,...] represent the output stream data. An
FIR filter consists of two positive integer
constants M and N and a collection of
numbers am[0:M] an d an[ 1:N] such that
B[M+k] = am[0]*A[M+k]+...+am[M]*A[k]
+an[1]*A[k+1]+...+an[N]*A[N+k]
Fixed OR0 and Fixed OR1
The fixed OR arrays found in the Dual PLA.
FPGA
Field programmable gate array
Flags
Single bits us ed f or com m unica tion betw ee n the
Adde r and MS Controlle r as w e ll as the MS
Controller and e ither the PLA or ex ternal pins.
Function
Arithmetic operations performed in input data
to produce output data. ‘Function’ also may
refer to the elements or data blocks found
within the MacroSequencers.
G
H
Handshake
Communication between the RAD5A4 and
external circuitry used during configuration.
I
ID Register
This is a serial register within the JTAG
Boundary Scan Circuit which identifies the
RAD5A4. It contains bits which determine
whether the chip is 5V TTL, 5V CMO S, 3.3V
CMOS, as well as bits which determine
which version of the silicon the part is.
InBusA, InBusB
These are outputs of the Input Selector
destined for the MAC, Adder and the
Logic Unit.
InBusC
This is an output of the Input Selector
destined for the Shifter.
Index
Address or location within the 3-port or 1-
port memory held in Index registers.
Index Register
The index registers hold the memory
addresses for reading and writing data to and
from the 1-port and 3-port Memories.
Each RAD5A4 MacroS equencer co ntains 5
Index Regist e rs. One Index Register is used
for memory access of the 1-port Memory.
Four Index Registers are u sed for access of
the 3-port Memory.
Each Index Register is composed of two
components: A control circuit and address
generation circuit.
Input Register Block
This is made up of both InRegA and InRegB.
Input Selectors - PLA
The input selectors provide selection of
inputs to the arithmetic processing units.
Input Selectors - MacroSequencer
The input selectors provide selection of
inputs to the arithmetic processing units.
InRegA, InRegB
These are two 16 bit registers connected to
external data sources. There are 6 input
buses; bus0 - bus4 and MSPair(nm). An
additional source of data is a constant from
the LIW word. Without an instruction for one
of these 7 sources the register holds previous
contents. Both registers have access to the
same data.
Instruction Memory
RAD5A4
Reconfigurable Arithmetic Datapath Terms and Definitions
Infinite Technology Corporation March 1997 133
Phone: 972-437-7800
The 32 x 48-bit LIW memory within the
Datapath controller that holds the Long
instruction words.
Instruction Set
The set of operations for control of the
MacroSequencers.
Interface
Type of connections to the RAD5A4. They
include the 5V TTL-l evel, 5V CMOS-level,
and 3.3V CMOS-level.
Internal Signals
There is one internal si gnal. Constant comes
from the LIW word.
I/O Interface
Type of I/O pin interface.
J
JTAG Scan Circuitry
This circuitry supports a specific serial
protocol documented in IEEE 1149.1a
Boundary Scan Protocol document IEEE
Standard Test Access Port and Boundary
Scan Architecture.
K
L
LIW = Long Instruction Word
The RA D 5A4 Ma croSe quence r is ope rationally
controlled by the LIW Register. The LIW
Regi ster is def ine d in term s of the Long
Instruction Word Format. T he Lon g
Instruction W ord Form at is 48 bits w ide. It is
compose d of bit f ields w hich initia te opera tions
in the follow ing internal units of the
MacroSeque ncer: Multiplie r-A ccum ulator,
Adde r, Shifte r, L ogic Unit, Input and O utput
Register Blocks, Index Registers, Data Memory
Ac ces ses , Program Counte r, Re turn Stack , Send
and Await status registers.
Load enable
This is a single bit registe r in the Control
com ponent of each Index Register of the
MacroSe quence r’s Da tapath C ontroller. If it
contains a ‘1’, then the a ddress com ponent w ill
be loaded by the nex t setinde x ope ration.
Load write offset
This is a single bit registe r in the Control
com ponent of each Index Register except the 1-
port Index Reg iste r of the Ma croSe quence r’s
Datapa th Controller. I t is only use d in the 3-port
Read Index Registers. In the Write Address and
Write Offset Registers, it is forced to 0 on every
clock cycle. When set to ‘1’ in a 3-port Read
Index Reg isters, it allow s the Write Of f set
Addre ss c om ponent to be loa ded into that Index
Reg iste r A ddres s com pone nt by an inde xm ode
operation.
Logic Unit
Each RAD5A4 MacroSequencer contains one
log ic unit . The shifter supports all bitwise
logic operations on two operands. The
operands are two words 16 bits of data,
InBusA and InBusB.
loop counter 0, 1
See Counter0, Counter1
M
MAC
Multiplier-Accumulator
Multiply-Accumulate
MacroSequencer
The RAD5A4 contains four
MacroSequencers and a PLA.
Each RAD5A4 MacroSequencer is
composed of an Instruction Memory,
Multiplier-Accumulator, Adder, Shifter,
Logic Unit, Input and Output Register
Blocks, I ndex Registers, Data Memory
Accesses, Program Counter, Return Stack,
Send and Await status registers.
MIMD = Multiple Instruction Multiple
Instruction Datapa th
MIMD systems possess multiple instruction
processors which are capable of acting upon
multiple data paths or streams in each
increment of ti me.
RAD5A4
Terms and Definitions Reconfigurable Arithmetic Datapath
134 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Minterms
Pairs of inputs to the AND arrays in the Dual
PLA arranged to allow all sixteen functions
of the the two inputs.
MSPair(nm), MSPair(mn)
The private buses bet ween t he two
MacroSequencers in a MacroSequ encer pair.
multiplicand, multiplier
Common terms for operands of a multiply.
Multiplier-Accumulator (MAC)
Each RAD5A4 MacroS equencer co ntains one
multiplier-accumulator. The multiplier-
accumulator can perform one 8 bit by 16 bit
multiply or multiply-accumulate per clock
cycle. It can also perform a 16 by 16 bi t
multiply or multiply-accumulate every two
clock cycles.
The accumulator in the multiplier-
accumulator is 48 bits , allowing up t o 64K 1 6
by 16 multiply-accumulate operations and up
to 16 Million 8 by 16 bits multiply-
accumulate op erat i ons before overflow.
Multiplier Data Conversion
Each MacroSequencer’s multiplier-accumulator
uses an interna l intege r form at w hich m ust be
converte d to standard inte ger f orm ats. T his is
done by the Ma croSe quenc er’s A dder.
N
Normal Operating Mode
The operating mode used for executing the LIW
sequenc es . Conf igura tion m ay not occ ur.
NTSC
NTSC stands for National Television System
Committee. This committee proposed in
1953 an analog signal protocol which was
adopted by law as the national television
standard in the U.S., Canada, Mexico and
Japan. This protocol was fully specified by
the Society of Motion Picture and Television
Engineers in 1994.
O
Operations
An assembly language command as defined
by the MacroS equencer Assembly tables.
When combined, these operations become
LIWs.
Output Register Block
This is made up of both OutRegA and
OutRegB.
OutRegA
This is a 16 bit register that holds results and
feeds directly to the Output Buffer which is
under control of the Output Enable circuitry.
OutRegB
This is a 16 bit register that holds temporary
results in MacroSequencer(n) and feeds
directly to the MSPair(nm) input of
MacroSequencer(m).
P
Parallel processing
This is the simultaneous operation of
processing units ( ie: adder MAC Shifter,
Contro l et c.).
Passive Configuration Mode
One of P GM0 or PGM1 are HIGH and the
other is LOW. Configuration may not occur.
Device outputs are held in a high-imped ence
state.
PGM_a, PGM_b
Terms used to refer to PGM0 and PGM1
since the two pins are identical and may be
interchanged.
Pipe
A path fo r data within RAD5A4 elements.
Pipeline structure
Element consisting of pipes such as the
Arithmetic Datapath, the Multiplier-
Accumulator, and the Adder.
PLA
Programmable Logic Array
PLA I/O Buffers
Element within the Dual PLA to hold data fo r
the PLAI/O pins.
Pointer
Holds the address for a memory
Positive Handshake
RAD5A4
Reconfigurable Arithmetic Datapath Terms and Definitions
Infinite Technology Corporation March 1997 135
Phone: 972-437-7800
Communication between the RAD5A4 and
external circuitry used during configuration.
Power On Reset
Term used to describe the state o f th e
RAD5A4 when it first receives po wer.
Preamble data word
The first data word i n each data packet load ed
during configuration
Programmable Logic Device
A device containing a programmable
elements and logic arrays.
Protected registers
These are registers th at hold t heir previous
contents in li eu of a specific inst ruction .
R
Run
Command sent to the MacroSequencer
Datapath Controller from either external pins
or th e Dual PLA cont rol signals. The Run
command allows the Datapath controller to
operate under control of the LIW sequence.
S
Scan Instruction Register
This is a serial register within the JTAG
Boundary Scan Circuit which holds the
intern al scan system control state. Please see
the IEEE 1149.1a Boundary Scan Protocol
document IEEE Standard Test Access Port
and Boundary Scan Architecture for further
details.
SetSequence0, SetSequence2
Command sent to the MacroSequencer
Datapath Controller from either external pins
or th e Dual PLA cont rol signals. The
Setsequence commands sets the program
counter to either ‘0’ or ‘2’ to begin execution
of a sequence of LIWs.
Shifter
Each RAD5A4 MacroSequencer contains one
shifter. The shifter supports all standard shift
operations: logic shift left and right, rotate
left and right and arithmetic shifts right. It
operates on 16 bits of data from InBusC.
Smart Index Register
Each RAD5A4 MacroSequencer contains 5
Index Registers. The four Index Registers are
used for access of th e 3-port Memory are
known as the Smart Inde x Re gisters.
Stack
A Datapath Controller element that holds
program counter values used with call and
return operation s.
Stack pointer
Holds the stack location of the previous call
operation.
State Machine
A logic element t hat changes value based on
the p r evious val ue.
Stream processing
Multiple streams of data are transformed by
an algorithm and output in another set of
streams.
T
Test Access Port (TAP)
This is a collection of four pins TDI, TDO,
TMS, TCK. These pins support a specific
serial protocol documented in IEEE 1149.1a
Boundary Scan Protocol document IEEE
Standard Test Access Port and Boundary
Scan Architecture.
TAP Controller
This is a serial protocol controller which
controls the in t erface of the Test Access Port
Pins.
V
VHDL
This is a computer language developed by the
U.S. Department of Defense. It is an
acronym for the VHSIC Hardware
Description Language. Currently the
language specifies and models digital
electron ic systems.
RAD5A4
Terms and Definitions Reconfigurable Arithmetic Datapath
136 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
0-9
1-port Memory
The 1-port Memory is a 32 by 16 bit RAM.
It is capab l e of one memory access per clock
cycle. This access may either be a read or a
write operation.
See also Data Memory, Index Register and
MacroSequencer ent r i es.
3-port Memory
The 3-port Memory is a 16 by 16 bit 3-port
RAM. It supports 2 read and one write
operation in each clock cycle. Note that i f
more than one of these operations address the
same memory location, the results are not
guaranteed.
See also Data Memory, Index Register and
MacroSequencer ent r i es.
32/16 bit configuration bit
MacroSequencer programmable bit that sets
the Adder for either 32-bit operation or 16-bit
operation.
RAD5A4
Reconfigurable Arithmetic Datapath Table of Signals
Infinite Technology Corporation March 1997 137
Phone: 972-437-7800
Appendix
Table of Signal Names
Signal Name No. of
Bits From To Referenced in these Figures F igure #
Adder Status Bits 4 MSn Arithmet ic
Datapath Adder MSn Arithmetic
Controller, Datapath
Shifter
MacroSequencer, MacroSequencer
Datapath Block Diagram, Adder,
Shifte r, Datapath Controller
9, 10,
14, 15,
22
BUS4IN 16 BUS4IN[15:0] Bus4 Simplified RAD5A4 Operational
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, Dual PLA Block
Diagram, PLA Input Selector
2, 8, 23,
24
bus0 16 MS0 M S0, M S1, M S2,
MS3 Simplifie d RAD5A4 Opera tiona l
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Input Registers, I/O
Interface
2, 8, 9,
10, 11,
21
bus2 16 MS1 M S0, M S1, M S2,
MS3 Simplifie d RAD5A4 Opera tiona l
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Input Registers, I/O
Interface
2, 8, 9,
10, 11,
21
bus3 16 MS2 M S0, M S1, M S2,
MS3 Simplifie d RAD5A4 Opera tiona l
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Input Registers, I/O
Interface
2, 8, 9,
10, 11,
21
bus4 16 MS3 M S0, M S1, M S2,
MS3 Simplifie d RAD5A4 Opera tiona l
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Input Registers
2, 8, 9,
10, 11
Control Bus 32 MS0, MS1, M S2,
MS3, Dual PLA,
MSn Direct Control
Pins
MS0, MS1, MS2,
MS3, Dual PLA,
MSn Direct Control
Pins
Simplifie d RAD5A4 Opera tiona l
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram
2, 8
CtrlReg 8 PLA0 Control
Registers PLA0, PLA1 Dual PLA Block Diagram, PLA
Input Selector, CtrlReg Register 23, 24,
33,
RAD5A4
Table of Signals Reconfigurable Arithmetic Datapath
138 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Signal Name No. of
Bits From To Referenced in these F igures Figure #
C0 8 Control OR Control Registers Dual PLA Block Diagram, Control
OR, CtrlReg Register 23, 31,
33
C1 8 Output OR Output Registers Dual PLA Block Diagram Output
OR, OutReg Register, PLAI/O
Buffers
23, 34,
36, 37
Constant 16 MSn Datapath
Controller MSn Input Register MacroSequencer Datapath Block
Diagram, Input Registers, 10, 11
FO0 8 Fixed OR Array 0 Control OR 0 Dual PLA Block Diagram, Fixed
OR 0, Control OR 23, 27,
31
FO1 14 Fixed OR Array 1 Output OR 1 Dual PLA Block Diagram, Fixed
OR 1, Control OR, Output OR 23, 29,
31, 34
InBusA 16 MSn Input Selector MSn MAC, Adder,
Logi c U n it MacroSequencer Datapath Block
Diagram, Input Selector, 16 by 8
Multiplie r-Ac cumulator, Add er,
Logi c U n it
10, 12,
13, 14,
16
InBusB 16 MSn Input Selector M Sn M AC, Adder,
Logi c U n it MacroSequencer Datapath Block
Diagram, Input Selector, 16 by 8
Multiplie r-Ac cumulator, Add er,
Logi c U n it
10, 12,
13, 14,
16
InBusC 16 MSn Input Selector MSn Shifter MacroSequencer Datapath Block
Diagram, Input Selector, Shifter, 10, 12,
15
InRegA 16 MSn Input Register MSn Input Selector MacroSequencer Datapath Block
Diagram, Input Registers, Input
Selector,
10, 11,
12
InRegB 16 MSn Input Register MSn Input Selector,
MSn Output Selector MacroSequencer Datapath Block
Diagram, Input Registers, Input
Selector, Output Selector
10, 11,
12, 20
LIW Control Bits 48 MSn Ar ithmetic
Controller MSn Arit hme t ic
Datapath MacroSequencer 9
mem0 16 MSn 1-port Memory MSn Input Selector,
MAC MacroSequencer Datapath Block
Diagram, Input Selector, 16 by 8
Multiplie r-Ac cumulat or, 1-Port
Memory
10, 12,
13, 17
mem1 16 MSn 3-port Memory MSn Input Selector MacroSequencer Datapath Block
Diagram, Input Selector, 3-Port
Memory
10, 12,
18
mem2 16 MSn 3-port Memory MSn Input Selector MacroSequencer Datapath Block
Diagram, Input Selector, 3-Port
Memory
10, 12,
18
MultOutA, MultOutB 32 MSn MAC MSn Adder MacroSequencer Datapath Block
Diagram, 16 by 8 Multiplier-
Accumulator, Adder,
10, 13,
14
MS0AWAIT 1 MS0 Datapath
Controller MS0AWAIT, Dual
PLA MacroSequencer 9
MS1AWAIT 1 MS1 Datapath
Controller MS1AWAIT, Dual
PLA MacroSequencer 9
MS2AWAIT 1 MS2 Datapath
Controller MS2AWAIT, Dual
PLA MacroSequencer 9
MS3AWAIT 1 MS3 Datapath
Controller MS3AWAIT, Dual
PLA MacroSequencer 9
RAD5A4
Reconfigurable Arithmetic Datapath Table of Signals
Infinite Technology Corporation March 1997 139
Phone: 972-437-7800
Signal Name No. of
Bits From To Referenced in these Figures F igure #
MS0CTRL 2 MS0 Datapath
Controller MS0CTRL MacroSequencer, Datapath
Controller 22
MS1CTRL 2 MS1 Datapath
Controller MS1CTRL MacroSequencer, Datapath
Controller 22
MS2CTRL 2 MS2 Datapath
Controller MS2CTRL MacroSequencer, Datapath
Controller 22
MS3CTRL 2 MS3 Datapath
Controller MS3CTRL MacroSequencer, Datapath
Controller 22
MS0I/O 16 MS0I/O[15:0], MS0
OutRegA MS0I/O[15:0], bus0 Simplified RAD5A4 Operational
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Output Selector, I/O
Interface
2, 8, 9,
10, 20,
21
MS1I/O 16 MS1I/O[15:0], MS1
OutRegA MS1I/O[15:0], bus0 Simplified RAD5A4 Operational
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Output Selector, I/O
Interface
2, 8, 9,
10, 20,
21
MS2I/O 16 MS2I/O[15:0], MS2
OutRegA MS2I/O[15:0], bus0 Simplified RAD5A4 Operational
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Output Selector, I/O
Interface
2, 8, 9,
10, 20,
21
MS3I/O 16 MS3I/O[15:0], MS3
OutRegA MS3I/O[15:0], bus0 Simplified RAD5A4 Operational
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, MacroSequencer,
MacroSequencer Datapath Block
Diagram, Output Selector, I/O
Interface
2, 8, 9,
10, 20,
21
MS0OE 1 MS0OE MS0 Datapath
Controller MacroSequencer 9
MS1OE 1 MS1OE MS1 Datapath
Controller MacroSequencer 9
MS2OE 1 MS2OE MS2 Datapath
Controller MacroSequencer 9
MS3OE 1 MS3OE MS3 Datapath
Controller MacroSequencer 9
RAD5A4
Table of Signals Reconfigurable Arithmetic Datapath
140 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Signal Name No. of
Bits From To Referenced in these F igures Figure #
MS0SEND 1 MS0 Datapath
Controller MS0SEND, Dual
PLA MacroSequencer 9
MS1SEND 1 MS1 Datapath
Controller MS1SEND, Dual
PLA MacroSequencer 9
MS2SEND 1 MS2 Datapath
Controller MS2SEND, Dual
PLA MacroSequencer 9
MS3SEND 1 MS3 Datapath
Controller MS3AWAIT, Dual
PLA MacroSequencer 9
MSPair01 16 M S0 OutRegB MS1 Input Register Simplified RAD5A4 Control and
Data Flow Diagram,
MacroSequencer, MacroSequencer
Datapath Block Diagram, Input
Registers
8, 9, 10,
11
MSPair10 16 M S1 OutRegB MS0 Input Register Simplified RAD5A4 Control and
Data Flow Diagram,
MacroSequencer, MacroSequencer
Datapath Block Diagram, Input
Registers
8, 9, 10,
11
MSPair23 16 M S2 OutRegB MS3 Input Register Simplified RAD5A4 Control and
Data Flow Diagram,
MacroSequencer, MacroSequencer
Datapath Block Diagram, Input
Registers
8, 9, 10,
11
MSPair32 16 M S3 OutRegB MS2 Input Register Simplified RAD5A4 Control and
Data Flow Diagram,
MacroSequencer, MacroSequencer
Datapath Block Diagram, Input
Registers
8, 9, 10,
11
mt 64 M interm Generators AND Arrays Dual PLA Block Diagram, Product
Terms 23, 25
oepla[n] 1 Dual PLA MSn MacroSequencer, I/O Interface,
Dual PLA Block Diagram 9, 21,
23
OutCom 8 Output OR PLAI/O Buffers Dual PLA Block Diagram 23
OutReg 8 PLA1 Output
Registers PLA0, PLA1 Dual PLA Block Diagram, PLA
Input Selector, OutReg Register 23, 24,
36
OutRegA 16 MSn Output Selector MSn I/O Interface,
1-port memory,
Input Selector
MacroSequencer Datapath Block
Diagram, Input Selector, 1-Port
Memory, Output Selector, I/O
Interface
10, 12,
17, 20,
21
OutRegB 16 MSn Output Selector MSn MSPair(nm),
Input Selector, 3-
p ort memory
MacroSequencer Datapath Block
Diagram, Input Selector, 16 by 8
Multiplie r-Ac cumulat or, 3-Port
Memory, Output Selector
10, 13,
18, 20
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Reconfigurable Arithmetic Datapath Table of Signals
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Signal Name No. of
Bits From To Referenced in these Figures F igure #
PLACtrl0 2 Dual PLA MS0 Datapath
Controller MacroSequencer, Datapath
Controller, Dual PLA Block
Diagram
9, 22,
23
PLACtrl1 2 Dual PLA MS1 Datapath
Controller MacroSequencer, Datapath
Controller, Dual PLA Block
Diagram
9, 22,
23
PLACtrl2 2 Dual PLA MS2 Datapath
Controller MacroSequencer, Datapath
Controller, Dual PLA Block
Diagram
9, 22,
23
PLACtrl3 2 Dual PLA MS3 Datapath
Controller MacroSequencer, Datapath
Controller, Dual PLA Block
Diagram
9, 22,
23
PLAI/O 8 PLAI/O[7:0], PLA0,
PLA1 PLAI/ O[7 :0], PLA1 Simplified RAD5A4 Operationa l
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, Dual PLA Block
Diagram, PLA Input Selector,
PLAI /O B u ffers
2, 8, 23,
24, 37
PLAIN 8 PLA1 PLAI N[7:0] Simplified R AD5A4 Operationa l
Block Diagram, Simplified
RAD5A4 Control and Data Flow
Diagram, Dual PLA Block
Diagram, PLA Input Selector
2, 8, 23,
24
PT0 32 AND Array 0 Fixed OR 0 Dual PLA Block Diagram, Product
Terms, Fixed OR 0 23, 25,
27
PT1 32 AND Array 1 Fixed OR 1 Dual PLA Block Diagram, Product
Terms, Fixed OR 1 23, 25,
29
Output Selector 16 Adder, Shifter, Logic
Unit Output Selector Adder, Shifter, Logic Unit 14, 15,
16
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Macr oSequencer Long Instruction Word
The RAD5A4 MacroSeq uencer is composed of elements within the dat apath
that are contro lled by Long Instru ction Word (LIW) bits. LIWs are
programmed into MacroSequencer LIW memory during device configuration.
The Datapath Controller executes the LIWs which control the arithmetic
datapath.
The LIW bits are used to control the MacroSequencer Arithmetic Datapath.
The LIW bit settings are changed according to the programmed operations.
The assembly operations use one of seven multiplexers for selecting the source
parameters. The LIW settings that control the multiplexer selections and the
assembly operation LIW settings are presented in this section.
Multiplexers These seven (7) multiplexers in the MacroSequencer Arithmetic Datapath are
controlled by different operations resulting in conflicts. Only one source or or
destination may be assigned to these seven multiplexers per LIW.
Input Re gisters
• InRegA
• InRegB
Input Selector
• InBusA
• InBusB
• InBusC
Output S e lector
• OutRegA
• OutRegB
The LIWs that control these multiplexers are shared among operations. For
example, when the inrega input source parameter is selected for an add1
operation, the InBusA multiplexer control bits LIW[9:8] are set. InBusA’s
resources are committed, and other operations cannot select a different InBusA
related input signal in the same instruction word.
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The following tables specify the LIW settings for each of the seven
MacroSequencer multiplexers:
InRegA
<src> LIW[4:2]
hold 000 (default)
bus4 001
constant (LIW[43:28]) 010
bus0 011
bus1 100
bus2 101
bus3 110
pair 111
table LIW-1
InRegB
<src> LIW[7:5]
hold 000 (default)
bus4 001
constant (LIW[43:28]) 010
bus0 011
bus1 100
bus2 101
bus3 110
pair 111
table LIW-2
The InBusA signal is used by the multiplier, adder, and logic unit which are
controlled by these operations: mult1, add1, sub1, and logic.
InBusA
<src> LIW[9:8]
inrega 00 (default)
outrega 01
outregb 10
mem1 11
table LIW-3
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The InBusB signal is used by the multiplier, adder, and logic unit which are
controlled by these operations: mult1, add1, sub1, and logic.
InBusB
<src> LIW[12:10]
0 000 (default)
mem0 001
inregb 100
outrega 101
outregb 110
mem2 111
table LIW-4
InBusC
<src> LIW[14]
outrega 0 (default)
inrega 1
table LIW-5
The OutRegA signal may be selected as a destination for results from the logic
unit, shifter and adder. Th e destinations for these units are controlled by the:
add2, sub2, shift, and logic operations. When these operations select the
destination to be outrega, LIW[18: 17] are affected as fol lows:
OutRegA
<src> LIW[18:17]
hold 00 (default)
logic 01
shifter 10
adder 11
table LIW-6
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Reconfigurable Arithmetic Datapath LIW
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The OutRegB signal may be selected as a destination for the InRegB input
register (in operation), MSnIO[15:0] pins (pins operation), adder, shifter, and
logic unit. The destinations for these units are controlled by the: move, in,
add2, sub2, shift, and logic operations. When these operations select the
destination to be outregb, LIW[21:19] are affected as follows:
OutRegB
Source / operation LIW[21:19]
hold 000 (default)
InRegB 001
pins 100
logic 101
shifter x10
adder x11
table LIW-7
Assembly Operations
LIW settings for each Macro Sequencer assembler operation are listed in the
tables that follow. Some LIW bits are set by only one operation; some are
shared by operations and are set depending on the operation parameter
selection.
nop The nop operation is the default setting and sets all 48 LIW bits:
LIW[47:0] in binary:
1001 0001 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000
LIW[47:0] in hexadecimal:
0x9100,0000,1000
in <src>,<dest>
If <dest> = inrega, LIW[4:2] bits are set according t o the InRegA tab le to select
the source.
If <dest> = inregb, LIW[7:5] bits are set according to the InRegB table to select
the source.
in pins, out regb
This operation sets LIW[21:19] to ‘100’ in acco rdance with the OutRegB tab le.
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mult1 <srca>,<srcb>
The Multiplier source parameter multiplexers are controlled by LIW[47,44]. If
a source is selected from the InBusA and/or In BusB signals, t hen LIW[9: 8]
and/or LIW[12:10] are also set in accordance with the InBusA and InBu sB
tables.
<srca> LIW[47,44]
InBusA multiplexer selection
(inrega, outrega, outregb, mem1) 00
mem0 01 or 10
hold 11 (default)
table LIW-8
<srcb> LIW[47,44]
InBusB multiplexer selection
(0, mem0, inregb, outrega, outregb,
mem2)
00 or 01
outregb 10
hold 11 (default)
table LIW-9
The mu ltiplier input multiplexers are controlled with the same two LIW[47,44]
bits. Therefore, the LIW control bits for the two inputs mu st have the same
values.
Operand A is multiplied by the most significant byte of operand B. The least
significant byte of operand B is stored for possible use in a mult1 hold
operation on the next cycle.
mult1 hold LIW[47,44] is set to ‘11’. This forces the previous cycle’s operand A to be
used with the least significant byte of the last cycle’s operand B.
mult3 <weight>, <enable>
The mult3 operation sets LIW[23] to ‘1’; otherwise LIW[23] is ‘0’.
<weight> LIW[40] <enable> LIW[43]
low 0 (default) clr 0 (default)
high 1 acc 1
table LIW-10 table LIW-11
add1 <oper1>, <oper2>
An add1 operation other than an add1 mult sets LIW[15,13] to [0,0].
LIW[9:8] bits are set by the <oper1> as shown in the InBusA table LIW-3.
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LIW[12:10] bits are set by the <oper2> as shown in the InBusB table LIW-4.
add1 mult, <pos>
An add1 mult operation sets LIW[15] to ‘1’; otherwise LIW[15] is ‘0’.
<pos> LIW[42:41]
low 00
norm 01
mid 10
high 11
table LIW-12
add2 [<dest1> [, <dest 2>] ]
The add2 operation sets the carry in bit LIW[16] to ‘0’.
LIW[18:17] bits are set to [11] when the <dest1> or <dest2> is outrega for the
add2 operation.
LIW[21:19] bits are set to [x11] when the <dest1> or <dest2> is outregb for
the add2 operation.
sub1 <srca>, <srcb>
The sub1 operation sets LIW[15,13] to [0,1] .
LIW[9:8] bits are set by the <oper1> as shown in the InBusA table LIW-3.
LIW[12:10] bits are set by the <oper2> as shown in the InBusB table LIW-4.
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sub2 [<dest1> [, <dest 2>] ]
The sub2 operation sets the carry in bit LIW[16] to ‘1’.
LIW[18:17] bits are set to [11] when the <dest1> or <dest2> is outrega for the
sub2 operation.
LIW[21:19] bits are set to [x11] when the <dest1> or <dest2> is outregb for
the sub2 operation.
shift <src>, <type>,<length>, <dest1>[ , <dest2>]
shift <src>, normal , <dest 1>[, <dest 2>]
The shift operation parameters set LIW[14, 34:32, 38:35, 18:17, and/or 21:19]
bits as listed here:
LIW[14] is set by the <src> parameter in accordance with the InBusC table
<type> LIW[34:32] <length>
in LIW[38:35]
logicright 001 0-15 or 0x0-0xf
logicleft 010 0-15 or 0x0-0xf
normal 011 0001
arithmetic 101 0-15 or 0x0-0xf
rotate 110 0-15 or 0x0-0xf
table LIW-13
LIW[18:17] bits are set to [10] when the <dest1> or <dest2> is outrega for the
shift operation.
LIW[21:19] bits are set to [x10] when the <dest1> or <dest2> is outregb for
the shift operation.
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logic <oper>, <dest1>, [ < dest 2>]
logic <oper>, <srca>, dest 1>, [ < dest 2>]
logic <oper>, <srcb>, dest 1>, [ < dest 2>]
logic <oper>, <srca>, <srcb>, dest 1>, [ < dest 2>]
The logic operation parameters set LIW[14, 34:32, 38:35, 18:17, and/or 21:19]
bits as listed here:
<oper> LIW[31:28]
0 0000
1 1111
nota 0011
a 1100
notb 0101
b 1010
nor 0001
notab 0010
anotb 0100
xor 0110
nand 0111
and 1000
xnor 1001
notaorb 1011
aornotb 1101
or 1110
table LIW-14
LIW[9:8] bits are set by the <srca> as shown in the InBusA table LIW-3.
LIW[12:10] bits are set by the <srcb> as shown in the InBusB table LIW-4.
LIW[18:17] bits are set to [01] when the <dest1> or <dest2> is outrega for the
logic operation.
LIW[21:19] bits are set to [101] when the <dest1> or <dest2> is outregb for
the logic operation.
When neither operand <srca> or <srcb> is needed there are no constraints on
LIW[12:8].
When only <srca> is needed there are no constraints on LIW[12:10].
When only <srcb> i s needed, there are no constraints on LIW[ 9:8]
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oneport <oper> <oper> LIW[1:0]
write 10
read 01
default 00
not allowed 11
table LIW-15
memw rite, memread1, memread2
The memwrite operation sets LIW[22] to ‘1’.
The memread1 operation sets LIW[45] to ‘1’.
The memread2 operation sets LIW[46] to ‘1’.
move - moves the contents of InRegB to OutRegB
LIW[21:19] is set to ‘001’.
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Datapath Controll er Operations
The datapath controller operations determine the values for LIW[27:24]. The
Parameters determine LIW[39:28].
Operation LIW
[27:24] Parameters LIW
[39:28] Arguments LIW
bits
indexmode
0001 <m0>: none, reset
<mw>: none, resetoffset,
resetall
<m1>: none, reset, align
<m2>: none reset, align
[28]
[31:30]
[33:32]
[35:34]
[39:36] = 0
none
reset
align
resetoffset
resetall
0
01
10
01
01
send 0010 no arguments none
await 0011 no arguments none
setcounter0 <value> 0100 <value>: 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
setcounter1 <value> 0101 <value>: 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
setindex <value> 0110 <value>: 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
setindex 0110 <valuew>: 0-15 or 0x0-0xf
<value1>: 0-15 or 0x0-0xf
<value2>: 0-15 or 0x0-0xf
[39:36]
[35:32]
[31:28]
indexdirect
0111
<d0>: none, inc, dec
<dw>: none, inc, dec, rev
<d1>: none, inc, dec, rev
<d2>: none, inc, dec, rev
<index>: readwrite0, write,
read1, read2,
all3port
[29:28]
[31:30]
[33:32]
[35:34]
[38:36]
none
inc
dec
rev
readwrite0
write
read1
read2
all3port
00
01
10
11
000
001
010
011
100
jump <address> 1000 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
call <address> 1001 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
return 1010 no arguments none
jumpequal <address> 1011 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
jumpoverflow <address> 1100 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
jumpsign <address> 1101 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
jumpcounter0 <address> 1110 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
jumpcounter1 <address> 1111 0-31 or 0x0-0x1f [32:28],
[39:33] = 0
table LIW-16
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LIW Setting Summary
The tables that follow summarize which MacroSequencer functional units affect which LIW bits.
LIW Opera tional Unit Definit ion Conti nued
Operational Unit 47 46 45 44 43 42 41 40 39 38 37 36
1-port memory access
1-port index register
operation X X X
3-port memory access X X
3-port index register
operation
set index mode
index directions X X X
Input Bus Mux A & B
Input Mux A & B
Adder Pipe 1
Adder Pipe 2
Output Mux 0 & 1
Multiplier pipe 1 X X
Multiplier pipe 2(Acc) X X X X
Sequence Controller
Constant X X X X X X X X
logic unit control
shifter X X X
LIW Operational Unit Definition
Operational Unit 35 34 33 32 31 30 29 28 27 26 25 24
1-port memory access
1-port index register
operation X X X
3-port memory access
3-port index register
operation
set index mode
X X X X X X
index directions X X X X X X
Input Bus Mux A & B
Input Mux A & B
Adder Pipe 1
Adder Pipe 2
Output Mux 0 & 1
Multiplier pipe 1
Multiplier pipe 2(Acc)
Sequence Controller X X X X
Constant X X X X X X X X
logic unit control X X X X
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shifter X X X X
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LIW Opera tional Field Definition Continued
Operational Fields 23 22 21 20 19 18 17 16 15 14 13 12
1-port memory access
1-port index register
operation
3-port memory access X
3-port index register
operation
Input Bus Mux A & B to
inrega,b
Input Mux A, B & C X X
Adder Pipe 1 X X
Adder Pipe 2 X
Output Mux 0 & 1 to
outrega,b X X X X X
Multiplier pipe 1
Multiplier pipe 2(Acc) X
Sequence Controller
Constant
logic unit control
shifter
LIW Operational Field Definition
Operational Fields 11 10 9 8 7 6 5 4 3 2 1 0
1-port memory access X X X X
1-port index register
operation
3-port memory access
3-port index register
operation
Input Bus Mux A & B to
inrega,b X X X X X X
Input Mux A, B & C X X X X
Adder Pipe 1
Adder Pipe 2
Output Mux 0 & 1 to
outrega,b
Multiplier pipe 1
Multiplier pipe 2(Acc)
Sequence Controller
Constant
logic unit control
shifter
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JTAG Scan Circuitry
The RAD5A4 JTAG Scan circuitry complies with the IEEE standard 1149.1a
Boundary Scan Protocol providing a reasonable test interface t o a complex
system. The active logic p ins no t involved in th e protocol itself are accessible
via the JTAG Scan circuitry. Many registers in each MacroSequencer are also
accessible.
The JTAG Scan circuitry supports production testing of the printed circuit
boards, remote site diagnosis of system conditions and the development of
applications software.
The IEEE 1149.1a Boundary Scan Protocol provides a low pin count method
for testing systems specified in the IEEE Standard Test Access Port an d
Boundary Scan Architecture, (c) 1993, Institute of Electrical and Electronics
Engineers, Inc., New York, ISBN 1-55937-350-4.
The Boundary Scan Protocol uses a serial protocol involving four special
purpose pins: TDI, TDO, TCK, TMS, which are known as the TAP (Test
Access Port) pins. The TAP pins allow the state of all act ive logic sign als to be
examined and for the state of many registers in the four Macro Sequencers t o be
examined.
RAD5A4 Scan Circuitry Components and Features
The primary components of the scan circuitry are the TAP Controller, the ID
Register, the BYPASS Register, the Scan Instruction Register, the Boundary
Scan Path and the four MacroSequencer Scan Paths.
The TAP Controller is documented in the IEEE standard 1149.1a as referenced.
The ID Register identifies which component is present.
The BYPASS Regi ster is a single register which is active when the Scan
Instruction Register contains the BYPASS instruction and the TAP Controller
is in data transfer mode. The BYPASS Register captures the TDI pin input on
the rising edge of TCK. The TDO out put sign al is the stat e of the BYPASS
register. Note that the TDO pin changes state after the falling edge of TCK.
The Scan Inst ruction Regi st er provides overall control for the scan ci rcuitry.
It has a five-bit code which is discussed later in this chapter.
The Boundary Scan Path is a collection of registers connected to form a shift
register which is capable of capturing and (for most pins) asserting the state of
the pins and the directionality of the bi-directional I/O pins.
The four MacroSequencer Scan Paths allow the state of many registers of each
MacroSequencer to be examined and potentiall y modified. The
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MacroSequencer Scan Path circuitry can be made to feed back the shifted data
pattern fro m the MacroSequencer, creating a circular sh i ft register network
from each MacroSequencer Scan Path. This supports a simple observe-only
emulator interface.
While scanning the contents of any scan path, none of the five clock pins
should change state. The MSnCLK input must be maintained LOW when
testin g the MacroSequencern scan path.
Boundary Scan Path Map
In the fol l owing tables, t he bus signals are deno t ed Bus[a:b] where Bu s[a] is
the first bit read out, and the last bit read out is Bus[b]. Thus, the first bit
scanned in is Bus[a] and the last bit scanned in is Bus[b].
Pin types include Input, Output, I/O, and Clock. A dash ‘-’ is used to denote
no entry or not applicable.
The following terms in the table include:
• Observe Only signals are signals which cannot be altered by the
Boundary Scan Registers but can be observed.
• The Observe and Assert signals can not only be observed, but may also
be altered by the Boundary Scan Registers.
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Boundar y Scan Path Map
Scan Signal Name and Scan Scan Cell F unction
Signal Signal Source Cell Observe Observe
Bits[0:137] Pin Internal Type and Assert Only Comme nts
0,1 MS0CTRL[0:1] - Input X -
2 MS0OE - Input X -
3 MS0CLK - Clock - X
4 MS0SEND - Output X -
5 MS0AWAIT - Output X -
6 - 21 MS0I/O[0:15] - I/O X -
22 - oems0 Input X - Output enable for
MS0I/O[15:0]
23,24 MS1CTRL[0:1] - Input X -
25 MS1OE - Input X -
26 MS1CLK - Clock - X
27 MS1SEND - Output X -
28 MS1AWAIT - Output X -
29 - 44 MS1I/O[0:15] - I/O X -
45 - oems1 Input X - Output enable for
MS1I/O[15:0]
46 - oems3 Input X - Output enable for
MS3I/O[15:0]
47 - 62 MS3I/O[15:0] - I/O X -
63 MS3AWAIT - Output X -
64 MS3SEND - Output X -
65 MS3CLK - Clock - X
66 MS3OE - Input X -
67,68 MS3CTRL[1:0] - Input X -
69 - oems2 Input X - Output enable for
MS2I/O[15:0]
70 - 85 MS2I/O[15:0] - I/O X -
86 MS2AWAIT - Output X -
87 MS2SEND - Output X -
88 MS2CLK - Clock - X
89 MS2OE - Input X -
90,91 MS2CTRL[1:0] - Input X -
Note: XXX[a:b] means XXX[a] is scanned out first, and XXX[b] is scanned out last.
For all output enable signals in Internal column: ‘1’ = output enabled, ‘0’ = output disabled.
table JTAG-1
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Boundar y Scan Path Map, Continued
Scan Signal Name and Scan Scan Cell F unction
Signal Signal Source Cell Observe Observe
Bits[0:137] Pin Internal Type and Assert Only Comme nts
92 PLACLK - Input - X
93 PACK - Output X -
94 - packoe Input X - Output enable for P ACK
95 PRDY - Input X -
96 PGM0 - Input X -
97 PGM1 - Input X -
98 - 113 BUS4IN[0:15] - Input X -
114 PLAI/O[7] - I/O X -
115 - plaoe[7] Input X - Output enable for
PLAI/O[7]
116 PLAI/O[6] - I/O X -
117 - plaoe[6] Input X - Output enable for
PLAI/O[6]
118 PLAI/O[5] - I/O X -
119 - plaoe[5] Input X - Output enable for
PLAI/O[5]
120 PLAI/O[4] - I/O X -
121 - plaoe[4] Input X - Output enable for
PLAI/O[4]
122 PLAI/O[3] - I/O X -
123 - plaoe[3] Input X - Output enable for
PLAI/O[3]
124 PLAI/O[2] - I/O X -
125 - plaoe[2] Input X - Output enable for
PLAI/O[2]
126 PLAI/O[1] - I/O X -
127 - plaoe[1] Input X - Output enable for
PLAI/O[1]
128 PLAI/O[0] - I/O X -
129 - plaoe[0] Input X - Output enable for
PLAI/O[0]
130 - 137 PLAIN[7:0] - Input X -
Note: XXX[a:b] means XXX[a] is scanned out first, and XXX[b] is scanned out last.
For all output enable signals in Internal column: ‘1’ = output enabled, ‘0’ = output disabled.
table JTAG-1, continued
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Scan Map within each MacroS equencer(n)
Scan Signal
Bits [0:190] Signal Name Comments
0-15 InRegA[0:15] Input Registers
16-31 InRegB[0:15] Input Registers
32-34 1-port Index Ctrl[0:2] Datapath Controller: I1P Control Register
Ctrl[0]=>lden, Ctrl[1] => count_up, Ctrl[2] => count_down
35-39 1-port Index Adr[4:0] Datapath Controller: I1P Address Register
40-43 3-port Read 2 Index Ctrl[0:3]
Datapath Controller: I3PR2 Control Register
Ctrl[0] => lden, Ctrl[1] => ldwo, Ctrl[2] => count_up,
Ctrl[3] => count_down
44-47 3-port Read 2 Index Adr[3:0] Datapath Controller: I3PR2 Address Register
48-51 3-port Read 1 Index Ctrl[0:3]
Datapath Controller: I3PR1 Control Register
Ctrl[0] => lden, Ctrl[1] => ldwo, Ctrl[2] => count_up,
Ctrl[3] => count_down
52-55 3-port Read 1 Index Adr[3:0] Datapath Controller: I3PR1 Address Register
56-59 3-port Write Index Ctrl[0:3] Datapath Controller: I3PW Control Register
Ctrl[0] => lden, Ctrl[1] => ldwo, Ctrl[2] => count_up,
Ctrl[3] => count_down See note 3.
60-63 3-port Write Index Ad r[ 3:0] Datapath Controller: I3PW Address Register
64-67 3-port Write Offset Ctrl[0:3]
Datapath Controller: I3PWO Control Register
Ctrl[0] = > lden, C tr l[1] => ldwo, Ctrl [2] => count_up,
Ctrl[3] => c ount_down See note 3.
68-71 3-port Write Offset Adr[3:0] Datapath Controller: I3PWO Address Register
72-80 LIW[7:2, 46:45, 22] Datapath Controller: LIW Register
81-105 LIW[1:0, 14:8, 39:24] Datapath Controller: LIW Register
106-112 LIW[47,44:40,23] Datapath Controller: LIW Register
113-119 LIW[16:15,21:17] Datapath Controller: LIW Register
120-124 PC[4:0] Datapath Controller: Program Counter
125-126 Stack pointer [1:0] Datapath Controller: Stack Pointer Registers
127-131 Stack wd3[4:0] Datapath Controller: Stack Word 3
132-136 Stack wd2[0:4] Datapath Controller: Stack Word 2
137-141 Stack wd1[4:0] Datapath Controller: Stack Word 1
142-146 Stack wd0[0:4] Datapath Controller: Stack Word 0
147-148 PLACtrln[1:0] Datapath Controller: PLACtrl Registers
149-153 Counter1 [4:0] Datapath Controller: Loop Counter 1
154-158 Counter0 [4:0] Datapath Controller: Loop Counter 0
159-174 OutRegB[15:0] Output Selector: Registers
175-190 OutRegA[15:0] Output Selector: Registers
Note 1: XXX[a:b] means XXX[ a] is scanned out first, and XXX[b] is scanned out last.
Note 2: lden = load enable, ldwo = load write offset.
Note 3: During normal operation, Ctrl[1] (ldwo) of the 3-port Write Index Control and the 3-port Write Offset Control is
set to ‘0’ on each MSnCLK clock cycle. Do not put ‘1’ into Ctrl[1] of these registers using scan and then clock the
relevent MSnCLK. t able JTAG-2
RAD5A4
JTAG Scan Circuitry Reconfigurable Arithmetic Datapath
160 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
Instruction Register
The Instruction Register (INSTREG) contains 5 bit cells, labeled
INSTREG[4:0] where INSTREG[4] is the most significant bit. INSTREG[0],
the least significant bit, is the first bit scanned in and the first bit scanned out.
The scan inst ruction codes used i n the RAD5A4 are listed here:
Scan Ins tructi o n Code Definition
Selection Name
Bit Number Boundary
Mode Observe Observe
/Assert Observe/
Assert/
4 3 2 1 0 Restore
EXTEST 0 0 0 0 0 Extest Input Pins Output Pins -
BYPASS
Default Codings 1
0
0
0
0
1
0
0
0
1
X
1
0
0
1
X
X
1
0
1
X
X
X
1
X
Normal - - -
INTEST 0 1 0 0 0 Intest Output Pins
(High Z) Input Pins -
SAMPLE/PRELOAD 0 1 0 1 1 Sample/
Preload All Input
and Output
Pins
- -
Observe Boundary 0 1 0 1 0 Normal All Input
and Output
Pins
- -
ID Register (IDCODE) 0 1 0 0 1 Normal - - -
CLAMP 0 1 1 0 0 Clamp - - -
HIGHZ 0 1 1 0 1 HighZ - - -
MS0 with TDI input 1 0 0 0 0 Clamp - MS0 -
MS0 with Wraparound 1 0 1 0 0 Clamp - - MS0
MS1 with TDI input 1 0 0 0 1 Clamp - MS1 -
MS1 with Wraparound 1 0 1 0 1 Clamp - - MS1
MS2 with TDI input 1 0 0 1 0 Clamp - MS2 -
MS2 with Wraparound 1 0 1 1 0 Clamp - - MS2
MS3 with TDI input 1 0 0 1 1 Clamp - MS3 -
MS3 with Wraparound 1 0 1 1 1 Clamp - - MS3
Notes:
• The instruction register is asynchronously forced to IDCODE during Power On Reset.
• Boundary Modes are defined in the IEEE standard 1149.1a Scan Document.
• MS0 represents MacroSequencer 0, MS1 represents MacroSequencer 1, MS2 represents
MacroSequencer 2, and MS3 represents MacroSequencer 3.
table JTAG-3
RAD5A4
Reconfigurable Arithmetic Datapath JTAG Scan Circuitry
Infinite Technology Corporation March 1997 161
Phone: 972-437-7800
Device Identification Register Specification
The Device Identification Register (IDREG) contains 32 b it cells, labeled
IDREG[0:31] where IDREG[31] is the most significant bit, and IDREG[0] is
the first bit scanned in and scanned out. IDREG[0] is ‘1’.
IDREG[31:28] contains the design version number which is ‘0000’ for initial
design silicon and will be incremented for any later redesigns. For example,the
first redesign silicon would contain the code ‘0001’.
IDREG[27:12] contains the Part Number. The coding used in the RAD5A4 is
0000,0000,0000,000a where “a” = 0 for CMOS-compatib l e i nterface, and “a”
= 1 for TTL- compatible in terface.
IDREG[11:1] contains the Manufacturer Number. The coding initially used in
the RAD5A4 is 000,0111,1111.
RAD5A4
Reconfigurable Arithmetic Datapath
162 M arch 1997 Infini te Technology Corporation
Phone: 972-437-7800
RAD5A4
Reconfigurable Arithmetic Datapath
Infinite Technology Corporation March 1997 163
Phone: 972-437-7800
Infinite Technology Corporation
2425 N. Central Expressway, Suite 323
Richardson, TX 75080
Phone: 972-437-7800
Fax: 972-437-7810
INFINITE TECHNOLOGY CORPORATION reserves the right to ma ke changes to the products
contained in this data book in order to improve the design or performance and to supply the best
po ssible product s. Infinite T echnology Corporation assumes no respo nsibilit y for t he use of any circuits
shown in this data book, conveys no license under any patent or other rights, and makes no claim that
the circuits are free from patent infringement. Applications for any device shown in this data book are
for illustr atio n only and Infinite Techno logy Corpora tion mak es no claim or w arranty t hat such
ap plicatio ns will be suitable for the use specified w ithout further t esting or mo dificatio n.
