RAD5A4 RECONFIGURABLE ARITHMETIC DATAPATH DEVICE DESCRIPTION AND SPECIFICATIONS MARCH 1997 INFINITE TECHNOLOGY CORPORATION RAD5A4 Reconfigurable Arithmetic Datapath Quality Assurance Our quality system focuses on high quality components and the best possible service for our customers. The RAD5A4 has been designed to optimize arithmetic performance. (c) 1995, 1996, 1997 Infinite Technology Corporation, Inc. Infinite Technology Corporation, Richardson, Texas, reserves the right to make changes in its products without notice in order to improve design or performance characteristics. Trademarks RADTM is a trademark of Infinite Technology Corporation, Richardson, Texas. RADwareTM is a trademark of Infinite Technology Corporation, Richardson, Texas. Reconfigurable Arithmetic DatapathTM is a trademark of Infinite Technology Corporation, Richardson, Texas. ii March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Description & Specifications RAD5A4 DATA BOOK Contents Product Status 2 Part Number Description 3 High-Speed Accelerator for Algorithms 4 Architecture Description 12 RAD5A4 Configuration 64 Device Specifications 89 Revision History 128 Terms and Definitions 129 Appendix 137 MacroSequencer programming information is found in the MacroSequencer Programming Manual in this book. PLA programming and configuration file generation is found in the RADware for Windows Manual. Simulation information is found in the RAD VHDL Simulation Guide in this book. Typical applications using RAD5A4 devices are described in various RAD Notes which contain Application descriptions and implementations, Execution Results, and Example MacroSequencer assembly programs. Infinite Technology Corporation Phone: 972-437-7800 March 1997 iii RAD5A4 Description & Specifications iv Reconfigurable Arithmetic Datapath March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Description & Specifications TABLE OF CONTENTS PRODUCT STATUS 2 PART NUMBER DESCRIPTION 3 HIGH-SPEED ACCELERATOR FOR DATA STREAM ALGORITHMS 4 HIGH-PERFORMANCE MULTIPLY-ACCUMULATE .............................................. 4 MULTIPLE OPERATIONS PER CLOCK CYCLE ..................................................... 4 DATA STREAM PROCESSING ............................................................................... 5 RAD5A4 COMPONENTS ...................................................................................... 5 RAD5A4 PERFORMANCE.................................................................................... 6 IMAGING APPLICATIONS .............................................................................................................................7 ARITHMETIC ACCELERATOR APPLICATIONS.................................................................................................7 RAD5A4 AS A COPROCESSOR ....................................................................................................................8 RAD5A4 IN MATRIX PROCESSING .............................................................................................................8 RAD5A4 FOR VIDEO FILTERING ................................................................................................................9 FFT NOISE FILTERING ................................................................................................................................9 EASE OF IMPLEMENTATION .............................................................................. 10 DESIGN TOOLS .........................................................................................................................................11 IN-CIRCUIT RECONFIGURABILITY . . .GREAT TIME-TO-MARKET .................. 11 ARCHITECTURE DESCRIPTION 12 RAD5A4 DATA BUS .......................................................................................... 15 RAD5A4 CONTROL BUS ................................................................................... 15 INPUT CLOCKS ................................................................................................... 17 MACROSEQUENCER DESCRIPTION ................................................................... 18 MACROSEQUENCER ARITHMETIC DATAPATH ................................................. 19 INPUT REGISTERS .....................................................................................................................................21 INPUT SELECTOR ......................................................................................................................................22 MULTIPLIER-ACCUMULATOR ....................................................................................................................23 ADDER .....................................................................................................................................................25 SHIFTER ...................................................................................................................................................28 LOGIC UNIT ..............................................................................................................................................30 1-PORT MEMORY .....................................................................................................................................31 3-PORT MEMORY .....................................................................................................................................32 Smart Indexing ...................................................................................................................................33 OUTPUT SELECTOR ...................................................................................................................................35 I/O INTERFACE .........................................................................................................................................37 MACROSEQUENCER DATAPATH CONTROLLER ............................................... 38 COMPONENTS ...........................................................................................................................................38 CONTROL SIGNALS ...................................................................................................................................40 Infinite Technology Corporation Phone: 972-437-7800 March 1997 v RAD5A4 Description & Specifications Reconfigurable Arithmetic Datapath STATUS SIGNALS ......................................................................................................................................42 ADDER STATUS SIGNALS ..........................................................................................................................42 PROGRAM COUNTER .................................................................................................................................43 BRANCH OPERATIONS ...............................................................................................................................44 LONG INSTRUCTION WORD REGISTER .......................................................................................................44 INSTRUCTION MEMORY ............................................................................................................................44 COUNTER0 AND COUNTER1 ......................................................................................................................44 STACK ......................................................................................................................................................45 INDEX REGISTERS .....................................................................................................................................46 MACROSEQUENCER CONFIGURATION BITS ..................................................... 48 RAD5A4 DUAL PLA DESCRIPTION ................................................................. 49 PLA INPUT SELECTORS ............................................................................................................................51 MINTERM GENERATOR .............................................................................................................................53 AND ARRAYS ..........................................................................................................................................53 AND ARRAY FUNCTION GENERATOR .......................................................................................................54 FIXED OR ARRAYS ...................................................................................................................................56 CONTROL OR ARRAY ...............................................................................................................................58 CTRLREG REGISTER .................................................................................................................................60 OUTPUT OR ARRAY .................................................................................................................................61 OUTPUT REGISTER ....................................................................................................................................63 PLAI/O BUFFERS .....................................................................................................................................63 RAD5A4 CONFIGURATION 64 CONFIGURATION CONTROL PIN DESCRIPTION ................................................ 65 RAD5A4 CONFIGURATION MODES .................................................................. 66 NORMAL OPERATING MODE: PGM0 = PGM1 = LOW............................................................................66 PASSIVE CONFIGURATION MODE: PGM0 OR PGM1 = HIGH, THE OTHER LOW......................................66 ACTIVE CONFIGURATION MODE: PGM0 = PGM1 = HIGH. ....................................................................67 CONFIGURING A RAD5A4 DEVICE .................................................................. 67 CONFIGURATION WITH POSITIVE HANDSHAKING SIGNALS ............................ 68 CONFIGURATION TIMING .................................................................................. 69 CONFIGURATION SUMMARY ......................................................................................................................75 MINIMIZING CONFIGURATION TIME...........................................................................................................78 CONFIGURATION WITHOUT HANDSHAKING ................................................................................................80 TIME TO CONFIGURE THE RAD5A4................................................................. 83 PLACLK PULSES PER MEMORY CONFIGURED ..........................................................................................83 Reading the PLACLK Pulses for Configuration Table.......................................................................84 PLACLK PULSES FOR DEVICE CONFIGURATION .......................................................................................85 DEVICE CONFIGURATION TIME .................................................................................................................86 MULTIPLE RAD5A4 DEVICE CONFIGURATION............................................... 87 CONFIGURATION DATA WORD COUNTER ........................................................ 88 DEVICE SPECIFICATIONS 89 PIN LIST ............................................................................................................. 91 ABSOLUTE MAXIMUM RATINGS ....................................................................... 93 vi March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Description & Specifications TTL-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION) .............. 94 5 V CMOS-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION) ..... 99 3.3 V CMOS-LEVEL INTERFACE OPTIONS (PRELIMINARY SPECIFICATION)104 TIMING DIAGRAMS .......................................................................................... 109 AC MEASUREMENT DIAGRAM OF THE LOAD CIRCUIT FOR OUTPUT .........................................................111 TRANSITIONING BETWEEN ACTIVE AND NORMAL OPERATING MODES ....... 112 WAVEFORMS ..........................................................................................................................................113 PIN DIAGRAM .................................................................................................. 114 RAD5A4 PIN DESCRIPTION........................................................................... 115 POWER SUPPLY PINS ..............................................................................................................................115 MACROSEQUENCER PINS ........................................................................................................................116 BUS 4 INPUT PINS ...................................................................................................................................118 PLA PINS...............................................................................................................................................119 CONFIGURATION PINS .............................................................................................................................120 SCAN PINS..............................................................................................................................................121 PACKAGE CHARACTERISTICS ......................................................................... 122 POWER DISSIPATION VERSUS CLOCK FREQUENCY ..................................................................................122 THERMAL CHARACTERISTICS ..................................................................................................................124 PACKAGE MECHANICAL DETAILS .................................................................. 126 THIN QUAD FLAT PACK (TQFP), 176 PINS .............................................................................................126 POWER TQFP, 176 PINS .........................................................................................................................127 REVISION HISTORY 128 TERMS & DEFINITIONS 129 ACRONYMS ...................................................................................................... 129 GLOSSARY........................................................................................................ 130 APPENDIX 137 TABLE OF SIGNAL NAMES ............................................................................... 137 MACROSEQUENCER LONG INSTRUCTION WORD .......................................... 142 Multiplexers......................................................................................................................................142 Assembly Operations........................................................................................................................145 LIW SETTING SUMMARY........................................................................................................................152 JTAG SCAN CIRCUITRY ................................................................................. 155 BOUNDARY SCAN PATH MAP..................................................................................................................156 Instruction Register...........................................................................................................................160 Device Identification Register Specification ....................................................................................161 Infinite Technology Corporation Phone: 972-437-7800 March 1997 vii RAD5A4 Description & Specifications viii Reconfigurable Arithmetic Datapath March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Description & Specifications TABLE OF FIGURES Figure Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Figure Name Part Number Description Simplified RAD5A4 Operational Block Diagram Video Filter Application RAD5A4 as a Coprocessor Matrix Processing Reconfigurable Video Filter FFT Noise Filter Programming the RAD5A4 Simplified RAD5A4 Data Flow Block Diagram MacroSequencer MacroSequencer Datapath Block Diagram MacroSequencer Input Registers MacroSequencer Input Selector Multiplier-Accumulator Adder Shifter Logic Unit 1-port Memory 3-port Memory 3-port Memory Index Pointers Output Selector I/O Interface MacroSequencer Datapath Controller Dual PLA Block Diagram PLA Input Selector Product Terms Function Generator Fixed OR0 Block Diagram Fixed OR0 Schematic Fixed OR1 Block Diagram Fixed OR1 Schematic Control OR Control OR Simplified Schematic Control Register Output OR Output OR Simplified Schematic Output OR Register PLAI/O Buffers Infinite Technology Corporation Phone: 972-437-7800 March 1997 Page Number 3 5 7 8 8 9 9 10 13 18 20 21 22 23 26 29 30 32 32 34 21 22 39 49 52 54 54 56 57 57 58 59 60 61 62 63 63 1 RAD5A4 Description & Specifications Figure Number 39 40 41 42 43 44 45 46 47 48 49 50 51 2 Reconfigurable Arithmetic Datapath Figure Name Configuration Timing - Initial Portion Configuration Timing - Mid-Cycle Portion Configuration Timing - Continue Portion Configuration Timing - Halt Portion Configuration Timing with Invalid Preamble Minimizing Configuration Timing - Mid-Cycle Portion Detailed Configuration Timing - Mid-Cycle Portion Synchronous Configuration Timing - Initial Portion Synchronous Configuration Timing - Mid-Cycle Portion Synchronous Configuration Timing - Continue Portion Synchronous Configuration Timing - Halt Portion Multiple RAD5A4 Configuration Configuration Data Word Counter March 1997 Page Number 70 70 71 71 74 78 79 80 81 81 82 87 88 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Description & Specifications RAD5A4 RECONFIGURABLE ARITHMETIC DATAPATH DEVICE DATAPATH SOLUTIONS . . . SMALLER, FASTER, SOONER INFINITE TECHNOLOGY CORPORATION Infinite Technology Corporation Phone: 972-437-7800 March 1997 1 RAD5A4 Description & Specifications Reconfigurable Arithmetic Datapath Product Status Infinite Technology Corporation uses various product status markings to designate phases of documentation as it relates to the products. The markings appear at the beginning of each data sheet. The following Data Sheet Classification definitions explain the status of the specifications presented in this Data Book. Definitions Data Sheet Classification Objective Specification Product Status Formative or In Design Preliminary Specification Preproduction Product Production Specification Full Production 2 Definition This data sheet reflects the target design specifications for product development. Specifications may change in any manner without notice. This data sheet reflects preliminary data based on engineering samples. Characterization tests have not been completed on some parameters. Supplementary data will be published upon availability. Specification changes may be made at any time without notice to improve the design and supply the best possible product. This data sheet reflects Final Specifications. Infinite Technology Corporation reserves the right to make changes in its products without notice in order to improve design or performance characteristics. table 1 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Description & Specifications Part Number Description Part number ordering information for ITC devices is shown in the following diagram. For information on specific package, speed, operating temperature combinations, and interface type, refer to individual device data sheets in this data book, or contact ITC Marketing at (214) 437-7800. RAD 5A4 - 100 T C Q 176 Pin Count Device Family 176 = 176 pins RAD = Reconfigurable Arithmetic Datapath Device Package Type Q = Thin plastic quad flat pack (TQFP) H = Power TQFP Operating Temperature Range C = Commercial (0 to +70C) Interface Type T = 5 V TTL C = 5 V CMOS V = 3.3 V CMOS Operating Clock Frequency Designation in MHz -100 = 100 MHz -70 = 70 MHz -60 = 60 MHz -40 = 40 MHz (5V only) (5V only) Device Number 5A4 = 5 internal data buses / 4 MacroSequencers figure 1 Device Type Operating Clock Frequency (MHz) Interface Type Operating Temperature Range Device Package Type Number of Pins RAD5A4 -70, -100 T, C C Q,H 176 -40, -60 V table 2 Infinite Technology Corporation Phone: 972-437-7800 March 1997 3 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Reconfigurable Arithmetic Datapath Device High-Speed Accelerator for Data Stream Algorithms The RAD5A4 is a high speed accelerator for data stream algorithms. It contains four independent 16-bit fixed-point programmable processors called MacroSequencers that together execute Multiple Instructions on Multiple Data paths (MIMD). The MacroSequencers may operate independently or combined for even greater performance in those systems requiring real-time operation. High-Performance Multiply-Accumulate Operating at 100 MHz and 75-100% multiplier efficiency across a wide range of applications, the RAD5A4 MacroSequencer architecture provides: * One 16 by 8 multiply-accumulate (MAC) per clock cycle * Up to 400 Million 16 by 8-bit MACs per second or * Up to 200 Million 16 by 16-bit MACs per second Multiplier efficiency is enhanced with local I/O Registers, 1-port and 3-port Memories using smart Index Registers. The multiplier's accumulator is 48 bits to support extended filter and linear transform computations. Multiple Operations per Clock Cycle Each RAD5A4 MacroSequencer is designed with a Long Instruction Word (LIW) architecture enabling multiple operations per clock cycle. Independent operation fields in the LIW control the MacroSequencer's data memories, 16-bit adder, multiplier-accumulator, logic unit, shifter, and I/O registers so they may be used simultaneously with branch control. The pipelined architecture allows up to seven operations of the execution units during each clock cycle. * 3 - 7 Operations per clock cycle per MacroSequencer * 300 - 700 Million operations per second per MacroSequencer * 1 to 2 Billion operations per second per RAD5A4 The RAD5A4 LIW architecture optimizes performance allowing algorithms to be implemented with a small number of long instruction words. Each MacroSequencer holds thirty-two LIWs, each capable of 3-7 operations. 4 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Data Stream Processing The RAD5A4 provides a cost effective, quick time-to-market solution for High Speed Data Stream requirements in imaging and simulation applications such as Video, Real-time Custom Array, Parallel Processor, Medical and Photo Manipulation. Input Data Stream RAD5A4 Math Algorithm Output Data Stream The RAD5A4 takes one or more input data streams, applies high-speed arithmetic algorithms, and outputs one or more data streams. RAD5A4 Components The heart of the RAD5A4 consists of the four MacroSequencers which are supported by: * * * * five global 16-bit buses, connections to 64 I/O pins and 16 input pins, a built-in Dual PLA with 8 I/O pins and 8 input pins, five independent clocks which drive four MacroSequencers and the Dual PLA at clock rates up to 100 MHz. Simplified RAD5A4 Operational Block Diagram MS2I/O[15:0] MS3I/O[15:0] MacroSequencer 2 MacroSequencer 3 MacroSequencer 0 MacroSequencer 1 MS0I/O[15:0] MS1I/O[15:0] Bus4IN[15:0] Bus 4 PLAI/O[7:0] Dual PLA Bus0 to 3 Control Bus PLAIN[7:0] figure 2 Infinite Technology Corporation Phone: 972-437-7800 March 1997 5 RAD5A4 Reconfigurable Arithmetic Datapath PLA The RAD5A4 contains a Dual PLA which may be used for initiating stream processes, output enable signal generation, and glue interface. The Dual PLA is often referred to simply as the PLA. Package The RAD5A4 is available in the 176-pin 24 x 24 mm plastic Thin Quad Flat Pack (TQFP) and Power TQFP packages. RAD5A4 Performance The RAD5A4 accelerates arithmetic algorithms such as: * * * * * * * * * Discrete Cosine Transform (DCT) Inverse Discrete Cosine Transform (IDCT) Finite Impulse Filter (FIR) filter at video speeds Fast Fourier Transform (FFT) analysis Array processing Convolution Linear transformations Signal processing and formatting Process control For example, these speeds are typical of RAD5A4 performance: Algorithm 1024 complex 16-bit FFT* 5 by 5 Convolution 3 by 3 Convolution 8 pt DCT (8 bit) 8 pt IDCT (8 bit) 2-D DCT (8 bit) 2-D IDCT (8 bit) 16 Tap FIR 64 Tap FIR YUV to RGB Color Space Conversion table 3 No. of RAD5A4s 1 1 1 1 1 8 8 1 1 1 Data Stream Speed 205 s 70 ns 30 ns 110 ns 100 ns 220 ns 200 ns 80 ns 320 ns 30 ns * Computation of inner most loop only. Refer to FFT RAD Note. 6 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Imaging Applications Imaging applications require many multiply-accumulates and benefit from greater performance. The RAD5A4 improves these imaging applications: * * * * * * * Video filter Multi-media image scaling and image functions Medical instrumentation Photo manipulation Satellite Radar Sonar Video Filter Application R A/D Video Input RAD5A4 Math Algorithm 3Channel D/A G B figure 3 Arithmetic Accelerator Applications * * * * * * * * * Communications (Linear transformations) Digital Compression Robotics FPGA Coprocessor DSP Coprocessor Avionics Encryption 2D and 3D Digital Filtering FFT Noise Filtering Infinite Technology Corporation Phone: 972-437-7800 March 1997 7 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 as a Coprocessor RAD5A4 as a Coprocessor Micro-Computer DSP FPGA RAD5A4 Math Algorithm Input Data Stream Output Data Stream figure 4 RAD5A4 in Matrix Processing RAD5A4 devices may be combined into blocks of any number of MacroSequencers for larger algorithms. Matrix Processing Output Data Stream Input Data Stream RAD5A4 Memory Control FPGA FPGA Data and Control Buses figure 5 One or more FPGAs, DSPs, or other microprocessors may be used for interfacing to the Buses. 8 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 for Video Filtering NTSC is an interlaced video protocol which requires a frame buffer for 2dimensional applications. In less complex applications, a frame buffer may not be necessary. Reconfigurable Video Filter RAD5A4 Video Filter NTSC / PAL Input A/D Video Decoder FPGA Switch Matrix D/A Video Encoder Enhanced NTSC / PAL Ouput Frame Buffer figure 6 FFT Noise Filtering Noise Removal in Video and Audio RAD5A4 Time domain input with low frequency noise FFT Transform to frequency domain and separate low frequency noise from signal R Optional Filter RAD5A4 G Inverse FFT From frequency Bto time domain Filtered time domain output with noise reduction figure 7 Infinite Technology Corporation Phone: 972-437-7800 March 1997 9 RAD5A4 Reconfigurable Arithmetic Datapath Ease of Implementation Applications development is simplified with the following features: * * * * * Programming is readily implemented using RADware design tools. Predictable timing for arithmetic algorithms. Example PLA configurations are predefined in the RADware design tools. 5 V TTL, 5V and 3.3 V CMOS interface Rapid Reconfiguration in less than 150 s Each MacroSequencer is programmed using the RAD5A4 assembly language. It is a hardware oriented instruction set with only fourteen Datapath operations and sixteen Controller operations. Each operation performs multiple low-level operations. Most operations may be executed during each clock cycle allowing multiple operations per cycle for high performance and efficient processing. The Dual PLA is programmed using a subset of the VHDL language. The MacroSequencer instruction code and PLA source code may be created in any text editor. These PLA and MacroSequencer source files are then compiled using a VHDL compiler and RAD5A4 assembler and combined by RAD5A4 software to produce a configuration file. A vector file is produced for VHDL simulation. These files are used to configure the RAD5A4 device and for simulation. When programming RAD devices, the design is separated into: * Arithmetic Algorithms to be programmed into the MacroSequencers and * Test Vectors and * Process initiation and response, handshake, and protocol logic to be programmed into the Dual PLA. .vec .msa .vhd Test Vectors MacroSequencer Source Code VHDL Design File RADware Combines Source Files to create Configuration File and Simulation File .cfg .sim Configuration File Simulation File figure 8 10 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Several standard configurations that bypass the PLA are provided within the RAD software package. These options will program the PLA to do nothing while connecting the MacroSequencers to external pins. Dual PLA or External Control Signals MacroSequencers may execute independently in two ways: Each MacroSequencer or pair may execute independently from each other with programs initiated from either the Dual PLA or the external control pins. Design Tools The RAD5A4 is fully supported by ITC's RADwareTM system. This system contains a VHDL compiler for programming the PLA, the MacroSequencer assembler, and the RAD5A4 Fitter which will combine the compiled files to produce reports, a configuration file to program the RAD5A4 and a vector file to use with the VHDL model and a simulator. A VHDL model and test-bench is provided for testing and debugging applications. This VHDL model can be used with Vantage or Model Technology VHDL simulators for running test vectors and verifying design operation. The RADwareTM system is offered with DOS or Windows interface. In-Circuit Reconfigurability . . .Great Time-to-Market The RAD5A4 is the first in a family of Reconfigurable Arithmetic Datapath (RAD) devices designed specifically for use in datapath applications that demand high-speed arithmetic operations on a data stream. The RAD5A4 can be reconfigured at any time in less than 150 s. FPGAs and CPLDs are inefficient solutions for arithmetic and datapath applications. RAD5A4 devices specifically address these performance and density issues while retaining the flexibility and time-to-market benefits of other programmable devices. The low implementation cost and high arithmetic performance of RAD5A4 devices provide significant advantages for computationally intensive applications. RAD5A4 devices offer the simplicity of a digital filter, the dynamic flexibility of a DSP, and the speed of a custom ASIC. Infinite Technology Corporation Phone: 972-437-7800 March 1997 11 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath RAD5A4 Reconfigurable Arithmetic Datapath Device High Speed Accelerator for Data Stream Algorithms Architecture Description The RAD5A4 is composed of an array of four 16-bit fixed-point processors, called MacroSequencers, that can be individually initiated either by using the Dual PLA-based built-in periphery logic or directly from the control pins. Five 16-bit data buses connect the MacroSequencers and 80 pins to allow data to be shared and passed according to design needs. In addition each pair of MacroSequencers is coupled directly by two private 16-bit buses. These private buses allow each pair of MacroSequencers to be paired together for additional data sharing. The heart of the RAD5A4 are the four MacroSequencers which are supported by: * Five global 16-bit buses, (bus0 to 4), * Connections to 64 I/O pins (MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], MS3I/O[15:0]) and 16 input pins (BUS4IN[15:0]), * Five independent clocks which drive the PLA and 4 MacroSequencers at clock rates up to 100 MHz. * A built-in Dual PLA. MacroSequencers Each RAD5A4 MacroSequencer is designed with a Long Instruction Word (LIW) architecture enabling multiple operations per clock cycle. Independent operation fields in the LIW control the MacroSequencer's data memories, 16bit adder, multiplier-accumulator, logic unit, shifter, and I/O registers so they may be used simultaneously with branch control. The pipelined architecture allows up to seven operations of the execution units during each cycle. The RAD5A4 LIW architecture optimizes performance allowing algorithms to be implemented with a small number of long instruction words. Each MacroSequencer may be configured to operate independently, or can be paired for some 32-bit arithmetic operations. MacroSequencer0, 1, 2, and 3 are referred to as MacroSequencer(n) or MSn where the n specifies the respective MacroSequencer number. 12 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description The data flow to and from the MacroSequencers is shown here: Simplified RAD5A4 Control and Data Flow Diagram MS2I/O[15:0] MS3I/O[15:0] Bus0 Bus1 Bus2 Bus3 BUS4IN[15:0] PLAI/O[7:0] PLAIN[7:0] Dual PLA 12 MacroSequencer 2 MSPair32 16 16 MSPair23 MacroSequencer 3 16 16 8 8 MSn Direct Control and Status Pins 20 Bus4 16 Control Bus 32 MS0I/O[15:0] 16 16 8 8 MacroSequencer 0 8 MSPair10 16 16 MSPair01 MacroSequencer 1 MS1I/O[15:0] figure 9 Built-In Glue Logic A programmable Dual PLA is built into the device to initiate processes in the MacroSequencers and provide glue logic interface capabilities. The PLAI/O[7:0] pins can be configured individually as input only or output only pins. These can be used for external interface control. Process initiation and response may be provided externally via input pins directly to the MacroSequencers or it may be provided by the programmable PLA via the control bus. Infinite Technology Corporation Phone: 972-437-7800 March 1997 13 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Operation Modes The RAD5A4 operates in either a normal operating mode or a configuration mode. * The RAD5A4 is configured during the Active Configuration mode which allows each MacroSequencer's instruction memory and Data Memories and Dual PLA memory to be programmed. * In the Normal Operating mode, the RAD5A4 MacroSequencers concurrently execute the Long Instruction Words (LIWs) programmed into each MacroSequencer's instruction memory. * The Passive Configuration mode disables the device I/O pins and disables the device from being configured, so that other RAD5A4s in the same circuit may be configured. Paired MacroSequencer Operational Support MacroSequencers may be used individually for 16-bit operations or in pairs for standard 32-bit addition, subtraction, and logic operations. When pairing, the MacroSequencers are not interchangeable. MacroSequencers 0 and 1 form one pair, and MacroSequencers 2 and 3 form the other pair. The least significant sixteen bits are processed by MacroSequencers 0 and 2. A summary of this information is listed here: Paired MacroSequencers First Pair MacroSequencer number Least significant 16-bits Most significant 16-bits Paired MacroSequencer 0 1 table 4 1 0 Second Pair 2 3 3 2 Paired MacroSequencer Bus Names Each pair of MacroSequencers have two private data buses between them labeled MSPair(nm) and MSPair(mn) where the first n or m references the MacroSequencer that sources the data, and the second n or m references the recipient MacroSequencer. The n refers to the current MacroSequencer, and the m refers to the other MacroSequencer in the pair. The source of the data is from the OutRegB signal of the MacroSequencer(m). The four data buses between paired MacroSequencers are: Name of Data buses between Paired MacroSequencers MSPair01 MSPair10 MSPair23 MSPair32 14 March 1997 From MacroSequencer 0 1 2 3 table 5 To MacroSequencer 1 0 3 2 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description RAD5A4 Data Bus The RAD5A4 Data Bus is composed of five global 16-bit data buses that can be simultaneously accessed by all of the MacroSequencers. Four of the buses, bus0, bus1, bus2, and bus3, are associated with MacroSequencer0, 1, 2, and 3 respectively. The fifth bus, bus4, always receives data from BUS4IN[15:0] pins. Data bus0, bus1, bus2, and bus3 receive data from either MacroSequencer output registers or from MacroSequencer I/O pins. Each MacroSequencer has input access from all of the buses. However, each MacroSequencer may only place data onto its respective busn from its output register, OutRegA or onto its MSnI/O pins. Busn may receive inputs from either MSnI/O[15:0] pins or from the output register, OutRegA of MacroSequencer(n). Input/Output between the busn and MSnI/O[15:0] pins are determined by configuration bits and instruction memory in each MacroSequencer and MSnOE and oepla[n]. RAD5A4 Control Bus The Control Bus is used to communicate control, status, and output enable information between the MacroSequencer and the PLA or external MacroSequencer pins. Control Signals Two control signals sent to the MacroSequencer are described in the MacroSequencer Datapath Controller section. They are used to: * Initiate one of two available LIW sequences, * Continue execution of the LIW sequence, or * Acknowledge the MacroSequencer status flags by resetting the send and await state bits. MacroSequencer(n)'s Configuration bit 5 determines whether the control signals are from the MSnCTRL[1:0] pins or from the PLA0 CtrlReg[2n+1:2n] signals. Configuration bits may be selected using the RADware design tools. Infinite Technology Corporation Phone: 972-437-7800 March 1997 15 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Status Signals The MacroSequencer always executes the LIW in the LIW Register on every clock cycle. The Await and Send status signals from the MacroSequencer are described in the MacroSequencer Datapath Controller section and indicate: * The Program Counter is sequencing. * The MacroSequencer is in the send state, and it has executed a specific LIW. The Program Counter is continuing to sequence. * The MacroSequencer is in the await state, and it has executed a specific LIW. The Program Counter is not continuing to sequence, and it is awaiting further commands before resuming. Two status signals, Send and Await, sent from the MacroSequencer(n)s are output both to the MSnAWAIT and MSnSEND pin outputs and to the Dual PLA input selectors. The MSn direct control pins shown in the Simplified RAD5A4 Control and Data Flow diagram (figure 8) are the control interface signals which connect directly between the pins and each MacroSequencer. These signals (MSnAwait, MSnSend, MSnCTRL[1:0], and MSnOE) are included in the table of MacroSequencer Control Interface Signals (table 6). Output Enable The output enable circuitry for MacroSequencer(n) is described in the Output Selection description and allows for output enable to be: * From the Dual PLA oepla[n] outputs or from MacroSequencer(n) output enable MSnOE pins. * Always output * Always input (the power up condition) * Optionally inverted. MacroSequencer Control Interface Signals The following table lists the names of the control, status, and output enable signals that interface with the MacroSequencers. MacroSequencer MacroSequencer0 MacroSequencer1 MacroSequencer2 MacroSequencer3 Status Signals To Pins & Dual PLA MS0AWAIT, MS0SEND MS1AWAIT, MS1SEND MS2AWAIT, MS2SEND MS3AWAIT, MS3SEND Control Signals From Pins Output Enable From Pins MS0CTRL[1:0] From Dual PLA PLACtrl0[1:0] MS0OE From Dual PLA oepla[0] MS1CTRL[1:0] PLACtrl1[3:2] MS1OE oepla[1] MS2CTRL[1:0] PLACtrl2[5:4] MS2OE oepla[2] MS3CTRL[1:0] PLACtrl3[7:6] MS3OE oepla[3] table 6 16 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Input Clocks Five input clocks are provided to allow the RAD5A4 to process multiple data streams at different transmission speeds. There is one clock for each MacroSequencer, and a separate clock for the PLA. Each MacroSequencer can operate on separate data paths at different rates. The clock signals can be connected, for synchronization between the four MacroSequencers and the Dual PLA. The PLA clock (PLACLK) is used for Active Configuration Mode. System Constraints The MacroSequencers and PLA change states on the rising edge of their respective clock signals. Signals between the Dual PLA and the MacroSequencers are resynchronized at the receiving MacroSequencer or Dual PLA. Techniques should be employed to reduce timing skew which may occur due to printed circuit board layout. When using the RAD5A4 at high clock frequencies, data should be loaded and captured synchronously with proper set-up and hold times. The I/O bandwidth on MSnI/O[15:0] pins and BUS4IN[15:0] is one-half of the MacroSequencer clock frequency. * Data to be input should be asserted on the pins for one MacroSequencer clock period before the data is to be captured in a MacroSequencer's registers. * Data to be output on these pins should be asserted one MacroSequencer clock period before the data is to be captured by external circuitry. Infinite Technology Corporation Phone: 972-437-7800 March 1997 17 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath MacroSequencer Description Each MacroSequencer is identical and composed of two functional blocks, the Arithmetic Datapath, and the Datapath Controller. The 3-port and 1-port memories are accessed by the arithmetic data path. The instruction memory, 3port and 1-port memories may be loaded during Active Configuration Mode. MacroSequencer (n) 3-Port Memory 1-Port Memory Data In bus0, bus1, bus2, bus3, bus4, MSPairmn Arithmetic Datapath 6 x 16 Adder Status bits: Equal, Overflow, Sign Control Signals MSnCTRL[1:0] PLACtrln[1:0] MSnOE oepla[n] 6 3 Data I/O Interface 2 x 16 busn MSPairnm 1 x 16 MSnI/O[15:0] 42 LIW Control bits 2 Datapath Controller Status Signals MSnAwait MSnSend Instruction Memory figure 10 The control signals may initiate one of two programmed LIW sequences in instruction memory in normal operating mode. Once a sequence begins, it will run, or loop indefinitely until stopped by the control signals. An await state programmed into the LIW sequence will stop the Program Counter from continuing to increment. The LIW sequences are a combination of data steering, data processing, and branching operations. Each MacroSequencer may execute a combination of branch, memory access, logic, shift, add, subtract, multiply-accumulate, and input / output operations on each clock cycle. The instruction memory can be reloaded dynamically at any time by transitioning to Active Configuration Mode which will also initialize all registers in the entire device. MacroSequencer0, 1, 2, and 3 are referred to as MacroSequencer(n) or MSn where the n specifies the respective MacroSequencer number. 18 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description MacroSequencer Arithmetic Datapath The MacroSequencer Arithmetic Datapath is a pipelined structure where data is processed in stages. There are nine basic elements in the MacroSequencer Arithmetic Datapath. Six of these are data processing functions and the other three are data steering functions. The data processing elements include: * * * * * * Multiplier-Accumulator (MAC), Adder, Shifter, Logic Unit, 3-port Data Memory, and 1-port Data Memory. The data steering functions include the: * Input Register block to capture any two inputs, * Input Selector for selecting any three operands for data processing elements, and * Output Register block to select which two of the data processing elements are stored. The processor core contains four parallel data processing units: the MultiplierAccumulator (MAC), Adder, Logic Unit, and Shifter. Each data processing unit runs independently of the others allowing the execution of multiple operations per cycle. Inputs to MacroSequencer(n) include: * Direct access to sixteen I/O pins (MSnI/O[15:0]). * Five 16-bit internal buses (bus0, bus1, bus2, bus3, and bus4) where busn may be connected to MSnI/O[15:0] or the output register, OutRegA from MacroSequencer(n). Bus4 is always connected to BUS4IN[15:0] and is shared between the MacroSequencers and the Dual PLA. * The Paired MacroSequencer 16-bit bus MSPair(mn) from MacroSequencer(m)'s OutRegB to MacroSequencer(n)'s Input Register. Infinite Technology Corporation Phone: 972-437-7800 March 1997 19 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath MacroSequencer (n) Datapath Block Diagram mem2 Register mem0 3-Port Memory 1-Port Memory MAC bus0 bus1 InRegA InRegB InBusA InBusB Logic Unit MSPairmn InBusC Constant Adder Output Selector bus4 Input Selectors bus3 Adder Status Input Registers bus2 MultOutA,B OutRegA OutRegB I/O Interface mem1 bus n MS nI/O MSPairnm Shifter '0' figure 11 Each of these data processing functions in the MacroSequencer Datapath Block Diagram is discussed individually in the following sections. They are controlled by the operation fields in the MacroSequencer's LIW Register. In the MacroSequencer discussions that follow, the terms `external' and `internal' do not refer to signals external and internal to the RAD5A4 device, but only to signals external and internal to an individual MacroSequencer. Relevant LIW Register control bits are shown in MacroSequencer Arithmetic Datapath data processing functions. They are defined in the RAD5A4 Long Instruction Word Appendix. 20 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Input Registers The 16-bit input registers are named InRegA and InRegB. There are six external inputs and one internal input available to the Input Registers. MacroSequencer (n) Input Registers bus4 Constant bus0 bus1 bus2 bus3 MSPairmn 16 16 16 16 16 InRegA 16 InRegB 16 16 16 LIW[4:2] Register LIW[7:5] figure 12 There are several possible input selections for each MacroSequencer Input Register: * * Five 16-bit internal buses (bus0, bus1, bus2, bus3, and bus4) The 16-bit bus from the partner MacroSequencer(m)'s OutRegB in each pair labeled MSPair(nm), and A Constant (0-65535) generated from LIW Register bits LIW[43:28]. * The Constant introduces 16-bit constants into any calculation. The constant of the MacroSequencer shares internal signals with the MacroSequencer Controller as well as the MAC, the Shifter, and the Logic Unit. Since the Constant field of the LIW is shared, care must be taken to insure that overlap of these signals does not occur. The RAD5A4 Assembler detects and reports any overlap problems. Related Assembly Operations: Syntax in <src>,<dest> Infinite Technology Corporation Phone: 972-437-7800 Allowed values for arguments <src>: bus0, bus1, bus2, bus3, bus4, pair, 65535 <dest>: inrega, inregb table 7 March 1997 0- 21 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath The pair parameter selects MSPair(mn) which is from OutRegB of the other member of the pair of MacroSequencers. When no operation occurs, the input register holds its data. Resource Conflicts: When using a constant value, there is a conflict with the MAC, Logic Unit, Shifter, and some Datapath Controller instructions. Input Selector The Input Selector generates the InBusA, InBusB, and InBusC signals. Data on these buses are independent. There are controls on InBusB to enable the number zero to be used and to invert the selected result. InBusA and InBusB are available to the MAC, Adder, and Logic Units. InBusC is available only to the Shifter. MacroSequencer Input Selector InRegA OutRegA OutRegB mem1 16 '0' mem0 InRegB 16 16 16 16 InBusA 16 InBusB 16 InBusC 16 LIW[9:8] 16 16 LIW[13] mem2 16 LIW[12:10] LIW[14] figure 13 Inputs to the Input Selector include: * * * * * InRegA and InRegB from the Input Register, OutRegA and OutRegB from the Output Register, Mem1 and mem2 from the 3-port Memory read ports 1 and 2 respectively, Mem0 from the 1-port Memory read port, and Constant `0' which is generated in the Input Selector and does not involve LIW Register bits LIW[43:28]. Control signals from the MacroSequencer Controller determine which three of the eight possible inputs are used and whether InBusB is inverted or not. The Input Selector is automatically controlled by RADware assembly language operations for the Multiplier, Adder, Shifter, and Logic Unit and does not require separate programming. 22 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description The input selections are controlled by the same assembly operations used by the MAC, Adder, Logic Unit and Shifter. Multiplier-Accumulator The Multiplier-Accumulator (MAC) is a three-stage, 16 by 8 multiplier capable of producing a full 32-bit product of a 16 by 16 multiply every two cycles. The architecture allows the next multiply to begin in the first stages before the result is output from the last stage so that once the pipeline is loaded, a 16 by 8 result (24-bit product) is generated every clock cycle. 16 by 8 Multiplier - Accumulator 48 InBusB 16 16 16 8 16 8 24 24 48 bit Accumulator Operand B OutRegB 16 16 x 8 bit Multiplier Operand A mem0 InBusA 48 16 To Adder: 16 16 16 16 16 MultOutA MultOutB LIW[42:41] LIW[47,44] Register LIW[43,40] figure 14 Input Stage The MAC input stage loads operands A and B and assures proper byte alignment for the multiplier. The multiplier input multiplexers serve two purposes: 1) They align the high or low bytes from operand B for the multiplier which allows 16 by 8 or 16 by 16 multiply operations; and 2) They allow the inputs to be selected from three different sources for each operand: a) Operand A is selected from the 1-port memory, InBusA, or operand A from the previous cycle. b) Operand B is selected from the high byte of OutRegB, InBusB, or the least significant byte of the previous operand B. Infinite Technology Corporation Phone: 972-437-7800 March 1997 23 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Related Assembly Operations: Syntax Allowed values for arguments mult1 <srca>, <srcb> <srca>: inrega, outrega, outregb, mem1, mem0 <srcb>: inregb, outrega, outregb, mem2, mem0, 0 mult1 hold table 8 Resource Conflicts: Using the mem0 or outregb arguments makes InBusA and InBusB available for other assembly operations. A mult1 hold operation holds operand A and moves the low byte of operand B to the Multiplier stage input. Multiplier Stage The Multiplier produces a 24-bit product from the registered 16-bit operand A and either the most significant byte (8-bits) or the least significant byte of operand B. Accumulator Stage The third stage aligns and accumulates the product. Controls in the accumulator allow the product to be multiplied by: * 1 when <weight> is low, or * 28 when <weight> is high. The result is then: * Added to the result in the accumulator when <enable> is acc, * Placed in the accumulator replacing any previous value when <enable> is clr, or * Held in the accumulator in lieu of a mult3 operation. A mult3 operation must follow two cycles after a mult1 operation. The accumulator holds its data when no mult3 is used. The accumulator output divides the 48-bit output into four 16-bit parts called low (bits[15:0]), mid (bits[31:16]), high (bits [47:32]) and norm (bits[30:15]). The low, mid, and high bits are used in conversion. Select norm when only the top 16 bits of a signed multiplication result is required. Related Assembly Operations: Syntax Allowed values for arguments mult3 <weight>, enable> add1 mult, <pos> <weight>: high, low <enable>: clr, acc <pos>: low, mid, high, norm table 9 Cycles per Multiply 24 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description The number of cycles required for Multiplies and MACs are shown in these tables. Cycles Between New Multiplies Multiply Accuracy Cycles 16 by 8 16 bits 24 bits 16 bits 32 bits table 10 1 2 2 3 16 by 16 Cycles Between New Multiply - Accumulates of n Products Multiply 16 by 8 16 by 16 Accuracy Cycles 16 bits 32 bits 48 bits 16 bits 32 bits 48 bits table 11 n n+1 n+2 2n 2n + 1 2n + 2 The MAC internal format is converted to standard integer format by the Adder. For this reason, all multiply and multiply-accumulate outputs must go through the Adder. If a 16 by 8 bit MAC is desired, new operands are loaded every cycle. The Multiplier results in a 24-bit product which is then accumulated in the third stage to a 4- bit result. This allows at least 224 multiply-accumulate operations before overflow. If only the upper 16 bits of a 24-bit result are required, the lower 8 bits may be discarded. If more than one 16-bit word is extracted, the accumulated result must be extracted in a specific order. First the lower 16-bit word is moved to the Adder, followed in order by the middle 16 bits and then the upper 16 bits. This allows at least 216 of these 16 by 16-bit multiply-accumulate operations before overflow will occur. For a 16 by 16-bit MAC, new operands may be loaded every other cycle. Example software is in the MacroSequencer Assembly Language documentation. Adder The Adder produces a 16-bit result of a 16 by 16-bit addition, subtraction, or 16-bit data conversion to two's complement every cycle. The Adder is also used for equality, less-than and greater-than comparisons. The Adder is a twostage structure: the input multiplexers with the first adder stage and the second Infinite Technology Corporation Phone: 972-437-7800 March 1997 25 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath adder stage. The architecture allows the next adder operation to begin in the first stage before the result is output from the last stage. The input multiplexers select one of two sources of data for operation by the Adder. The operands are selected from either InBusA and InBusB, or from the Multiplier. Select InBusA and InBusB for simple addition or subtraction and setting the Adder Status flags. Select the multiplier outputs, MultOutA and MultOutB, for conversion. Adder 16 InBusA 16 MultOutB 16 InBusB 16 16 16 16 16 Carry Out a=b Out Adder (pipe 2) MultOutA Adder (pipe 1) Carry In a=b In 1 4 16 3 Adder Status Flags: Equality, Overflow, Sign Output Selector LIW[15] config bit[3:2] LIW[16] Register figure 15 The first adder stage receives the operands and begins the operation. The second adder stage completes the operation and specifies the output registers in the Output Selector where the result will be stored. The two adder stages may be controlled separately for addition and subtraction operations. 26 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Related Assembly Operations: Syntax Allowed values for arguments add1 <oper1>, <oper2> add1 mult, <pos> add2 [<dest1> [, <dest2>]] sub1 <srca>, <srcb> sub2 [<dest1> [, <dest2>]] <oper1>: inrega, outrega, outregb, mem1 <oper2>: inregb, outrega, outregb, mem2, mem0, 0 <pos>: low, mid, high, norm <dest1>, <dest2>: outrega, outregb <srca>: inrega, outrega, outregb, mem1 <srcb>: inregb, outrega, outregb, mem2, mem0, 0 <dest1>, <dest2>: outrega, outregb table 12 The add1 mult operation is used for data conversion in the Accumulator and allows InRegA and InRegB to be available for other operations in the same cycle. The sub1 operation inverts the InBusB selection. If sub2 is used, Carry In is set to a logical `1'. Adder Configuration Bits / Switches Configuration bit[3] selects 32-bit or 16-bit addition or subtraction. The 32/16 bit configuration bit is set in the RADware design tools. For successful 32-bit operation, MacroSequencer1 and/or MacroSequencer3 should have the 32/16bit configuration bit set for 32-bit operation. The MacroSequencer0 and MacroSequencer2 32/16-bit configuration bit should always be set for LOW for proper operation. When in 32-bit mode, the a=b Out signal tells the other MacroSequencer in the pair if Operand A and Operand B are equal. The a=b In signal is input ot the upper 16 bits. When MacroSequencer1 is in 32-bit mode, its External Carry In is from the External Carry Out from MacroSequencer0. When MacroSequencer3 is in 32bit mode, its External Carry In is from the External Carry Out from MacroSequencer2. External Carry In for MacroSequencer0 and MacroSequencer2 is from specialized circuitry for addition and subtraction carries. Configuration bit[2] selects whether the operands are signed values or unsigned values. The signed/unsigned configuration bit is set with directives when programming the MacroSequencer. Refer to the MacroSequencer Configuration bits discussion and the Assembler Directives discussion in the MacroSequencer Programming Section for more detail. Infinite Technology Corporation Phone: 972-437-7800 March 1997 27 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Adder Status Bits The Equal, Sign, Overflow, and Carry flags are set two cycles after an addition operation (add1 or sub1) occurs and remain in effect for one clock cycle: * The Equal flag is set when the two operands are equal during an addition operation. * The Overflow flag is set when the result of an addition or subtraction results in a 16-bit out-of-range value. * When the adder is configured for unsigned integer arithmetic, Overflow = Carry. Range = 0 to 65535 * When the adder is configured for signed integer arithmetic, Overflow = Carry XOR Sign. Range = -32768 to +32767 * The Sign flag is set when the result of an addition or subtraction is a negative value. * The Carry flag indicates whether a carry value exists. Conversion The Adder may be used to convert the data in the Accumulator of the Multiplier to standard integer formats when inputs are selected from the output of the MAC. The MAC outputs are shown as MultOutA and MultOutB on the diagrams. Since the Accumulator is 48 bits, the multiplier's accumulated result must be converted in a specific order: lower-middle for 32-bit conversion, and lowermiddle-upper for 48-bit conversion. Once the conversion process is started, it must continue every cycle until completed. Signed number conversion uses bits 30:15. Conversion is explained in more detail in the MacroSequencer Assembly Language examples. Shifter Shift Mode (type) signals control which Shifter functions are performed: * Logical Shift Left by n bits (shift low order bits to high order bits). The data shifted out of the Shifter is lost, and a logical `0' is used to fill the bits shifted in. * Logical Shift Right by n bits (shift high order bits to low order bits). The data shifted out of the Shifter is lost, and a logical `0' is used to fill the bits shifted in. * Arithmetic Shift Right by n bits. This is the same as logical shift right with the exception that the bits shifted in are filled with Bit[15], the sign bit. This is equivalent to dividing the number by 2n. * Rotate Shift Left by n bits. The bits shifted out from the highest ordered bit are shifted into the lowest ordered bit. * Normalized Shift Right by 1 bit. All bits are shifted one lower in order. The lowest bit is lost and the highest bit is replaced by the Overflow Register bit of the Adder. This is used to scale the number when two 16-bit words are added to produce a 17-bit result. 28 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Logical, Arithmetic and Rotate shifts may shift zero to fifteen bits as determined by the Shift Length control signal. Shifter Adder Status Overflow 1 InBusC 16 Shifter LIW[35:32] n LIW[38:36] type 16 Output Selector figure 16 The Shift Mode (type) and the Shift Length (n) controls are shared by the Constant word; therefore, only one of these functions may be used on any one cycle. Constant inputs to the MacroSequencer are shown in the MacroSequencer Datapath Block Diagram. Related Assembly Operations: Syntax shift <src>, <type>,<length>, <dest1> [, <dest2>] shift <src>, normal, <dest1> [,<dest2>] Infinite Technology Corporation Phone: 972-437-7800 March 1997 Allowed values for arguments <src>: inrega, outrega <type>: logicleft, logicright, arithmetic, rotate <length>: 0-15 or 0x0-0xf <dest1>, <dest2>: outrega, outregb <src>: inrega, outrega <dest1>, <dest2>: outrega, outregb table 13 29 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Logic Unit The Logic Unit is able to perform a bit-by-bit logical function of two 16-bit vectors for a 16-bit result. All bit positions will have the same function applied. All sixteen logical functions of 2 bits are supported. The Logic Function controls determine the function performed. Logic Unit InBusA 16 a InBusB 16 b Logic Unit 16 Output Selector LIW[31:28] figure 17 Related Assembly Operations: Syntax logic <oper>, <dest1> [, <dest2>] logic <oper>, <srca>, <dest1> [,<dest2>] logic <oper>, <srcb>, <dest1> [,<dest2>] logic <oper>, <srca>, <srcb>, <dest1> [, <dest2>] 30 March 1997 Allowed values for arguments <oper>: 0, 1 <dest1>, <dest2>: outrega, outregb <oper>: nota, a, <srca>: inrega, outrega, outregb, mem1 <dest1>, <dest2>: outrega, outregb <oper>: notb, b <src>: inregb, outrega, outregb, mem2, mem0, 0 <dest1>, <dest2>: outrega, outregb <oper>: nor, notab, anotb, xor, nand, and, xnor, notaorb, aornotb, or <srca>: inrega, outrega, outregb, mem1 <srcb>: inrega, outrega, outregb, mem2, mem0, 0 <dest1>, <dest2>: outrega, outregb table 14 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description The sixteen logical functions are: LIW[31:28] Operation Description 0000 0 logical `0' 1111 1 logical `1' 0011 a a 1100 a inverted value of a 1010 b b 0101 b inverted value of b 0001 nor A nor B 0010 ab not A and B 0100 ab A and notB 0110 xor A xor B 0111 nand A nand B 1000 and A and B 1001 xnor A xnor B 1011 a or b not A or B 1101 a or b A or not B 1110 or A or B table 15 The Logic Function controls are shared by the Constant word, the Logic Unit, the 1-port memory index register operations and the MAC Function. Only one of these functions may be used on any one cycle. The output is defined by the LIW bits as follows: Out[i] = (LIW[28] and not A[i] and not B[i]) or (LIW[29] and A[i] and not B[i]) or (LIW[30] and not A[i] and B[i]) or (LIW[31] and A[i] and B[i]) 1-Port Memory The 1-port memory supports single-cycle read and single-cycle write operations, but not both at the same time. There are 32 addressable 16-bit memory locations in the 1-Port Memory. A separate register is provided to store and maintain the result of a read operation until a new read is executed. Read and write operands control whether reading or writing memory is requested. No operation is performed when both the Read and Write controls are inactive. Only one operation, read or write, can occur per cycle. Index register I1P in the Datapath Controller provides the read and write address to the 1-port memory. The index register may be incremented, Infinite Technology Corporation Phone: 972-437-7800 March 1997 31 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath decremented, or held with each operation. Both the index operation and the read or write operation are controlled by the MacroSequencer LIW. 1-Port Memory OutRegA 1-port Address 16 32 x 16 RAM 5 16 LIW[1] mem0 LIW[0] Register figure 18 Related Assembly Operations: Syntax Allowed values for arguments oneport <oper> <oper>: write, read table 16 3-Port Memory The 3-port memory is a 16 x 16-bit RAM that supports two read and one write operation on each clock cycle. The two read ports may be used independently; however, data may not be written to the same address as either read address in the same clock cycle. 3-Port Memory OutRegB 3-port Read1 Address 3-port Read2 Address 3-port Write Address 16 mem1 16 mem2 16 4 4 16 x 16 RAM LIW[45] 4 LIW[46] LIW[46,45,22] Register figure 19 Four index registers are associated with the 3-port memory. Two separate registers are provided for write indexing: Write Offset (I3PWO) and Write Index (I3PW). These two registers may be loaded or reset simultaneously or independently. Write Offset provides a mechanism to offset read index 32 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description registers from the Write Index by a fixed distance. Increment and Decrement apply to both write registers so that the offset is maintained. The two Read Index registers may be independently reset or aligned to the Write Offset. Related Assembly Operations: Syntax Allowed values for arguments memwrite memread1 memread2 no arguments no arguments no arguments table 17 Each index has separate controls and may be incremented, decremented, or held after each read or write operation. Syntax Allowed values for arguments setindex <value> setindex <valuew>, <value1>, <value2> <value>: 0-31 or 0x0-0x1f <valuew>: 0-15 or 0x0-0xf <value1>: 0-15 or 0x0-0xf <value2>: 0-15 or 0x0-0xf <m0>: none, reset <mw>: none, resetoffset, resetall <m1>: none, reset, align <m2>: none reset, align <d0>: none, inc, dec <dw>: none, inc, dec, rev <d1>: none, inc, dec, rev <d2>: none, inc, dec, rev <index>: readwrite0, write, read1, read2, all3port indexmode <m0>, <mw>, <m1>, <m2> indexdirect <d0>, <dw>, <d1>, <d2> <index> table 18 The setindex operation sets the index to a specified value. The indexmode operation resets or aligns the index values. The indexdirect operation controls whether the index values are incremented, decremented, or held after access. Smart Indexing Smart indexing operates multiple memory addresses to be accessed. This is particularly useful when the data is symmetrical. Refer to the DCT and symmetric filter RAD Notes for detailed examples. Symmetrical coefficients are accessed by providing the Write Offset from the center of the data and aligning both Read Indices to the Write Offset. The Read Indices may be separated by a dummy read. Additional simultaneous reads with one index incrementing and the other decrementing allows for addition or subtraction of data that uses the same or inverted coefficients. Infinite Technology Corporation Phone: 972-437-7800 March 1997 33 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Each index has separate direction controls. Each index may increment or decrement, and/or change its direction. The change in each index register's address takes place after a read or write operation on the associated port. 3-port Memory Index Pointers offset write offset read1 write index read2 figure 20 Smart indexing is ideal for Filter, and DCT applications where pieces of data are taken from equal distance away from the center of symmetrical data. The smart index method used in the 3-port Memory allows symmetrical data to be multiplied in half the number of cycles that would have normally been required. Data from both sides can be added together and then multiplied with the common coefficient. For example, a 6-tap filter which would normally take 6 multiplies and 7 cycles, can be implemented with a single MacroSequencer and only requires 3 cycles to complete the calculation. An 8-point DCT which normally requires 64 multiplies and 65 cycles can be implemented with a single MacroSequencer and only requires 32 clock cycles to complete the calculation. 34 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Output Selector The Output Selector controls the state of output registers OutRegA and OutRegB and controls the state of the MSnI/O[15:0] bus pins. Output Selector Input Selector Logic Unit Shifter Adder 16 16 16 OutRegA 16 LIW[18:17] Input Selector MSnI/O[15:0] InRegB 16 16 16 16 OutRegB LIW[21:19] Register figure 21 The Output Selector multiplexes five 16-bit buses and places the results on two 16-bit output registers which drive two on-chip buses and the MacroSequencer I/O pins. The Output registers may be held for multiple cycles. Inputs The output selector receives inputs from the: * Adder, * Logic Unit, * Shifter, * InRegB, and * MacroSequencer I/O MSnI/O[15:0] pins. Outputs The output selector places outputs for OutRegA and OutRegB. Output Register A, OutRegA, is available to the: * Input Selector, * Write port of the 1-port memory, * MSnI/O pins, and * Busn input from MacroSequencer(n) OutRegA. Data placed on busn is available to the other three MacroSequencers. Infinite Technology Corporation Phone: 972-437-7800 March 1997 35 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Output Register B, OutRegB, is available to the: * Write port of the 3-port memory, * Input Selector, * MAC, and * Paired MacroSequencer bus MSPair(nm) where: - OutRegB from MacroSequencer0 is the source for MSPair01. - OutRegB from MacroSequencer1 is the source for MSPair10. - OutRegB from MacroSequencer2 is the source for MSPair23. - OutRegB from MacroSequencer3 is the source for MSPair32. Related Assembly Operations: Syntax move no arguments; moves the value of InRegB to OutRegB no arguments; moves the value of the MSnI/O pins to OutRegB table 19 in pins, outregb 36 Allowed values for arguments March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description I/O Interface The I/O Interface selection for each MacroSequencer determines: * * Input source for data busn and The output enable configuration. MacroSequencer I/O Interface 16 MSnI/O[15:0] 16 16 16 To Output Selector (Input) OutRegA MSnOE oepla[n] '1' busn config bit[4] MSnI/O[15:0] Port 16 (Output) 1 1 OE config bit[7:6] config bit[8] figure 22 The I/O Interface diagram for the output enable circuitry represents the equivalent of the output enable selection for configuration bits 6, 7, and 8 in the normal operating mode. These MacroSequencer configuration bit selections are made in the RADware design tools. Busn Selection The input data on busn is selected from the MSnI/O[15:0] pins or the OutRegA output of MacroSequencer(n) by configuration bit 4. When MacroSequencer(n)'s associated busn is connected to the OutRegA signal, the MacroSequencer still has input access to the MSnI/O pins via the Output Selector. Output Enable Control Output Enable to the MSnI/O pins is controlled by configuration bit selections. Inputs to the output enable control circuitry include the MSnOE pin for MacroSequencer(n) and the oepla[n] signal. Infinite Technology Corporation Phone: 972-437-7800 March 1997 37 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath MacroSequencer Datapath Controller The MacroSequencer Datapath Controller contains and executes one of two sequences of Long Instruction Words (LIWs) that may be configured into instruction memory. The Datapath Controller generates LIW bits which control the MacroSequencer Arithmetic Datapath. It also generates the values for the 1-port and 3-port index registers. The controller accepts control signals from the PLA PLACtrl(n)[1:0] signals or external MSnCTRL pins which initiates one of two possible LIW sequences. It outputs Send and Await status signals to the PLA and to external MSnSEND and MSnAWAIT pins. The Datapath Controller operation is determined by MacroSequencer the contents of its LIW register and the two control signals. Components Each MacroSequencer Controller contains the following elements: * * * * * * Program Counter (PC), LIW Register which holds the currently executing LIW, 32 by 48-bit reprogrammable Instruction Memory, Two loop counters: Counter0 and Counter1, Return Stack for `calls' which holds 4 return addresses, and Index Registers for the 1-port and 3-port memories. Inputs include: * Controln signals for setting one of the two sequences, or issuing Run and Continue commands and * Adder status bits: Equal, Overflow, and Sign. Outputs include: * LIW instruction bits, * 1-port and 3-port memory addresses, and * Two single-bit Send and Await Status signals 38 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description The Datapath Controller is shown in the following diagram. 5 3 Adder Status Control Signals MSnCTRL 2 PLACtrln 2 48 11 LIW Register LIW Memory 32 x 48 MacroSequencern Datapath Controller 48 42 LIW Control Bits I1p 5 1-Port Address I3pR1 4 3-Port Read1 Address I3pR2 4 3-Port Read2 Address 9 PC Sequence Controller 16 2 5 2 Control 5 2 1 7 Counter 1 Counter 0 7 Stack 16 Configuration Bit 5 22 1 4 16 I3pWO 4 52 Register 16 I3pW 4 3-Port Write Address 2 Status Signals figure 23 The Datapath Controller is a synchronous pipelined structure. A 48-bit instruction is fetched from instruction memory at the address generated by the program counter and registered into the LIW register in one clock cycle. The actions occurring during the next clock cycle are determined by the contents of the LIW register from the previous clock cycle. Meanwhile, the next instruction is being read from memory and the contents of the LIW register is changed for the next clock cycle so that instructions are executed every clock cycle. Because of the synchronous pipelined structure, the Datapath Controller will always execute the next instruction before branch operations are executed. The program counter may be initiated by control signals. It increments or branches to the address of the LIW to be executed next. Infinite Technology Corporation Phone: 972-437-7800 March 1997 39 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath The Adder status signals, Stack and two Counter elements in the Datapath Controller support the program counter. Their support roles are: * The Adder status bits report the value of the Equal, Overflow, and Sign, for use in branch operations. * The Stack contains return addresses. * Counter0 and Counter1 hold down loop-counter values for branch operations. The five index registers hold write, read, and write offset addresses for the 1port and 3-port memories. The write offset register (I3PWO) is used for alignment of the two read index registers, and it holds the value of an offset distance from the 3-port memory write index for the two read indices. Each of the Datapath Controller Block Diagram elements is described in detail. Control Signals The MSn Direct Control and Status pins shown in the Simplified RAD5A4 Control and Data Flow diagram (figure 8) are the control and status interface signals which connect directly between the pins and each MacroSequencer. The direct control signals are MSnCTRL[1:0], and MSnOE, and the direct status signals are MSnAWAIT and MSnSEND. These are listed in the table of MacroSequencer Control Interface Signals (table 6). Alternatively, the MacroSequencers may use control signals from the Dual PLA. The Dual PLA also receives the MacroSequencer status signals. Two Control signals for each MacroSequencer specify one of four control commands. They are selected from either the MSnCTRL[1:0] pins or from the two PLACtrln signals. The control state of the MacroSequencer on the next clock cycle is determined by the state of the above components and the state of these PLACtrln[1:0] signals. The four control states include: SetSequence0 SetSequence0 sets and holds the Program Counter to `0' and resets the Send and Await state registers to `0' without initializing any other registers in the MacroSequencer. Two clock cycles after the SetSequence0 is received, the Datapath Controller will execute LIW 0 every clock cycle. The Program Counter does not change until a Run or Continue command is received. 40 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description SetSequence2 SetSequence2 sets and holds the Program Counter to `2' and resets the Send and Await state registers to `0' without initializing any other registers in the MacroSequencer. Two clock cycles after the SetSequence2 is received, the Datapath Controller will execute LIW 2 every clock cycle. The Program Counter does not change until a Run or Continue command is received. Run Run permits normal operation of the Datapath Controller. The Run command should be asserted every cycle during normal operation except when resetting the Send and/or Await flags, or initiating an LIW sequence with SetSequence0 or SetSequence2. Continue Continue resets both the Send and Await status signals and permits normal operation. If the Await State was asserted, the Program Counter will resume normal operation on the next cycle. If an await operation is encountered while the Continue command is in effect, the Continue command will apply, and the await operation will not halt the Program Counter, nor will the Await status register be set to a `1'. Therefore, the Continue command should be changed to a Run command after two clock cycles. If a send operation is encountered while the Continue command is in effect, the Continue command will apply, and the Send status register will not be set to a `1'. About the Commands The following table summarizes the four command options for Controln[1:0] which may be from PLACtrln or from MSnCTRL pins: Controln [1:0] Command 0 0 0 1 1 0 Run Continue SetSequence0 1 1 SetSequence2 Description Normal Operating Condition Reset Send and Await registers. The Program Counter is set to `0'. Resets the Send and Await registers. This must be asserted for at least two cycles. The Program Counter is set to `2'. Resets the Send and Await registers. This must be asserted for at least two cycles. table 20 By allowing two sequence starting points, each MacroSequencer can be programmed to perform two algorithms without reloading. The two PLACtrln signals are synchronized within the MacroSequencer. The two MSnCTRL pin signals are not synchronized within the MacroSequencer; therefore, consideration for timing requirements is necessary. Infinite Technology Corporation Phone: 972-437-7800 March 1997 41 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Status Signals There are two single-bit registered status signals that notify the external pins and the PLA when the MacroSequencer has reached a predetermined point in its sequence of operations. They are the Await and Send status signals. Both of the Status signals and their registers are reset to `0' in any of these conditions: * During Power On Reset, * Active configuration of any part of the RAD5A4, * During Control States: SetSequence0, SetSequence2, or Continue. Related Assembly Operations: Syntax await send Allowed values for arguments no arguments no arguments table 21 When an await operation is asserted from the LIW register, the MacroSequencer executes the next instruction, and repeats execution of that next instruction until a Continue or SetSequence command is received. The await instruction stops the Program Counter from continuing to change and sets the Await status signal and register to `1'. A Continue command resets the Await status signal and register to `0' allowing the Program Counter to resume. A send operation only sets the Send status signal and register to `1'. Execution of the sequence continues. The Program Counter is not stopped. A Continue command will reset the Send status signal and register to `0'. Status signals are resynchronized in the Dual PLA with the PLACLK. Adder Status Signals The Adder status bits, Equal, Overflow, and Sign are provided for conditional jumps. 42 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Program Counter The Program Counter is a 5-bit register which changes state based upon a number of conditions. The program counter may be incremented, loaded directly, or set to `0' or `2'. The three kinds of LIW operations which affect the MacroSequencer Program Counter explicitly are: * Branch operations, * SetSequence0 and SetSequence2 commands, and * Await operation. The Program Counter is set to zero `0': * * * * During power-on Reset, During Active configuration of any part of the RAD5A4, During the SetSequence0 command, When the Program Counter reaches the value `31', and the previous LIW did not contain a branch to another address, or * Upon the execution of a branch operation to address `0'. Control Signal Effects: The Controln[1:0] signals are used to reset the program counter to either `0' or `2' at any time with either SetSequence0 or SetSequence2 respectively. A Run command begins and maintains execution by the program counter according to the LIW. A Continue command resumes the program counter operation after an Await state and resets the Send and Await registers to `0' on the next rising clock edge. A Continue command after a Send operation resets the Send register to `0' on the next rising clock edge. Status Signal Effects: The Await status register is set to `1' and the Program Counter stops on the next clock cycle after an await operation is encountered. A Continue command resets the Send and Await registers and permits the Program Counter to resume. The Send status register is set to `1' on the next clock cycle after a send operation. A Continue command is required to reset the Send register. A Send operation does not effect the Program Counter. Infinite Technology Corporation Phone: 972-437-7800 March 1997 43 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Branch Operations The LIW register may contain one Branch operation at a time. Conditional Branches should not be performed during the SetSequence commands to insure predictable conditions. Branch Operation Assembly Instruction Unconditional branch jump <address> Branch on loop Counter0 jumpcounter0 <address> jumpcounter1 <address> or loop Counter1 not equal to `0' Branch on an Adder status condition: Equal, Overflow, Sign Call subroutine jumpequal <address> jumpoverflow <address> jumpsign <address> call <address> Return from subroutine operation return Result in the Program Counter Program Counter is set to <address>. Program Counter is set to <address> if the respective loop counter has a non-zero value. The respective loop counter will then be decremented in the next clock cycle. Program Counter is set to <address> if the Adder status bits agree with the branch condition. The current address plus `1' in the Program Counter is pushed onto the Stack. The contents of the Program Counter on the next clock cycle will be set to the address in the LIW. The address from the top of the Stack is popped into the Program Counter. table 22 Long Instruction Word Register The purpose of the 48-bit LIW Register is to hold the contents of the current LIW to be executed. Its bits are directly connected to elements in the datapath. The LIW register is loaded with the contents of the instruction memory pointed to by the Program Counter before the Program Counter is updated. The effect of that instruction is calculated during the next clock cycle. Instruction Memory The Instruction memory consists of thirty-two words of 48-bit RAM configured according to the MacroSequencer assembly language program. The Instruction memory is not initialized during Power On Reset. For reliability, the LIW RAM must be configured before MacroSequencer execution begins. Bit fields in the LIW Registers control datapath operations and program flow. They are described in detail in the LIW Appendix. Counter0 and Counter1 There are two 5-bit loop counters labeled Counter0 and Counter1. Both loop counters are filled with `0's during Power On Reset and active configuration of any component in the RAD5A4. 44 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Counter0 and Counter1 may be loaded by the setcounter0 and setcounter1 operations respectively. The jumpcounter0 and jumpcounter1 operations will decrement the respective counter on the next clock cycle until the Counter value reaches `0'. The SetSequence0 and SetSequence2 control signals do not alter or reset the loop counters. Therefore, the counters should be initialized with setcounter0 and setcounter1 operations before they are referenced in the program. Related Assembly Operations: Syntax jumpcounter0 <address> jumpcounter1 <address> setcounter0 <value> setcounter1 <value> Allowed values for arguments <address>: 0-31 or 0x0-0x1f or label <address>: 0-31 or 0x0-0x1f or label <value>: 0-31 or 0x0-0x1f <value>: 0-31 or 0x0-0x1f table 23 Stack The Stack holds return addresses. It contains four 5-bit registers and a 2-bit stack pointer. After Power On Reset or the active configuration of any component in the RAD5A4, the stack pointer and all of the 5-bit registers are initialized to `0's. A call performs an unconditional jump after executing the next instruction, and pushes the return address of the second instruction following the call into the Stack. A return operation pops the return address from the Stack and into the Program Counter. The call and return operations will repeat and corrupt the Stack if these operations are in the next LIW after an await operation because the program counter is held on that address, and the MacroSequencer repeats execution of the LIW in that address. Infinite Technology Corporation Phone: 972-437-7800 March 1997 45 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Related Assembly Operations: Syntax call <address> return Allowed values for arguments <address>: 0-31 or 0x0-0x1f or label no arguments table 24 Index Registers The LIW Register controls the five index registers which are used for data memory address generation. One index register holds the 1-port memory address. The other four index registers hold 3-port memory address information. During Power On Reset or the active configuration of any component in the RAD5A4, all index register bits are reset to `0's. The control states, Run, Continue, SetSequence0 or SetSequence2 do not affect the index registers. During each clock cycle that a memory access is performed, that memory address can be loaded, incremented, decremented or held depending upon the control bit settings in each index register. Related Assembly Operations: Syntax Allowed values for arguments setindex <value> <value>: 0-31 or 0x0-0x1f setindex <valuew>, <value1>, <value2> <valuew>: 0-15 or 0x0-0xf <value1>: 0-15 or 0x0-0xf <value2>: 0-15 or 0x0-0xf indexmode <m0>, <mw>, <m1>, <m2> <m0>: none, reset <mw>: none, resetoffset, resetall <m1>: none, reset, align <m2>: none reset, align indexdirect <d0>, <dw>, <d1>, <d2> <d0>: none, inc, dec <index> <dw>: none, inc, dec, rev <d1>: none, inc, dec, rev <d2>: none, inc, dec, rev <index>: readwrite0, write, read1, read2, all3port table 25 46 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Index Register Components Each index register contains an address register and a control register that provide: * Index Control bits which include: * Two index direction bits * A load enable bit * Index memory address bits where: * The 1-port Index address is five bits. * The 3-port Read1 Index address is four bits. * The 3-port Read2 Index address is four bits. * The 3-port Write Offset address is four bits. * The 3-port Write Index address is four bits. The 3-port read index control registers also contain a load-write-offset (ldwo) bit, which enables loading from the write offset register. The index direction can be set by the assembly language to: * increment (count_up=1 and count_down=0), * decrement (count_up=0 and count_down=1), or * hold its value (count_up=0 and count_down=0). The effects of the control bits on the address bits are set by the software and are listed in this table: Index Control Bits Count_ Count_ up down Load Enable (lden) Load Write Offset (ldwo) Effect 1-port Index X X 1 n/a 0 0 1 0 1 0 0 0 0 n/a n/a n/a allows a value to be loaded into address[4:0] value of address[4:0] is held post-decrements address[4:0] post-increments address[4:0] 3-port Read1 and Read2 Index, 3-port Write Offset, and 3-port Write Index X X 1 0 0 0 1 X 0 1 0 X 0 0 0 X 0 0 0 1 allows a value to be loaded into address[3:0] value of address[3:0] is held post-decrements address[3:0] post-increments address[3:0] Address is set to the value of the Write Index address less the Write Offset address table 26 Infinite Technology Corporation Phone: 972-437-7800 March 1997 47 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath The Index Register bits are shown in this table: Index Register Control Register Bits Description Name count_ up 1-port Index 3-port Read1 Index 3-port Read2 Index 3-port Write Offset 3-port Write Index I1p I3pR1 I3pR2 I3pWO I3pW count_ down table 27 Load Enable (lden) Load Write Offset (ldwo) Address Register Bits adr[4:0] adr[3:0] adr[3:0] adr[3:0] adr[3:0] MacroSequencer Configuration Bits In each MacroSequencer there are nine programmable configuration bits. They are listed in the table below. The three signed/unsigned bits are set with directives when programming the MacroSequencer. The other selections are made in the RADware design tools. MacroSequencer Configuration Bits Bit Functional Block Function If Bit = 0 If Bit = 1 0 Multiplier 1 Multiplier 2 Adder 3 Adder 32/16 Bit 16 bit Datapath mode 32 bit Datapath mode 4 Data Bus Connections Select OutRegA or MSnI/O pins for MacroSequencer busn inputs Busn inputs are from OutRegA of MacroSequencer(n) Busn inputs are from MSnI/O pins 5 Datapath Controller Control[1:0] source select Control[1:0] from MSnCTRL[1:0] pins Control[1:0] from PLA0 CtrlPLAn[1:0] 7:6 I/O Interface Output Enable Select or `1' [00]: OE is from MSnOE pin [01]: OE is from PLA [1x]: OE is `1' 8 I/O Interface OE Polarity Select OE = OE Mult operand A sign A is unsigned. A is signed. Mult operand B sign B is unsigned. B is signed. Signed / Unsigned Bit Unsigned Add Signed Add OE = OE `1' - logical one, `0' - logical zero table 28 The configuration bits are configured with the instruction memory, where bits 0 through 8 of the 16-bit program data word are the nine configuration bits listed above. They are placed automatically by the RADware design tools. 48 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description RAD5A4 Dual PLA Description The RAD5A4 Dual PLA contains two in-circuit programmable, 32 input by 34 product term PLAs. PLA0 may serve as a state machine to coordinate the MacroSequencer array operation with external devices. PLA1 may be used for random interface logic. The Dual PLA may perform peripheral logic or control functions based upon the state of BUS4IN, PLAIN and PLAI/O bus states and the Control bus. Dual PLA Block Diagram PLA0 oepla[1] oepla[3] (Inputs) B 16 16 64 mt 32 PT0 FO0 8 C0 Control Registers 8 A Control OR 8 Fixed OR 0 4 AND Array 0 34 x 32 4 Minterm Generater 16 Input Selector BUS4IN[15:0] Send Status Await Status PLAIN[7:0] PLAI/O[7:0] 8 PLACtrl0[1:0] PLACtrl1[1:0] 8 PLACtrl2[1:0] PLACtrl3[1:0] CtrlReg 8 C1 PLAI/O Buffers 14 FO1 Output OR PT1 Fixed OR 1 mt 32 Output Registers 16 64 OutCom B 16 8 AND Array 1 34 x 32 A Minterm Generater Input Selector OutReg 8 PLAI/O[7:0] (Outputs) oepla[0] oepla[2] PLA1 Register figure 24 The Dual PLA control functions which may be used by any or all of the MacroSequencers include: * Registered control outputs, CtrlReg[7:0], for: - Initiation of LIW sequences and - Control response to Send and Await status signals. * Combinatorial outputs, oepla[3:0], used to generate Output Enable signals for the MacroSequencers. The oepla[3:0] signals are generated from individual product terms. Infinite Technology Corporation Phone: 972-437-7800 March 1997 49 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath The CtrlReg[7:0] signals may be used in pairs by each of the MacroSequencers where: * * * * CtrlReg[1:0] are available as Control0[1:0] for MacroSequencer0. CtrlReg[3:2] are available as Control1[1:0] for MacroSequencer1. CtrlReg[5:4] are available as Control2[1:0] for MacroSequencer2. CtrlReg[7:6] are available as Control3[1:0] for MacroSequencer3. The RAD5A4 Dual PLA and MacroSequencers should be programmed at power up and may be dynamically reconfigured at any time during operation. Active Configuration of the RAD5A4 forces all registers in every component of the RAD5A4, including the Dual PLA output and control registers to be initialized. Outputs The PLA0 produces eight CtrlReg outputs that can be used as MacroSequencer control signals where two signals are available for each MacroSequencer to use as Control signals. They are also available as feedbacks to both PLA0 and PLA1. The CtrlReg[7:0] signals are useful in multi-chip array processor applications where system control signals are transmitted to each RAD5A4. PLA1 produces combinatorial or registered I/O outputs for the PLAI/O[7:0] pins. The fourteen Fixed OR outputs(FO1) from PLA1 are also available to the Control OR array in the PLA0. The PLA1 registers are available for feedback to both PLA Input Selectors. The PLAI/O signals are useful for single chip applications requiring a few interface/handshake signals, and they are useful in multi-chip array processor applications where system control signals are transmitted to each device. Components PLA0 consists of : * * * * * * 50 Input Selector Minterm Generator to the AND Array0 34 product terms by 32 inputs AND Array0 Fixed OR array (Fixed OR0) 8 x 16 Programmable OR array (Control OR) 8 registers (Control Register) March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description PLA1 consists of: * * * * * * * Input Selectors Minterm Generator to the AND Array1 34 product terms by 32 inputs AND Array1 14 Fixed OR nodes with 1 to 4 product terms per node (Fixed OR1) 8 x 14 Programmable OR array (Output OR) 8 registers (Output Registers) Choice of 8 registers or combinatorial outputs (PLAI/O Buffers) Each element in the RAD5A4 Dual PLA is described in detail. PLA Input Selectors The Input Selectors for PLA0 and PLA1 are identical and accept inputs from: * The Send and Await status signals from each MacroSequencer which are synchronized nd registered in the Input Selector circuits. * BUS4IN[15:0] input pins, * PLAI/O[7:0] pins, * PLAIN[7:0] pins, * CtrlReg[7:0] registered signals from the PLA0, and * OutReg[7:0] registered signals from the PLA1. Infinite Technology Corporation Phone: 972-437-7800 March 1997 51 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath There are two groups of generated signals A[15:0] and B[15:0] which are output by the PLA Input Selector circuit. PLA Input Selector CtrlReg[6,4,2,0] OutReg[6,4,2,0] 4 A[3:0] CtrlReg[7,5,3,1] OutReg[7,5,3,1] 4 B[3:0] 4 A[7:4] 4 B[7:4] BUS4IN[6,4,2,0] 4 A[11:8] BUS4IN[7,5,3,1] 4 B[11:8] PLAIN[6,4,2,0] 4 A[15:12] PLAIN[7,5,3,1] 4 B[15:12] PLA Configuration Bit (CtrlReg or OutReg) PLAI/O[6,4,2,0] Await[3:0] PLACLK PLAI/O[7,5,3,1] Send[3:0] PLA Configuration Bit (PLAI/O or Await / Send) Register figure 25 PLA Configuration bits are set within the RADware design tools when the Dual PLA is programmed. 52 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Minterm Generator The Minterm generator provides the 16 sets of four minterms of the two adjacent numbered inputs (A[i] and B[i]) from the Input Selectors to the AND planes. There are two 16-bit parallel inputs to the Minterm Generator known as A[15:0] and B[15:0]. Adjacent inputs, A[i] and B[i], are paired to generate the four possible minterms for use in the AND array. Instead of routing the conventional inverted and non-inverted input signals to the AND array, the four minterms of the two inputs are routed. The number of lines through the array and the number of memory signals in the AND array are four per two inputs for each product term which is the same as a conventional AND array. From each input pair, A[i] and B[i], minterms are generated as inputs to the AND array. A[i] & B[i] A[i] & B[i] A[i] & B[i] A[i] & B[i] Each pair of inputs to the Minterm generator, A[i] and B[i], generate the following minterm signals for i=0, ..., 15: * * * * mt[4*i] = A[i] & B[i] mt[4*i+1] = A[i] & B[i] mt[4*i+2] = A[i] & B[i] mt[4*i+3] = A[i] & B[i] The minterm results, mt[63:0] are available to the AND planes. AND Arrays Each PLA generates 34 product terms of 32 inputs arranged as 16 pairs (A[i], B[i]) of signals. AND array inputs are from the Minterm Generator. The Minterm Generator translates 16 pairs of A[i] and B[i] signals into 16 groups of four minterms labeled mt[4i+3:4i]. These 64 minterm signals are then transmitted to each of the 34 product terms within the AND array. Infinite Technology Corporation Phone: 972-437-7800 March 1997 53 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Each product term consists of 16 function generators which use four of the minterm signals to generate any function of the two A[i] and B[i] signals. The function generator outputs, f(0) to f(15) are the inputs to a 16-input AND gate. Each 16-input AND gate outputs one of the product term signals. Product Terms mt[3:0] mt[7:4] Function Generator f(0) mt[63:60] Function Generator ... f(1) Function Generator f(15) 16 16-input AND Gate PT figure 26 AND Array Function Generator Configuration of four PLA configuration bits, s0, s1, s2, and s3, within each function generator determines the functions of each A[i], B[i] input pair for the product terms. The relation between the PLA configuration bits, input pairs and AND-gate inputs are shown in this diagram: Function Generator AB AB AB AB s0 s1 AND Array Inputs s2 s3 figure 27 54 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Memory selections for the sixteen possible input functions are shown in this truth table: AB AB AB AB si0 si1 si2 si3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Resulting Function 0 0, the constant function 1 Ai & Bi 0 Ai & !Bi 1 Ai 0 !Ai & Bi 1 Bi 0 Ai xor Bi 1 Ai or Bi 0 !Ai & !Bi 1 Ai xnor Bi 0 !Bi 1 Ai or !Bi 0 !Ai 1 !Ai or Bi 0 !Ai or !Bi 1 1, the constant function table 29 Bolded functions are not normally available in PLA structures. The function generators allow these extra six functions. The logic formula for product term PT[i] is: PT[i] = f[i,0] & f[i,1] & f[i,2] & f[i,3] & f[i,4] & f[i,5] & f[i,6] & f[i,7] & f[i,8] & f[i,9] f[i,10] & f[i,11] & f[i,12] & f[i,13] & f[i,14] & f[i,15] where f[i,j] represents the generated function signal for the PT[i] and input pair A[j], B[j]. Example The RAD5A4 minterm generator and enhanced product term allow a single product to cover the same Boolean function that several conventional product terms would require. Consider the comparison: A[7:0] = B[7:0] between the two 8-bit vectors A and B. This one equation requires 256 conventional product terms; but with the RAD5A4 it will fit in exactly one. This is accomplished by implementing !(A0 XOR B0) . . . !(A7 XOR B7) directly. Infinite Technology Corporation Phone: 972-437-7800 March 1997 55 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Fixed OR Arrays Fixed OR 0 The AND Array 0 outputs are summed in sets of four successive signals to form eight 4-product term signals FO0[7:0] as shown here: Fixed OR 0 PT0 32 Fixed OR 0 8 FO0 8x4 figure 28 where one of the eight Fixed OR 1 outputs is shown here: Fixed OR 0 a b c d Fixed OR Outputs figure 29 56 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Fixed OR 1 The AND Array 1 outputs are summed in sets of one, two and four successive signals to form fourteen, fixed OR term signals FO1[13:0]. The AND Array 1 outputs are summed as follows: * 4 sets of four AND array * 6 sets of two AND array outputs * 4 sets of single AND array outputs Fixed OR 1 Fixed OR 1 PT1 32 14 FO1 4x4 6x2 4x1 figure 30 The detailed product terms are shown in this diagram. Fixed OR 1 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 PT10 PT11 PT12 AND Array PT13 PT Outputs PT14 15 PT16 PT17 FO1 0 FO1 1 FO1 2 FO1 3 Fixed OR Outputs FO1 4 PT18 PT19 FO1 5 PT20 PT21 FO1 6 PT22 PT23 FO1 7 PT24 PT25 FO1 8 PT26 PT27 PT28 PT29 PT30 PT31 FO1 9 FO1 10 FO1 11 FO1 12 FO1 13 figure 31 Infinite Technology Corporation Phone: 972-437-7800 March 1997 57 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Control OR Array The Control OR array is a programmable OR array with 22 inputs that produce eight registered in the Control Register to form the MacroSequencer Control signals which are available as inputs to the PLA Input Selector. The inputs for the Control OR array include FO0[7:0] and FO1[13:0]. Control OR AND ARRAY 0 FO0[7] [6] [5] [4] [3] [2] [1] [0] AND ARRAY 1 FO1[13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] C0[0] [1] [2] [3] [4] [5] [6] [7] figure 32 The vertical lines in the above diagram represent a programmable OR gate, and the horizontal lines represent fixed OR gates. The boxes at the intersections show which of the fixed OR terms may be ORed together. 58 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Each OR gate input is determined by PLA configuration bits as shown in this schematic: Control OR Simplified Schematic FO 0 FO 1 ... FO 15 s0,j ... ... s1,j C0[i] 16-input OR Gate s16,j figure 33 The formula for each Control OR output, C0[i] is: C0[i] = Infinite Technology Corporation Phone: 972-437-7800 FO1[0] AND s[0,i] OR FO1[1] AND s[1,i] OR FO1[2] AND s[2,i] OR FO1[3] AND s[3,i] OR FO1[4] AND s[4,i] OR FO1[5] AND s[5,i] OR FO1[6] AND s[6,i] OR FO1[7] AND s[7,i] OR FO1[8] AND s[8,i] OR FO1[9] AND s[9,i] OR FO1[10] AND s[10,i] OR FO1[11] AND s[11,i] OR FO1[12] AND s[12,i] OR FO1[13] AND s[13,i] OR FO0[j+2] AND s[14,j+2] OR FO0[j] AND s[15,j] OR March 1997 59 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath CtrlReg Register The CtrlReg Registers hold the MacroSequencer Control signals produced by the Control OR array. C0 Register 8 CtrlReg CtrlReg Register 8 CtrlReg PLACLK figure 34 60 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Output OR Array The Output OR array is a programmable OR array with fourteen inputs from the Fixed OR 1 array producing eight combinatorial OutCom[7:0] signals which may be registered. The Output Registers are available as inputs to the PLA Input Selector. Both the combinatorial outputs and the registered Outputs are available to the PLAI/O Buffers. The inputs for the Output OR array are the Fixed OR 1 signals which are labeled FO1. All PLA1 fixed OR terms are available to every programmable OR term. Output OR FO1[13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] C1[0] [1] [2] [3] [4] [5] [6] [7] figure 35 The vertical lines in the above diagram represent a programmable OR gate, and the horizontal lines represent fixed OR gates. The boxes at the intersections show which of the fixed OR terms may be ORed together. Infinite Technology Corporation Phone: 972-437-7800 March 1997 61 RAD5A4 Architecture Description Reconfigurable Arithmetic Datapath Each OR gate input is determined by PLA configuration bits as shown in this schematic: Output OR Simplified Schematic FO1 0 FO1 1 ... FO1 13 s0,j C1[i] ... ... s1,j 14-input OR Gate s16,j figure 36 The formula for each Output OR output, C1[i] is: C1[i] = 62 FO1[0] AND s[0,i] OR FO1[1] AND s[1,i] OR FO1[2] AND s[2,i] OR FO1[3] AND s[3,i] OR FO1[4] AND s[4,i] OR FO1[5] AND s[5,i] OR FO1[6] AND s[6,i] OR FO1[7] AND s[7,i] OR FO1[8] AND s[8,i] OR FO1[9] AND s[9,i] OR FO1[10] AND s[10,i] OR FO1[11] AND s[11,i] OR FO1[12] AND s[12,i] OR FO1[13] AND s[13,i] OR March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Architecture Description Output Register The eight Output Registers are used for holding the signals produced by the Output OR array. The registered signals, OutReg[7:0], are available to the Input Selectors for both PLA0 and PLA1. OutReg OutReg Register 8 C1 8 OutReg PLACLK Register figure 37 PLAI/O Buffers The eight I/O buffers select either the combinatorial outputs or the registered outputs from the Output OR array for the PLAI/O pins. The simple schematic for one buffer is shown here: PLAI/O Buffers Registered C1 OutReg 8 Combinatorial C1 OutCom 8 8 PLAI/O Output PLA Config. Bits figure 38 Exactly one configuration bit controls whether combinatorial or registered outputs are selected for all of the eight PLAI/O pins. One configuration bit for each pin determines whether each PLAI/O pin is always an output or always an input. Infinite Technology Corporation Phone: 972-437-7800 March 1997 63 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath RAD5A4 Configuration This chapter offers directions for RAD5A4 device configuration of the thirteen memories in the RAD5A4 that can be programmed. The RAD5A4 is configured by loading the configuration file into the device. RAD5A4 Configurable Memories There are three memories in each of the four MacroSequencers and a Dual PLA configuration memory. Within each of the MacroSequencers, there is a: * MacroSequencer configuration memory, * 1-port data memory, and * 3-port data memory. The MacroSequencer LIW memory and the nine programmable configuration bits are supplied together in the MacroSequencer configuration memory data packet. The MacroSequencer configuration memory and Dual PLA configuration memory may only be written during Active Configuration Mode. The 1-port and 3-port data memories for each MacroSequencer may be loaded during Active Configuration and accessed during Normal Operating Mode as directed by each MacroSequencer's LIW Register. RAD5A4 Operating Modes The configuration file is loaded into the RAD5A4 during Active Configuration Mode. The RAD5A4 may be in one of three operating modes depending on the logic states of PGM0 and PGM1: * Normal Operation Mode, the RAD5A4 MacroSequencers concurrently execute the LIWs, and the Dual PLA is operational. * Active Configuration Mode allows each MacroSequencer's configuration memory and data memories and the Dual PLA configuration memory to be configured. * Passive Configuration Mode disables the device I/O outputs. This allows other RAD5A4s sharing the same I/O bus circuitry to be configured individually. Four configuration pins, named PGM0, PGM1, PRDY, and PACK, are used to control the operating mode and configuration process. PGM0 and PGM1 control the device operating mode. PRDY and PACK provide a positive handshake interface between the internal RAD5A4 circuitry and the external circuitry configuring the device. BUS4IN[15:0] pins are used to input the configuration data words. 64 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration This chapter includes the following: * * * * * * * Configuration control pin descriptions Description of Configuration Modes Configuration with positive handshaking signals Minimizing Configuration Time Configuration without handshaking Time to Configure the RAD5A4 Multiple RAD5A4 Configuration Throughout this chapter the term LOW is used for a logic level `0'. The term HIGH is used to indicate a logic level `1'. And an X indicates a `don't care' which should be set to either a logical `0' or `1'. The l symbol indicates the rising edge of the signal, and the h symbol indicates the falling edge of the signal. Configuration Control Pin Description Symbol: No. of Pins Pin Number Type Function: PGM0 1 174 Input Configuration Mode0 PGM1 1 173 Input Configuration Mode1 table 30 PRDY 1 3 Input Configuration Ready PACK 1 4 Output Configuration Acknowledge PGM0 and PGM1: Configuration Mode Pins The PGM0 and PGM1 pins are used as inputs to determine the operating mode of the RAD5A4. They are functionally identical. * When both pins are HIGH, the RAD5A4 is in Active Configuration Mode. In this mode, all I/O outputs are in a high-impedance state, and most internal registers and flip-flops in the MacroSequencers and Dual PLA are held in an initialized state. PACK is enabled for output to indicate when the device may be configured. * When they are both LOW, the device is in Normal Operating Mode, and all I/O pins are under the control of the MacroSequencers and Dual PLA, and PACK is in a high-impedance state. No configuration of the device may occur. * When one is LOW and one is HIGH (either one), the device is in a Passive Configuration Mode, and all I/O outputs and the PACK output are in a highimpedance state. No configuration of the device may occur. Infinite Technology Corporation Phone: 972-437-7800 March 1997 65 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath PRDY: Configuration Ready During Active Configuration Mode, external circuitry uses the PRDY (l) input to communicate to the device to load the configuration data word present on BUS4IN[15:0] into the device. PRDY (h) is used to query if the RAD5A4 is ready for the next configuration data word. PACK: Configuration Acknowledge During Active Configuration Mode, PACK (l) is used by the RAD5A4 to indicate when the configuration data word has been accepted and PACK (h) is used to indicate when a new data word will be accepted. PLACLK: Configuration Clock Signal During Active Configuration Mode, PLACLK should be connected to a freerunning clock signal as defined in the Electrical Specifications. The RAD5A4 configuration circuitry is rising edge (l) triggered by this clock pulse. RAD5A4 Configuration Modes Normal Operating Mode: PGM0 = PGM1 = LOW Normal Operating Mode occurs when PGM0 and PGM1 are set LOW and maintained LOW. This prevents configuration from occurring, and device I/O pins will remain active under the control of the MacroSequencers and Dual PLA. PACK will remain in a high-impedance state. PGM0 and PGM1 are asynchronous inputs and must be maintained in their logic states to prevent undesired device operation. PRDY should be set to a known state to minimize power dissipation. Passive Configuration Mode: PGM0 or PGM1 = HIGH, the other LOW Passive Configuration Mode occurs when one of PGM0 or PGM1 is HIGH and the other is LOW. When at least one of PGM0 or PGM1 is HIGH, all I/O outputs are in a high-impedence state. Configuration will not occur in Passive Configuration Mode or Normal Operating Mode. Passive Configuration Mode allows RAD5A4 devices on a common bus to be configured one at a time without affecting I/Os to other RAD5A4 devices in the system. 66 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Active Configuration Mode: PGM0 = PGM1 = HIGH. Only during Active Configuration Mode can the configuration file be loaded into the RAD5A4 device. For Active Configuration, PLACLK, PGM0, PGM1, PRDY, PACK, and BUS4IN[15:0] are used as follows: * * * * PLACLK should be connected to a free running clock signal. PGM0 and PGM1 must be held HIGH for active RAD5A4 Configuration. BUS4IN[15:0] is used for configuration data word input. PRDY input and PACK output work together to provide positive handshaking signals. When both PGM0 and PGM1 are HIGH, MacroSequencer and Dual PLA registers and flip-flops are held in an initialized state. Once PGM0 and PGM1 are HIGH, and the device is in Active Configuration Mode, they must remain HIGH until a Configuration Halt state. If one of them goes LOW, the device will transition out of Active Configuration Mode resulting in the configuration circuitry internal registers, counters, and flipflops resetting to an initialized state. Configuring a RAD5A4 Device The RAD5A4 is configured by loading the configuration file which may be generated by the RADware design tools. The configuration file is divided into 16-bit configuration data words labeled `DWn' where n represents the data word being loaded. The preamble is represented by DWP. DW0 represents the first configuration data word, and DWmax represents the last configuration data word. Each memory type requires a different number of configuration data words. For example, 99 data words are required to load the MacroSequencer configuration memory. The LIW instruction memory requires 96 (32 x 3) configuration data words (DW0 - DW95). The MacroSequencer configuration bits are loaded using an additional data word (DW96). Two more data words (DW97 - DW98) contain reserved bits that complete the MacroSequencer configuration memory data packet. Infinite Technology Corporation Phone: 972-437-7800 March 1997 67 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath When loading configuration data words into a memory, it is necessary to load all data words to fill that memory. Configurable Number of Data Words to Load into Memory DWmax RAD5A4 Memories MacroSequencer configuration memory 99 DW98 MacroSequencer 1-port memory 32 DW31 MacroSequencer 3-port memory 16 DW15 300 DW299 Dual PLA configuration memory table 31 About the Configuration File All information needed to configure the RAD5A4 is prepared in a configuration file by the ITC software tools. Some information about the configuration file has also been included for reference purposes: * The configuration file consists of configuration data packets for each RAD5A4 memory to be programmed. * Each configuration data packet consists of one 16-bit preamble data word that indicates which memory is to be programmed followed by the data to be loaded into the memory. * The configuration file is loaded onto the RAD5A4 using 16-bit configuration data words (DWn). Configuration with Positive Handshaking Signals The RAD5A4 has been designed for configuration to occur with positive handshaking signals by using the PRDY input and PACK output. This pattern between PRDY and PACK is repeated from Configuration Initialization to Configuration Halt: * PRDY (h) is an input to query if RAD5A4 will accept new data. * PACK (h) is an output to advise that the device is ready to receive new data. * PRDY (l) is an input to indicate when new data is present on pins BUS4IN[15:0] and ready to be loaded. * PACK (l) is an output used to advise when data is accepted by the device. PRDY should not be changed until PACK has changed to the same state as PRDY. The RAD5A4 supports synchronous or asynchronous protocols. Changes of state for PRDY, PGM0 and PGM1 will be detected by the RAD5A4. When configuration is complete, PACK will remain HIGH indefinitely indicating that the device will not accept more configuration data. The device may be taken out of Active Configuration Mode by taking PGM0 and/or PGM1 LOW. 68 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Configuration Timing When loading configuration data words, PACK output will go LOW on the second PLACLK (l) after PRDY goes LOW, and PACK will go HIGH on the second PLACLK (l) pulse after PRDY goes HIGH. The shortest time to load a configuration data word is four PLACLK cycles unless one of these four conditions occur that require additional PLACLK cycles: * * * * Configuration Initialization. Additional PLACLK pulses are required. Configuration Continue. Additional PLACLK pulses are required. Configuration Halt. PACK will not go LOW. Invalid preamble. PACK will not go LOW. The following diagrams depict the relationship between PRDY and PACK in Active Configuration Mode. The PGM0 and PGM1 pins are referenced as PGM_a and PGM_b because either pin may be changed first, or they may be changed at the same time. All PLACLK pulse timing is with respect to the rising edge of the clock pulse (l). Active Configuration begins when PGM0 and PGM1 are set HIGH (tB). Infinite Technology Corporation Phone: 972-437-7800 March 1997 69 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath The timing diagrams that follow depict typical configuration cycle timing separated into four areas of operation: * * * * Initial portion, Mid-Cycle portion, Continue portion, and Halt portion. Configuration Cycle Timing for RAD5A4 - Initial Portion BUS4IN[15:0] Inputs DWP tE PLACLK Input tO VIH VIL VIH VIL tH tK tM tP VIH VIL tG tD tI tL tN VOH Hi-Z VOL tB PGM_b Input PGM_a Input DW2 DW 1 tJ tF tC PRDY Input PACK Output DW0 VIH VIL tA VIH VIL I/O Outputs VOH Hi-Z VOL figure 39 Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion BUS4IN[15:0] Inputs DWn DWn+1 tJ PLACLK Input tO VIH VIL tM tK tP PRDY Input PACK Output VIH VIL VIH VIL tI tL tN VOH VOL figure 40 70 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Configuration Cycle Timing for RAD5A4 - Continue Portion BUS4IN[15:0] Inputs DWmax-1 DWmax VIH DWP VIL tE tT PLACLK Input VIH VIL tW tU tF tH VIH PRDY Input VIL tV tS PACK Output tG tX tI VOH VOL figure 41 Configuration Cycle Timing for RAD5A4 - Halt Portion BUS4IN[15:0] Inputs DWmax-1 VIH DWmax VIL tT PLACLK Input VIH VIL tW tU VIH PRDY Input VIL tV tS PACK Output tX Hi-Z VOH VOL tY PGM_b Input VIH VIL tZ PGM_a Input VIH VIL I/O Outputs Hi-Z VOH VOL figure 42 Between time tB in the Initial portion and time tY in the Halt portion, the states of PGM_a, PGM_b, and the I/O outputs remain constant, and are not shown in the Mid-Cycle portion and the Continue portion. These four timing figures (figures 38 - 41) illustrate RAD5A4 configuration timing and operation using one example of PRDY response time after PACK transitions. For this example, a positive handshake exists between the PRDY signal from external circuitry and the PACK acknowledge signal from the RAD5A4. PRDY is an asynchronous input signal that is changed between the first and second PLACLK rising edge after PACK transitions. Infinite Technology Corporation Phone: 972-437-7800 March 1997 71 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Configuration Initialization Configuration initialization begins upon entry into the Active Configuration Mode when the second of PGM0 and PGM1 are set HIGH (tB) and ends when PACK goes LOW for the first time (tD). PACK goes from a high-impedence state to HIGH at the beginning of Configuration Initialization (tB) and remains HIGH during Configuration Initialization. Configuration Initialization is represented as the time between tB and tD in the timing diagrams and the configuration summary table, and is represented by time tBD in the Time to Configure the RAD5A4 discussions. During Configuration Initialization, PACK output remains HIGH for a minimum of four PLACLK rising edges after the second of PGM0 and PGM1 are asserted HIGH at time tB. PRDY may be asserted LOW during or before Configuration Initialization. The time when PACK goes LOW is dependent on when PRDY is LOW. * If PRDY is set LOW before the third PLACLK pulse (l) after PACK goes HIGH (l), then PACK will go LOW (h) on the fourth PLACLK (l) after PACK goes HIGH (l). This is the quickest method. * If PRDY is set LOW after the second PLACLK pulse (l) after PACK goes HIGH (l), then PACK will go LOW (h) on the second PLACLK pulse (l) after PRDY is set LOW (h). When PACK goes LOW (tD) at the end of Configuration Initialization, the device will be ready to accept data input on BUS4IN[15:0]. The preamble, DWP, should be present on BUS4IN[15:0] before PRDY is set HIGH at time tF. Configuration Continue Either Configuration Continue or Configuration Halt occurs at the end of each data packet. Bit 7 from each preamble (DWP:b7) specifies whether the accompanying data packet is the last one (b7 = 0), or if another data packet follows (b7 = 1) to continue configuration. When a Configuration Continue occurs, PACK output remains HIGH for a minimum of six PLACLK periods after receiving the last data word, DWmax, at time tV. The time when PACK goes LOW is dependent on when PRDY is LOW. * If PRDY is set LOW before the fifth PLACLK pulse (l) after PACK goes HIGH (l), then PACK will go LOW (h) on the sixth PLACLK (l) after PACK goes HIGH (l). This is the quickest method. * If PRDY is set LOW after the fourth PLACLK pulse (l) after PACK goes HIGH (l), then PACK will go LOW (h) on the second PLACLK pulse (l) after PRDY is set LOW (h). The preamble, DWP, for the next data packet may be placed on BUS4IN[15:0] in preparation for configuration of the next memory after PACK goes HGH to accept DWmax. 72 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration When PACK goes LOW (h) (tX), configuration may continue. If PACK remains HIGH at time tX, then a Configuration Halt is indicated. Configuration Halt Configuration Halt occurs when all data packets in the configuration file have been loaded. In the halted state, PACK remains HIGH after time tX regardless of when PRDY is set LOW until the Active Configuration Mode has been terminated by setting PGM0 and/or PGM1 to LOW. The only time the device should enter a Configuration Halt state is when the configuration file is completely loaded. Timing for Configuration Halt is the same as the timing for Configuration Continue. Configuration Halt is differentiated from the Configuration Continue by the logic state of PACK after time tX. The device should always be in a Configuration Halt before transitioning PGM0 or PGM1 LOW. During Active Configuration termination, when the first of pins PGM0 or PGM1 is set LOW (tY), PACK output will go to a highimpedance state. When the second of pins PGM0 or PGM1 is set LOW(tZ), the I/O outputs will become active under control of the MacroSequencers and Dual PLA. PGM0 and PGM1 are referenced as PGM_a and PGM_b because either pin may be set LOW first, or they may be set LOW at the same time. Infinite Technology Corporation Phone: 972-437-7800 March 1997 73 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Invalid Preamble (DWP) If bits six through zero of the preamble (DWP b6:b0) are an allowed option, the preamble is considered to be valid, and additional data words may be loaded. * If the preamble is valid, PACK will go LOW two PLACLK pulses after PRDY is set LOW (tI) as shown in figure 38. * Otherwise, the preamble is invalid, and PACK will remain HIGH until Active Configuration is terminated as shown by time tI in figure 42. PACK will remain HIGH until Active Configuration Mode is terminated. Configuration Cycle Timing for RAD5A4 with Invalid Preamble VIH BUS4IN[15:0] Inputs DWP PLACLK Input tF tC tH VIH VIL tD tG tI Hi-Z VOH VOL tB PGM_b Input PGM_a Input VIH VIL PRDY Input PACK Output VIL tE VIH VIL tA VIH VIL I/O Outputs Hi-Z VOH VOL figure 43 The RADware software automatically generates the correct preamble for each memory configured by the configuration file; therefore, the device should not enter an invalid preamble state unless it is caused by other factors. 74 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Configuration Summary The following configuration table is a summary of the detailed configuration steps described in this chapter. The number of PLACLK pulses between signal changes is not indicated. The time (t_) refers to times shown on Configuration timing diagrams, figures 38 - 42. Configuration Pins Inputs Step PGM_a PGM_b Time Outputs PRDY BUS4IN PACK I/Os Operation Description t_ X X Hi-Z Active I/O pins are operational under control of the Dual PLA and MacroSequencers. <tA X X Hi-Z Hi-Z Passive Configuration tA Set both PGM0 and PGM1 High to begin Active Configuration. Set PRDY LOW, if it is not already LOW. Configuration Initialization complete tB Place preamble on pins BUS4IN[15:0] if not already loaded. Set PRDY HIGH to tell device that DWP is ready. PACK acknowledges that preamble is received. Take PRDY LOW to query if RAD5A4 will accept new data. When Preamble is valid, PACK will go LOW. Go to step 3a. tE Normal Operation Mode L L Passive Configuration Mode H L Active Configuration Mode - Initialization 1a H H H or L X H Hi-Z 1b H H L X H Hi-Z 1c H H L X h Hi-Z tC tD Load Preamble 2a H H L DWP L Hi-Z 2b H H l DWP L Hi-Z 2c H H H DWP l Hi-Z 2d H H h X H Hi-Z 2e H H L X h Hi-Z tF tG tH tI table 32 Infinite Technology Corporation Phone: 972-437-7800 March 1997 75 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Configuration Pins Inputs Step PGM_a PGM_b Time Outputs PRDY BUS4IN PACK I/Os Operation Description Place next DWn data on BUS4IN[15:0]. Set PRDY HIGH to advise that next data is present. PACK acknowledges DWn data is received. Take PRDY LOW to query if RAD5A4 will accept new data. PACK goes LOW to acknowledge that next data will be accepted. Repeat steps 3a - 3e until DWmax. t_ Load DWn (n = 0,1,2, . . . max-1) 3a H H L DWn L Hi-Z 3b H H l DWn L Hi-Z 3c H H H DWn l Hi-Z 3d H H h X H Hi-Z 3e H H L X h Hi-Z tJ tK tL tM tN Load DWmax 4b H H L DWmax L Hi-Z 4c H H l DWmax L Hi-Z 4d H H H DWmax l Hi-Z 4e H H h X H Hi-Z X h Hi-Z Place DWmax configuration data word on BUS4IN[15:0] Set PRDY HIGH to advise that DWmax is present. PACK acknowledges DWmax data is received. Take PRDY LOW to query if RAD5A4 will accept new data. Go to 4f or 4g. tT tU tV tW Continue Active Configuration 4f H H L If PACK goes LOW, the next tX data will be accepted. Continue configuration of another memory with step 2a. table 32 76 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Configuration Pins Inputs Step PGM_a PGM_b Time Outputs PRDY BUS4IN PACK I/Os Operation Description t_ tY Halt Active Configuration 4g H H L X H Hi-Z 4h H h L X Hi-Z Hi-Z If PACK remains HIGH, configuration is halted. To terminate active Configuration, take PGM0 or PGM1 LOW. tX X X Hi-Z Hi-Z Passive Configuration tY X X Hi-Z Active Normal operation. >tZ Passive Configuration Mode L H Normal Operation Mode L L table 32 Infinite Technology Corporation Phone: 972-437-7800 March 1997 77 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Minimizing Configuration Time The shortest configuration cycle is four PLACLK pulses per data word in the Mid-Cycle portion of Active Configuration. The number of PLACLK pulses required to load each data word is dependent upon how soon PRDY input changes state after PACK output changes state. The timing examples shown earlier in this chapter illustrate changes in PRDY between the rising edges of the first and second PLACLK pulses after PACK output transitions. This results in six PLACLK pulses for each data word in the Mid-Cycle portion of Active Configuration. To achieve the fastest configuration operations with or without handshaking, PRDY must transition before the first PLACLK rising edge after PACK output transitions. PRDY may be taken LOW before the next PLACLK pulse (l) after PACK goes HIGH, and PRDY may be taken HIGH before the next PLACLK pulse ( l ) after PACK goes LOW. A timing diagram showing a minimum of four clock cycles per configuration data word is shown here. This diagram illustrates asynchronous configuration with handshaking. The BUS4IN[15:0] data is valid whenever PRDY is HIGH. Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion BUS4IN[15:0] Inputs PLACLK Input DWn DWn+1 tO tJ VIH VIL VIH VIL tK tM tP PRDY Input PACK Output DWn+2 VIH VIL tI tL tN VOH VOL figure 44 Setup and Hold Timing The setup and hold timing requirements of the PRDY and BUS4IN[15:0] inputs with respect to the PLACLK (l) input signal to correctly load configuration data is shown in figure 44. During Active Configuration Mode, a PRDY transition is received by the RAD5A4 on the first PLACLK (l) after the PRDY transition satisfies the actual setup time. For asynchronous PRDY signals, a PRDY transition that does not meet the actual setup time on the first PLACLK (l) will be received on the next PLACLK (l). Synchronous PRDY inputs must satisfy the 78 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration minimum setup time (tSU) specified in the Electrical Specifications to be received by the RAD5A4 on the desired PLACLK rising edge. The configuration circuitry has been designed so that the data on BUS4IN[15:0] is received by the RAD5A4 one PLACLK (l) after PRDY (l) input is received by the device. This allows BUS4IN[15:0] data to change at the same time with PRDY (l) and provides for a defined maximum allowed skew (tSKEW(max)) between PRDY (l) input and input data on BUS4IN[15:0]. The parameter tSKEW(max) is calculated as follows: tSKEW(max) = PLACLK period + tSU (PRDY) - tSU (BUS4IN[15:0]) where: PLACLK period tSU (PRDY) = the period of the PLACLK signal = minimum setup time for PRDY specified in the Electrical Specifications, Active Configuration tSU (BUS4IN[15:0]) = minimum setup time for BUS4IN[15:0] specified in the Electrical Specifications, Active Configuration When using asynchronous configuration, BUS4IN[15:0] transitions should occur no later than PRDY (l) to assure correct configuration. Asynchronous configuration should use positive handshaking. When using synchronous configuration, PRDY and BUS4IN[15:0] transitions must satisfy the setup and hold time requirements of the Electrical Specifications for the appropriate PLACLK (l) as shown in figure 44. Synchronous configuration may be used with or without handshaking provided proper timing is implemented. Detailed Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion BUS4IN[15:0] Inputs VIH DWn VIL tSU tH VIH PRDY Input tSU tH tSU tH PLACLK Input tCO tCO PACK Output VIL VIH VIL VOH VOL figure 45 Infinite Technology Corporation Phone: 972-437-7800 March 1997 79 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Configuration without Handshaking It is possible to configure the RAD5A4 without using PACK output signals. This requires an understanding of the number of PLACLK signals required to receive and load data into memory. To speed configuration, PRDY input from external circuitry may change state synchronously on the same PLACLK (l) as PACK changes in anticipation of PACK transitioning. The PRDY signal must not change state until after the minimum specified hold time (tH) following PLACLK (l) has been satisfied. This procedure may be used to minimize configuration time when executing at a high PLACLK frequency by eliminating the effects of PACK output delay time, system response time, and PRDY setup time when using the handshaking protocol. The timing diagrams in figures 45 - 48 illustrate an example synchronous system where PRDY and BUS4IN[15:0] inputs are from external registers that are clocked on the appropriate PLACLK (l) edge. The minimum number of PLACLK pulses for synchronous configuration is illustrated in these figures between time tB and time tY . This example uses one PLACLK pulse between the transitions of PGM_a and PGM_b inputs in both the Initial portion (figure 45) and the Halt portion (figure 48) of the configuration cycle. Synchronous Configuration Cycle Timing for RAD5A4 - Initial Portion BUS4IN[15:0] Inputs DW0 DWP tE DW 1 tJ tO PLACLK Input VIL VIL tC tF tH tK tM tP VIH VIL tD tG tI Hi-Z tL tN VOH VOL tB PGM_b Input PGM_a Input VIH VIH PRDY Input PACK Output DW2 VIH VIL tA VIH VIL I/O Outputs Hi-Z VOH VOL figure 46 80 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Synchronous Configuration Cycle Timing for RAD5A4 - Mid-Cycle Portion BUS4IN[15:0] Inputs DWn DWn+1 DWn+2 VIL tJ tO VIH PLACLK Input VIL tK tM tP tI tL tN VIH PRDY Input PACK Output VIH VIL VOH VOL figure 47 Synchronous Configuration Cycle Timing for RAD5A4 - Continue Portion BUS4IN[15:0] Inputs PLACLK Input DWmax VIH DWP VIL tE tT tU tW tF VIH tH PRDY Input PACK Output VIL VIH VIL tS tV tX tG VOH VOL figure 48 Infinite Technology Corporation Phone: 972-437-7800 March 1997 81 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Synchronous Configuration Cycle Timing for RAD5A4 - Halt Portion BUS4IN[15:0] Inputs VIH DWmax VIL tT VIH PLACLK Input VIL tU tW VIH PRDY Input PACK Output VIL tS tV tX Hi-Z tY VOL VIH PGM_b Input VIL tZ PGM_a Input I/O Outputs VOH VIH VIL Hi-Z VOH VOL figure 49 PRDY is initially set HIGH (tC) at the same time PGM_b is set HIGH (tB) to start Active Configuration as shown in figure 45. PGM_b is set LOW (tY) at the same time that tX occurs to end Active Configuration as shown in figure 48. PACK output transition occurs on the second PLACLK (l) after PRDY changes state except for tC to tD in figure 45 and time tW to tX in figures 47 and 48 where additional PLACLK pulses are required. 82 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Time to Configure the RAD5A4 RAD5A4 devices may be completely reconfigured in less than 150s. The exact time required to configure a RAD5A4 device is dependent upon: * Number of PLACLK pulses per configuration memory which is determined by the size of the memory and the PRDY response time after PACK changes, * How many of the memories are programmed, and * PLACLK rate. A discussion of each of these factors follows with tables of example choices. PLACLK Pulses per Memory Configured The number of PLACLK Pulses for each configuration memory is dependent upon the PRDY response time after PACK changes. To minimize configuration time, PRDY can be changed before the rising edge of the first PLACLK pulse following a change in PACK as shown in figure 43. However, some systems may require more time before PRDY is changed. The example used in figures 38 - 42 shows PRDY changing asynchronously between the rising edges of the first and second PLACLK pulses following a change in PACK. This table shows the number of complete PLACLK pulses required to configure each type of RAD5A4 memory using several different PLACLK delays (tDPR). The time required for Configuration Initialization and Configuration Continue and Halt are shown separately because they are independent of the type of memory being configured. PLACLK Pulses for Configuration Type of Memory MacroSequencer Memories During PLACLK pulse after PACK changes first second third fourth fifth sixth seventh eighth PRDY Delay MS Config. Memory 1-port Memory 3-port Memory (TDW=100) (TDW=33) (TDW=17) tDPR tDV tDV tDV 0 1 2 3 4 5 6 7 398 597 796 995 1194 1393 1592 1791 130 195 260 325 390 455 520 585 66 99 132 165 198 231 264 297 table 33 Infinite Technology Corporation Phone: 972-437-7800 March 1997 Dual PLA Config. Memory Config. (TDW=301) Initialization Config. Continue & Halt tDV tBD tVX 1202 1803 2404 3005 3606 4207 4808 5409 5 5 5 5 6 7 8 9 6 6 6 6 6 7 8 9 83 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Reading the PLACLK Pulses for Configuration Table TDW TDW = the total number of data words for each type of memory and includes the preamble data word. During PLACLK pulse and PRDY Delay (tDPR) tDPR = the number of PLACLK rising edges between a change in PACK and the PRDY response. For example, when PRDY changes before the rising edge of the first PLACLK pulse following a change in PACK, the PRDY Delay is 0 (tDPR = 0). If PRDY changes between the rising edges of the first and second PLACLK following a change in PACK, then the PRDY delay is 1 (tDPR = 1). The example illustrated in figures 38 - 41 uses tDPR = 1. The example illustrated in figures 45 - 48 uses tDPR = 0. tDV tDV = number of PLACLK pulses to load a memory not including the extra clock pulses required for a Configuration Continue or Configuration Halt. In the example timing diagrams shown in this chapter, tDV is the time from tD to tV. tDV = (2 + tDPR)*(2 * TDW - 1) tBD - Configuration Initialization Time tBD = number of PLACLK periods for Configuration Initialization including the full PLACLK period in which the second of the two PGM pins are taken HIGH. In the example timing diagrams shown in this chapter, tBD is the time from tB to tD. tBD = (2 + tDPR) if tDPR > 3 tBD = 5 if tDPR < 4 (minimum time) In the timing diagrams shown in this chapter, time tBC = tDPR. tVX - Configuration Continue & Halt Time tVX = number of PLACLK pulses for Configuration Continue and Halt. In the example timing diagrams shown in this chapter, tVX is the time from tV to tX. tVX = (2 + tDPR) if tDPR > 4 tVX = 6 if tDPR < 5 (minimum time) 84 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration PLACLK Pulses for Device Configuration PLACLK Pulses for Configuration Single Memory Configuration Dual PLA MacroSequencer Memories MS Config. During Memory PLACLK pulse PRDY Delay after PACK (TDW=100) changes first second third fourth fifth sixth seventh eighth tBX 409 608 807 1006 1206 1407 1608 1809 tDPR 0 1 2 3 4 5 6 7 1-port Memory (TDW=33) tBX 141 206 271 336 402 469 536 603 3-port Memory (TDW=17) Multiple Memories Config. Memory (TDW=301) One MacroSequencer (3 memories) RAD5A4 (13 memories) tBX 1213 1814 2415 3016 3618 4221 4824 5427 tBX 617 914 1121 1508 1806 2107 2408 2709 tBX 3661 5450 7239 9028 10818 12621 14424 16227 tBX 77 110 143 176 210 245 280 315 table 34 tBX - Time from Configuration Initialization to Halt tBX = number of PLACLK pulses for device configuration. It includes the number of PLACLK pulses for: * * * * Configuration Initialization, Each configured memory, and Applicable Configuration Continues, and Configuration Halt In the example timing diagrams shown in this chapter, tBX is the time from tB to tX in Configuration Halt. tBX = tBD + tDV (for each memory) + (tVX * no. of configured memories) Infinite Technology Corporation Phone: 972-437-7800 March 1997 85 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Device Configuration Time Device configuration time is a function of the number of PLACLK pulses and the PLACLK rate. RAD5A4 Configuration Time (13 memories) During PLACLK pulse after PACK changes first second third fourth fifth sixth seventh eighth PRDY Delay tDPR 0 1 2 3 4 5 6 7 PLACLK Input Frequency (MHz) 5 s) tAZ ( 733 1091 1449 1807 2165 2526 2886 3247 10 tAZ ( s) 366 545 724 903 1082 1263 1443 1624 table 35 15 20 tAZ ( s) 244 364 483 602 722 842 962 108 tAZ ( s) 183 273 362 452 541 631 722 812 25 tAZ ( s) 147 218 290 361 433 505 577 649 tAZ - Time for Device Configuration tAZ includes the number of PLACLK pulses for: * * * * Configuration Initialization, Each configured memory, Applicable Configuration Continues, and Configuration Halt. In the example timing diagrams shown in this chapter, tAZ is the time from tA to tZ. tAZ = tAB + tBX (for all 13 memories) + tXY + tYZ where these variable assumptions were made: tAB = time from tA to tB = 1 PLACLK pulse tXY = time from tX to tY = tDPR tYZ = time from tY to tZ = 1 PLACLK pulse 86 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath RAD5A4 Configuration Multiple RAD5A4 Device Configuration Multiple RAD5A4 devices may be configured as shown in the following diagram. In this diagram, setting PGM1 HIGH, with all the PGM0s LOW, will put all of the RAD5A4s in a Passive Configuration Mode. Each RAD5A4 may be configured one at a time by asserting its PGM0 HIGH. Only one PGM0 may be asserted HIGH at a time. This method permits PRDY and PACK to communicate with the host controller one device at a time. All RAD5A4 I/O outputs are in highimpedance state when any devices are being configured. Multiple RAD5A4 Device Configuration PGM0 RAD5A4_0 PGM1 PRDY PACK BUS4IN[15:0] Host Controller PGM0 PGM1 PRDY RAD5A4_1 PGM1 PRDY PACK BUS4IN[15:0] PACK BUS4IN[15:0] PGM0 for device 0 PGM0 for device 1 . . . . . . PGM0 for device n PGM0 RAD5A4_n PGM1 PRDY PACK BUS4IN[15:0] figure 50 Infinite Technology Corporation Phone: 972-437-7800 March 1997 87 RAD5A4 RAD5A4 Configuration Reconfigurable Arithmetic Datapath Configuration Data Word Counter Configuration data is loaded serially by 16-bit data words into the RAD5A4 memories beginning with DW0 and ending at DWmax for each memory being configured. When in Active Configuration Mode, the RAD5A4 updates its internal configuration data word (DW) counter automatically to place the configuration data in the correct memory location. The following diagram illustrates how the DW counter relates to the memory addresses. DWP is the preamble and is not stored in RAD5A4 device memory. BUS4IN[15:0] Preamble (DWP) DW0 DW1 . . . Memory ... . . . DW1 b15 .. b0 DW0 b15 .. b0 DWmax DWmax ... next Preamble DW0 DW1 figure 51 88 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications RAD5A4 I DEVICE SPECIFICATIONS 1. Features * Efficient solution for applying custom numerical algorithms to a high-speed * * * * * * * * data stream 400 Million 16 x 8 Multiply-Accumulate Operations per second Four 100 MHz 16-bit Arithmetic MacroSequencers Integrated High-Speed programmable State Machine Five shared 16-bit internal data buses 10 ns 16 x 8 Multiply in each MacroSequencer 20 ns 16 x 16 Multiply in each MacroSequencer Predictable Datapath Timing In-Circuit Programmability Each MacroSequencer offers: * 1 or 2 dynamically loadable arithmetic macros that may contain nested loops, * * * * * * * * conditional logic and subroutines Concurrent 10 ns Multiply-Accumulate, Add, Shift and Logic operations 48-bit Accumulator in Multiplier-Accumulator 200 MBytes/Second Datapath throughput Zero-overhead looping Smart indexing for efficient FIR, IIR, FFT, and DCT functions 16 configurable I/O pins 48 general purpose 16-bit memories a 32 Word Single-Indexed 1-port Memory a 16 Word Triple-Indexed 3-port Memory Cascadable architecture for multi-stage filtering and 32-bit operations 2. RAD5A4 General Description A RAD5A4 is a high-speed accelerator for data stream algorithms. It is composed of four independent 16-bit fixed-point programmable processors called MacroSequencers that execute multiple instructions on multiple data paths (MIMD). The RAD5A4 also contains a built-in Dual PLA, five 16-bit buses, 64 I/O pins, 16 input pins, and five independent clocks which drive the four MacroSequencers and the Dual PLA at clock rates up to 100 MHz. Infinite Technology Corporation Phone: 972-437-7800 March 1997 89 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath 3. Applications Imaging * Video filter * Multi-media image scaling and image functions * Medical instrumentation * Photo manipulation * Satellite * Radar * Sonar Arithmetic Accelerator for: * Communications (Linear transformations) * Compression * Robotics * FPGA Coprocessor * DSP Coprocessor 4. Ordering and Package Information Device Type Speed (MHz) Interface Type Temp Range Package Pin Count RAD5A4 -70, -100 T, C C Q,H 176 -40, -60 V 5. Block Diagram Simplified RAD5A4 Control and Data Flow Diagram MS3I/O[15:0] MS2I/O[15:0] Bus0 Bus1 Bus2 Bus3 BUS4IN[15:0] PLAI/O[7:0] PLAIN[7:0] Dual PLA 12 MacroSequencer 2 MSPair32 16 16 MSPair23 MacroSequencer 3 16 16 8 MSn Direct Control and Status Pins 8 20 16 Control Bus 32 MS0I/O[15:0] March 1997 8 16 16 8 8 MacroSequencer 0 90 Bus4 MSPair10 16 16 MSPair01 MacroSequencer 1 MS1I/O[15:0] Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Pin List Pin Name No. of Pins Pin Number Pin Function Type VDD 12 VSS 19 14, 24, 35, 49, 59, 74, 84, 98, 109, 119, 147, 162 5, 11, 19, 29, 30, 40, 54, 64, 69, 79, 93, 103, 104, 114, 122, 128, 130, 152, 157 PS Positive Power Supply PS Power Supply: Ground MacroSequencer0 MS0I/O [15:0] 16 MS0CTRL[1:0] MS0AWAIT MS0SEND MS0OE MS0CLK 2 1 1 1 1 Input and output signals of MacroSequencer0 99, 100, 101, 102, 105, 106, 107, 108, 110, 111, 112, 113, 115, 116, 117, 118 125, 126 120 121 124 123 I/O I O O I I MacroSequencer0 Control Signals MacroSequencer0 Await Signal MacroSequencer0 Send Signal MacroSequencer0 Output Enable Positive edge clock for MacroSequencer0 MacroSequencer1 MS1I/O[15:0] 16 MS1CTRL[1:0] MS1AWAIT MS1SEND MS1OE MS1CLK 2 1 1 1 1 67, 68, 70, 71, 72, 73, 75, 76, 77, 78, 80, 81, 82, 83, 85, 86 96, 97 91 92 95 94 Input and output signals of MacroSequencer1 I/O I O O I I MacroSequencer1 Control Signals MacroSequencer1 Await Signal MacroSequencer1 Send Signal MacroSequencer1 Output Enable Positive edge clock for MacroSequencer1 MacroSequencer2 MS2I/O [15:0] 16 MS2CTRL[1:0] MS2AWAIT MS2SEND MS2OE MS2CLK 2 1 1 1 1 34, 33, 32, 31, 28, 27, 26, 25, 23, 22, 21, 20, 18, 17, 16, 15 8, 7 13 12 9 10 Infinite Technology Corporation Phone: 972-437-7800 Input and output signals of MacroSequencer2 I/O I O O I I March 1997 MacroSequencer2 Control Signals MacroSequencer2 Await Signal MacroSequencer2 Send Signal MacroSequencer2 Output Enable Positive edge clock for MacroSequencer2 91 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath Pin List Continued Pin Name No. of Pins Pin Number Pin Type Function MacroSequencer3 66, 65, 63, 62, 61, 60, 58, 57, 56, 55, 53, 52, 51, 50, 48, 47 37, 36 42 41 38 39 MS3I/O [15:0] 16 MS3CTRL[1:0] MS3AWAIT MS3SEND MS3OE MS3CLK 2 1 1 1 1 Dual PLA BUS4IN[15:0] 16 PLAIN[7:0] 8 PLAI/O[7:0] 8 PLACLK 1 155, 156, 158, 159, 160, 161, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172 144, 143, 142, 141, 140, 139, 138, 137 154, 153, 151, 150, 149, 148, 146, 145 6 Configuration PGM0 PGM1 PRDY PACK 1 1 1 1 Scan Test TCK TMS TDI TDO 1 1 1 1 92 Input and output signals of MacroSequencer3 I/O I O O I I MacroSequencer3 Control Signals MacroSequencer3 Await Signal MacroSequencer3 Send Signal MacroSequencer3 Output Enable Positive edge clock for MacroSequencer3 I Inputs to the Dual PLA and bus4. Configuration data inputs in active configuration mode. Inputs to the Dual PLA I/O I/O of the Dual PLA I Positive edge clock for the Dual PLA and configuration. 174 173 3 4 I I I O Configuration input Configuration input Configuration Ready Handshake Signal Program Acknowledge Handshake Signal 127 136 135 129 I I I O Test Clock Input Test Mode Select Input Test Data Input Test Data Output March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Absolute Maximum Ratings Storage Temperature -65C to +150C Ambient Temperature with Power Applied -55C to +125C Junction Temperature -65C to +150C VDD Supply Voltage with Respect to VSS * -0.5V to +7.0V DC Input Voltage -0.5V to VDD +1.0V DC Output or I/O Pin Voltage -0.5V to VDD +1.0V Lead Temperature (Soldering, 10 seconds) 260C *All voltages are with respect to the device VSS terminals in this data sheet. Infinite Technology Corporation Phone: 972-437-7800 March 1997 93 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath TTL-Level Interface TTL-Level Interface Options (Preliminary Specification) Recommended Operating Conditions Symbol Parameter VDD VIH Supply voltage Input HIGH Level VIL TA Input LOW Level Ambient Temperature Symbol MS0CLK, MS1CLK, MS2CLK, MS3CLK, PLACLK Other Inputs Parameter Min Max Unit 4.75 2.4 5.25 VDD+0.3 V V 2.0 -0.3 0 VDD+0.3 0.8 70 V V C -70 -100 Unit Min Max fCLOCK Min Max MS0CLK, MS1CLK, MS2CLK, 0 70 0 100 MS3CLK PLACLK External feedback 0 33 0 43 Normal Mode Internal feedback 0 70 0 100 MHz See Note 1. No feedback 0 83 0 111 PLACLK Active Configuration 0 20 0 25 tWH High-level Clock MS0CLK, MS1CLK, MS2CLK, 6.5 4 Pulse Width MS3CLK ns PLACLK 6 4 tWL Low-level Clock MS0CLK, MS1CLK, MS2CLK, 6.5 4 Pulse Width MS3CLK ns PLACLK 6 4 Note 1: fCLOCK (external feedback) = 1/(tSU + tCO), where tCO is from the registered PLAI/O output configuration. fCLOCK (internal feedback) is measured using internal registers and applies to signal paths from registered outputs within the Dual PLA that are internally connected to the Input Selectors of the Dual PLA. fCLOCK (no feedback) = 1/(tWH + tWL) 94 Clock Frequency March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications TTL-Level Interface Recommended Operating Conditions (Continued) Normal Operating Mode Parameter From (Input) tSU Setup Time tH Hold Time MSnI/O[15:0], MS0CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS1CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS2CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS3CTRL[1:0], BUS4IN[15:0] BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] MS0CLK To Test (Input) Conditions -70 Min -100 Max Min Unit Max MS0CLK MS1CLK 8 6 ns 12 9 ns MS2CLK MS3CLK PLACLK MSnI/O[15:0], MS0CTRL[1:0], BUS4IN[15:0] MS1CLK MSnI/O[15:0], MS1CTRL[1:0], ns 3 4 BUS4IN[15:0] MS2CLK MSnI/O[15:0], MS2CTRL[1:0], BUS4IN[15:0] MS3CLK MSnI/O[15:0], MS3CTRL[1:0], BUS4IN[15:0] 0 0 ns PLACLK BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. Infinite Technology Corporation Phone: 972-437-7800 March 1997 95 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath TTL-Level Interface Recommended Operating Conditions (Continued) Active Configuration Mode Parameter From (Input) tSU Setup Time tH Hold Time To Test (Input) Conditions -70 Min -100 Max Min Unit Max PRDY BUS4IN[15:0] PLACLK PLACLK 3 8 2 6 ns ns PLACLK PLACLK PRDY BUS4IN[15:0] 2 0 2 0 ns ns DC Characteristics Symbol VOH VOL lIH lIL lOZH lOZL ISC IDD IDDS CIN COUT 96 Parameter Output HIGH Voltage Output LOW Voltage TMS, TDI, Input PLACLK, HIGH MSnCLK, Current TCK Other inputs Input LOW TMS, TDI Current Other inputs Off-State Output Current HIGH Off-State Output Current LOW HIGH-State Output Short Circuit Current VDD Supply Current, Dynamic Test Conditions Min VDD = Min, IOH = -4mA VDD = Min, IOL = 8mA VDD = Max, VIN = VDD 2.4 VDD = Max, VIN = 0 V Typ Max Unit 0.4 10 V V A 100 -100 A A -10 A VDD = Max, 100 A VOUT = VDD VDD = Max, -10 A VOUT = 0 V VDD = Max, VOUT = 0.5V, -30 -135 mA TA = 25C See Note 2. VIN = 0V or VDD, VDD = Max, mA f = 25MHz, Outputs open VDD Supply Current, VIN = 0V or VDD, VDD = Max, mA Static f = 0MHz, Outputs open Input Capacitance TA = 25C, VDD = 5.0V, 5 pF f = 1MHz Output Capacitance TA = 25C, VDD = 5.0V, 8 pF f = 1MHz MSnCLK refers to any of MS0CLK, MS1CLK, MS2CLK, or MS3CLK. Note 2: Only one output should be tested at a time and the duration of the short circuit should not exceed one second. March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications TTL-Level Interface AC Characteristics Normal Operating Mode Parameter From To (Input) tCO Clock to Output Delay Time MS0CLK MS1CLK MS2CLK MS3CLK PLACLK tPD Prop. Delay Time tOE Output Enable Time BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] Conditions (Output) MS0I/O[15:0], MS0SEND, MS0AWAIT MS1I/O[15:0], MS1SEND, MS1AWAIT MS2I/O[15:0], MS2SEND, MS2AWAIT MS3I/O[15:0], MS3SEND, MS3AWAIT PLAI/O[7:0] PLAI/O[7:0] -70 Min registered PLAI/O output combinatorial PLAI/O output See Note 3. combinatorial PLAI/O output -100 Max Min Unit Max 25 15 ns 18 14 ns 30 24 ns 24 20 ns MS0OE MS0I/O[15:0] MS1OE MS1I/O[15:0] 25 20 ns MS2OE MS2I/O[15:0] MS3OE MS3I/O[15:0] Through BUS4IN[15:0], MSnI/O[15:0] Dual PLA PLAIN[7:0], 40 33 ns PLAI/O[7:0] See Note 3. PLACLK MSnI/O[15:0] 36 30 ns tOD MS0OE MS0I/O[15:0] Output MS1OE MS1I/O[15:0] 25 20 ns Disable MS2OE MS2I/O[15:0] Time MS3OE MS3I/O[15:0] Through BUS4IN[15:0], MSnI/O[15:0] Dual PLA PLAIN[7:0], 40 33 ns PLAI/O[7:0] See Note 3. PLACLK MSnI/O[15:0] 36 30 ns MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. Note 3: This applies to signal paths from registered outputs within the Dual PLA that are internally connected to the Input Selectors of the Dual PLA. Infinite Technology Corporation Phone: 972-437-7800 March 1997 97 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath TTL-Level Interface AC Characteristics (Continued) Configuration Modes Parameter From To (Input) (Output) Conditions -70 Min -100 Max Min Unit Max PLACLK PACK Active tCO 18 14 ns Config. Clock to Mode Output Delay Time tOE PGM0, PGM1 PACK 20 15 ns PGM0, PGM1 MSnI/O[15:0], Output PLAI/O[7:0] 50 40 ns Enable Time tOD PGM0, PGM1 PACK 20 15 ns PGM0, PGM1 MSnI/O[15:0], Output PLAI/O[7:0] 90 70 ns Disable Time MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. 98 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications 5 V CMOS-Level Interface 5 V CMOS-Level Interface Options (Preliminary Specification) Recommended Operating Conditions Symbol VDD VIH VIL TA Parameter Supply voltage Input HIGH Level Input LOW Level Ambient Temperature Symbol Parameter Min Max 4.75 0.7*VDD -0.3 0 5.25 VDD+0.3 0.2*VDD 70 V V V C -100 Unit -70 Min Max fCLOCK Min Unit Max Clock Frequency MS0CLK, MS1CLK, MS2CLK, 0 70 0 100 MS3CLK PLACLK External feedback 0 31 0 40 Normal Mode Internal feedback 0 70 0 100 MHz See Note 1. No feedback 0 83 0 111 PLACLK Active Configuration 0 20 0 25 tWH High-level Clock MS0CLK, MS1CLK, MS2CLK, 6.5 4 Pulse Width MS3CLK ns PLACLK 6 4 tWL Low-level Clock MS0CLK, MS1CLK, MS2CLK, 6.5 4 Pulse Width MS3CLK ns PLACLK 6 4 Note 1: fCLOCK (external feedback) = 1/(tSU + tCO), where tCO is from the registered PLAI/O output configuration. fCLOCK (internal feedback) is measured using internal registers and applies to signal paths from registered outputs within the Dual PLA that are internally connected to the Input Selectors of the Dual PLA. fCLOCK (no feedback) = 1/(tWH + tWL) Infinite Technology Corporation Phone: 972-437-7800 March 1997 99 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath 5 V CMOS-Level Interface Recommended Operating Conditions (Continued) Normal Operating Mode Parameter From (Input) tSU Setup Time tH Hold Time 100 MSnI/O[15:0], MS0CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS1CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS2CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS3CTRL[1:0], BUS4IN[15:0] BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] MS0CLK To Test (Input) Conditions -70 Min -100 Max Min Unit Max MS0CLK MS1CLK 8 6 ns 12 9 ns MS2CLK MS3CLK PLACLK MSnI/O[15:0], MS0CTRL[1:0], BUS4IN[15:0] MS1CLK MSnI/O[15:0], MS1CTRL[1:0], ns 3 4 BUS4IN[15:0] MS2CLK MSnI/O[15:0], MS2CTRL[1:0], BUS4IN[15:0] MS3CLK MSnI/O[15:0], MS3CTRL[1:0], BUS4IN[15:0] PLACLK BUS4IN[15:0], 0 0 ns PLAIN[7:0], PLAI/O[7:0] MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications 5 V CMOS-Level Interface Recommended Operating Conditions (Continued) Active Configuration Mode Parameter From (Input) tSU Setup Time tH Hold Time To Test (Input) Conditions -70 Min -100 Max Min Unit Max PRDY BUS4IN[15:0] PLACLK PLACLK 3 8 2 6 ns ns PLACLK PLACLK PRDY BUS4IN[15:0] 2 0 2 0 ns ns DC Characteristics Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage lIH Input HIGH Current lIL Input LOW Current lOZH lOZL ISC IDD IDDS CIN COUT TMS, TDI, PLACLK, MSnCLK, TCK Other inputs TMS, TDI Test Conditions VDD = Min, IOH = -4mA VDD = Min, IOH = -10A VDD = Min, IOL = 4mA VDD = Min, IOL = 10A VDD = Max, VIN = VDD VDD = Max, VIN = 0 V Min Typ Max Unit 0.4 0.1 10 V V V V A 100 -100 A A VDD-0.7 VDD-0.1 Other inputs Off-State Output Current HIGH Off-State Output Current LOW HIGH-State Output Short Circuit Current VDD Supply Current, Dynamic -10 A VDD = Max 100 A VOUT = VDD VDD = Max -10 A VOUT = 0 V VDD = Max, VOUT = 0.5V, -30 -135 mA TA = 25C See Note 2. VIN = 0V or VDD, VDD = Max, mA f = 25MHz, Outputs open VDD Supply Current, Static VIN = 0V or VDD, VDD = Max, mA f = 0MHz, Outputs open Input Capacitance TA = 25C, VDD = 5.0V, 5 pF f = 1MHz Output Capacitance TA = 25C, VDD = 5.0V, 8 pF f = 1MHz MSnCLK refers to any of MS0CLK, MS1CLK, MS2CLK, or MS3CLK. Note 2: Only one output should be tested at a time and the duration of the short circuit should not exceed one second. Infinite Technology Corporation Phone: 972-437-7800 March 1997 101 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath 5 V CMOS-Level Interface AC Characteristics Normal Operating Mode Parameter From (Input) tCO Clock to Output Delay Time MS0CLK MS1CLK MS2CLK MS3CLK PLACLK tPD Prop. Delay Time tOE Output Enable Time BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] To Conditions (Output) MS0I/O[15:0], MS0SEND, MS0AWAIT MS1I/O[15:0], MS1SEND, MS1AWAIT MS2I/O[15:0], MS2SEND, MS2AWAIT MS3I/O[15:0], MS3SEND, MS3AWAIT PLAI/O[7:0] PLAI/O[7:0] -70 Min registered PLAI/O output See Note 3. combinatorial PLAI/O output combinatorial PLAI/O output -100 Max Min Unit Max 27 17 ns 20 16 ns 32 26 ns 26 22 ns MS0OE MS0I/O[15:0] MS1OE MS1I/O[15:0] 27 22 ns MS2OE MS2I/O[15:0] MS3OE MS3I/O[15:0] Through Dual BUS4IN[15:0], MSnI/O[15:0] PLA PLAIN[7:0], 42 35 ns PLAI/O[7:0] See Note 3. PLACLK MSnI/O[15:0] 38 32 ns tOD MS0OE MS0I/O[15:0] Output MS1OE MS1I/O[15:0] 27 22 ns Disable MS2OE MS2I/O[15:0] Time MS3OE MS3I/O[15:0] Through Dual BUS4IN[15:0], MSnI/O[15:0] PLA PLAIN[7:0], 42 35 ns PLAI/O[7:0] See Note 3. PLACLK MSnI/O[15:0] 38 32 ns MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. Note 3: This applies to signal paths from registered outputs within the Dual PLA that are internally connected to the Input Selectors of the Dual PLA. 102 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications 5 V CMOS-Level Interface AC Characteristics (Continued) Configuration Modes Parameter From To (Input) (Output) Conditions -70 Min -100 Max Min Unit Max PLACLK PACK Active tCO Config. Clock to ns 16 20 Mode Output Delay Time tOE PGM0, PGM1 PACK 22 17 ns PGM0, PGM1 MSnI/O[15:0], Output PLAI/O[7:0] 53 42 ns Enable Time tOD PGM0, PGM1 PACK 22 17 ns PGM0, PGM1 MSnI/O[15:0], Output PLAI/O[7:0] 93 72 ns Disable Time MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. Infinite Technology Corporation Phone: 972-437-7800 March 1997 103 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath 3.3 V CMOS-Level Interface 3.3 V CMOS-Level Interface Options (Preliminary Specification) Recommended Operating Conditions Symbol VDD VIH VIL TA Parameter Supply voltage Input HIGH Level Input LOW Level Ambient Temperature Symbol Parameter Min Max 3.0 0.7*VDD -0.3 0 3.6 VDD+0.3 0.2*VDD 70 V V V C -40 -60 Unit Min Max fCLOCK Min Unit Max MS0CLK, MS1CLK, MS2CLK, 0 40 0 60 MS3CLK PLACLK External feedback 0 20 0 25 Normal Mode Internal feedback 0 40 0 60 MHz See Note 1. No feedback 0 45 0 66 PLACLK Active Configuration 0 10 0 15 tWH High-level Clock MS0CLK, MS1CLK, MS2CLK, 11 7.5 Pulse Width MS3CLK ns PLACLK 10 7.5 tWL Low-level Clock MS0CLK, MS1CLK, MS2CLK, 11 7.5 Pulse Width MS3CLK ns PLACLK 10 7.5 Note 1: fCLOCK (external feedback) = 1/(tSU + tCO), where tCO is from the registered PLAI/O output configuration. fCLOCK (internal feedback) is measured using internal registers and applies to signal paths from registered outputs within the Dual PLA that are internally connected to the Input Selectors of the Dual PLA. fCLOCK (no feedback) = 1/(tWH + tWL) 104 Clock Frequency March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications 3.3 V CMOS-Level Interface Recommended Operating Conditions (Continued) Normal Operating Mode Parameter From (Input) tSU Setup Time tH Hold Time MSnI/O[15:0], MS0CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS1CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS2CTRL[1:0], BUS4IN[15:0] MSnI/O[15:0], MS3CTRL[1:0], BUS4IN[15:0] BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] MS0CLK To Test (Input) Conditions -40 Min -60 Max Min Unit Max MS0CLK MS1CLK 14 10 ns 20 15 ns MS2CLK MS3CLK PLACLK MSnI/O[15:0], MS0CTRL[1:0], BUS4IN[15:0] MS1CLK MSnI/O[15:0], MS1CTRL[1:0], ns 5 7 BUS4IN[15:0] MS2CLK MSnI/O[15:0], MS2CTRL[1:0], BUS4IN[15:0] MS3CLK MSnI/O[15:0], MS3CTRL[1:0], BUS4IN[15:0] 0 0 ns PLACLK BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. Infinite Technology Corporation Phone: 972-437-7800 March 1997 105 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath 3.3 V CMOS-Level Interface Recommended Operating Conditions (Continued) Active Configuration Mode Parameter From (Input) tSU Setup Time tH Hold Time To Test (Input) Conditions -40 Min -60 Max Min Unit Max PRDY BUS4IN[15:0] PLACLK PLACLK 5 14 3 10 ns ns PLACLK PLACLK PRDY BUS4IN[15:0] 3 0 3 0 ns ns DC Characteristics Symbol Parameter VOH Output HIGH Voltage VOL Output LOW Voltage lIH Input HIGH Current lIL Input LOW Current lOZH lOZL ISC IDD IDDS CIN COUT 106 TMS, TDI, PLACLK, MSnCLK, TCK Other inputs TMS, TDI Test Conditions VDD = Min, IOH = -2mA VDD = Min, IOH = -10A VDD = Min, IOL = 2mA VDD = Min, IOL = 10A VDD = Max, VIN = VDD VDD = Max, VIN = 0 V Min Typ Max Unit 0.4 0.1 10 V V V V A 100 -100 A A VDD-0.7 VDD-0.1 Other inputs Off-State Output Current HIGH Off-State Output Current LOW HIGH-State Output Short Circuit Current VDD Supply Current, Dynamic -10 A VDD = Max, 100 A VOUT = VDD VDD = Max, -10 A VOUT = 0 V VDD = Max, VOUT = 0.5V, -20 -135 mA TA = 25C See Note 2. VIN = 0V or VDD, VDD = Max, mA f = 25MHz, Outputs open VDD Supply Current, Static VIN = 0V or VDD, VDD = Max, mA f = 0MHz, Outputs open Input Capacitance TA = 25C, VDD = 3.3V, 5 pF f = 1MHz Output Capacitance TA = 25C, VDD = 3.3V, 8 pF f = 1MHz MSnCLK refers to any of MS0CLK, MS1CLK, MS2CLK, or MS3CLK. Note 2: Only one output should be tested at a time and the duration of the short circuit should not exceed one second. March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications 3.3 V CMOS-Level Interface AC Characteristics Normal Operating Mode Parameter From To (Input) tCO Clock to Output Delay Time MS0CLK MS1CLK MS2CLK MS3CLK PLACLK tPD Prop. Delay Time tOE Output Enable Time BUS4IN[15:0], PLAIN[7:0], PLAI/O[7:0] Conditions (Output) MS0I/O[15:0], MS0SEND, MS0AWAIT MS1I/O[15:0], MS1SEND, MS1AWAIT MS2I/O[15:0], MS2SEND, MS2AWAIT MS3I/O[15:0], MS3SEND, MS3AWAIT PLAI/O[7:0] PLAI/O[7:0] -40 Min registered PLAI/O output combinatorial PLAI/O output See Note 3. combinatorial PLAI/O output -60 Max Min Unit Max 42 33 ns 30 24 ns 50 40 ns 40 33 ns MS0OE MS0I/O[15:0] MS1OE MS1I/O[15:0] 42 33 ns MS2OE MS2I/O[15:0] MS3OE MS3I/O[15:0] Through Dual BUS4IN[15:0], MSnI/O[15:0] PLA PLAIN[7:0], 67 55 ns PLAI/O[7:0] See Note 3. PLACLK MSnI/O[15:0] 60 50 ns tOD MS0OE MS0I/O[15:0] Output MS1OE MS1I/O[15:0] 42 33 ns Disable MS2OE MS2I/O[15:0] Time MS3OE MS3I/O[15:0] Through Dual BUS4IN[15:0], MSnI/O[15:0] ns PLA PLAIN[7:0], 67 55 PLAI/O[7:0] See Note 3. PLACLK MSnI/O[15:0] 60 50 ns MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. Note 3: This applies to signal paths from registered outputs within the Dual PLA that are internally connected to the Input Selectors of the Dual PLA. Infinite Technology Corporation Phone: 972-437-7800 March 1997 107 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath 3.3 V CMOS-Level Interface AC Characteristics (Continued) Configuration Modes Parameter From To (Input) (Output) Conditions -40 Min -60 Max Min Unit Max PLACLK PACK Active tCO Config. Clock to ns 23 30 Mode Output Delay Time tOE PGM0, PGM1 PACK 33 25 ns PGM0, PGM1 MSnI/O[15:0], Output PLAI/O[7:0] 100 65 ns Enable Time tOD PGM0, PGM1 PACK 33 25 ns PGM0, PGM1 MSnI/O[15:0], Output PLAI/O[7:0] 140 110 ns Disable Time MSnI/O[15:0] refers to any of MS0I/O[15:0], MS1I/O[15:0], MS2I/O[15:0], or MS3I/O[15:0]. 108 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Timing Diagrams A common set of timing diagrams is used for the TTL-level, 5 V CMOS-level, and 3.3 V CMOS-level interface options of the RAD5A4. Voltage levels that apply to each of the three interface options are in the table below: Voltage RAD5A4 Interface Options TTL 5 V CMOS 3.3 V CMOS VIH 3.0 V VDD VDD VIL 0.0 V 0.0 V 0.0 V 50% VDD 50% VDD VTHZ VOH - 0.5 V 1.5 V VOH - 0.5 V VOH - 0.3 V VTLZ VOL + 0.5 V VOL + 0.5 V VOL + 0.3 V VT All Input Signals 2ns Inputs 90% 2ns VIH 90% 10% 10% VIL Clock Inputs 2ns Clock Inputs 10% 90% VT 2ns 90% VT tWH VIH VT 10% 1/fCLOCK VIL tWL tSU & tH Setup and Hold Times Input or I/O Input VIH VT VT tSU Clock Input tH VIL VIH VT VIL Infinite Technology Corporation Phone: 972-437-7800 March 1997 109 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath Timing Diagrams (Continued) tCO Clock to Output Delay Time Clock Input VIH VT VIL tCO VOH VT Output VOL tPD Propagation Delay Time Input or I/O Input VT VIH VT VIL tPD VOH VT Output VOL tOE & tOD Input to Output Enable/Disable Times from MSnOE, BUS4IN, PLAIN, or PLAI/O Input or I/O Inputs VT tOD VTH Output VIH VT VTLZ Z VIL tOE VO VT VT Hi-Z H VOL tOE & tOD Input to Output Enable/Disable Times from PLACLK PLACLK Input VT tOD Output 110 VTHZ VIH VT VTLZ tOE Hi-Z March 1997 VT VT VIL VOH VOL Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Timing Diagrams (Continued) tOE & tOD Input to Output Enable/Disable Times from PGM0 or PGM1 VIH PGM_a Input VT VT VIL VIH PGM_b Input VT VT PACK Output VTHZ VT Hi-Z VIL tOD tOE tOD VTHZ VTLZ I/O Outputs VOH Hi-Z tOE VOL VT VT Hi-Z VOH VOL PGM0 and PGM1 are identical inputs and are represented by PGM_a and PGM_b to allow a single diagram to represent them. PGM_a represents the first of PGM0 or PGM1 to change states. AC Measurement Diagram of the Load Circuit for Output VA I1 Output under test S1 Test Point S2 CL Output load Test Condition TTL VA 3.5 V VDD VDD I1 8 mA 4 mA 2 mA I2 I2 CL GND Test tCO, tPD tOE tOD Infinite Technology Corporation Phone: 972-437-7800 5V CMOS 3.3 V CMOS 4 mA 4 mA 2 mA tPD, tCP, tOE 35 pF 35 pF 35 pF tDD 5 pF 5 pF 5 pF Output Transition S1 S2 HL open open LH open open ZH open closed ZL closed open HZ open closed LZ closed open March 1997 111 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath Transitioning between Active and Normal Operating Modes During Active Configuration (PGM0 = PGM1 = HIGH), the Controln[1:0] circuitry is disabled. The Controln[1:0] circuitry remains disabled after Active Configuration ends until the first LOW to HIGH (l) transition of Controln[1] activates the Controln[1:0] circuitry to the SetSequence0 or SetSequence2 command on the following MSnCLK (l) clock pulse. Once activated, the Controln[1:0] circuitry will remain active until the next Active Configuration Mode occurs or power is removed from VDD. As soon as Active Configuration Mode ends (the first of PGM0 or PGM1 goes LOW), the MacroSequencer begins execution of LIW0. MacroSequencern will repeatedly execute LIW0 on each MSnCLK cycle as long as the Controln[1:0] circuitry is disabled. After activation, the Controln[1:0] circuitry will respond correctly to each of the four operating commands listed in the table below: Controln [1:0] Command 0 0 0 1 1 0 Run Continue SetSequence0 1 1 SetSequence2 Description Normal Operating Condition Reset Send and Await registers. The Program Counter is set to `0'. Resets the Send and Await registers. This must be asserted for at least two cycles. The Program Counter is set to `2'. Resets the Send and Await registers. This must be asserted for at least two cycles. Example MacroSequencer Instructions Programmed for 2 Sequences ; LIW0 jump sequence0 ; LIW 1 indexdirect or indexmode ; LIW 2 indexdirect or indexmode ;LIW 3 ; something to execute repeatedly, no read or write operations ; operations used to set up the index registers for 1st sequence ; operations used to set up the index registers for 2nd sequence ; continue second sequence of operations Example MacroSequencer Instructions Programmed for 1 Sequence ; LIW0 indexdirect or indexmode ; something to execute repeatedly, no read or write operations ;LIW 1 ; continue sequence of operations The index registers must be initialized before any read or write operations. The use of indexdirect and indexmode should precede any read or write operations. If the 1-port or 3-port memories are not used, then any operation can appear in LIW0 and/or LIW2. 112 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Waveforms Either MSnCtrl[1:0] pins or PLACtrln[1:0] may be used for the Controln[1:0] MacroSequencer inputs. When using PLACtrln [1:0] signals, allow two clock cycles for latency. There is no latency with the MSnCtrl[1:0] signals. Under Dual PLA control, both PLACtrln[1:0] signals are LOW when Active Configuration ends. When PLACLK and MSnCLK are connected together, a minimum of two clock cycles will occur after Active Configuration before Controln[1] will first go HIGH to activate the Controln[1:0] circuitry. Input Voltage waveforms for transitioning between Active Configuration Mode and Normal Operating Mode using the MSnCtrl[1:0] pins to provide the Controln[1:0] signals are shown below. PGM0 and PGM1 are referenced as PGM_a and PGM_b because either pin may change first, or they may be changed at the same time. Operating Mode Transitioning VIH PGM_a Input VT VT VIL PGM_b Input VIH VT tREC1 VIL tREC2 MSnCtrl[1] Input VT VIH VT VIL VIH MSnCtrl[0] Input VT VIL tSU MSnCLK Input VIH VT tOD VTHZ VTLZ I/O Outputs VIL tOE Hi-Z VT VT VOH VOL Use tREC1 = tREC2 = 20 ns minimum. All times on this diagram are independent of MSnCLK frequency within device specifications. Infinite Technology Corporation Phone: 972-437-7800 March 1997 113 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 NC NC PGM0 PGM1 BUS4IN0 BUS4IN1 BUS4IN2 BUS4IN3 BUS4IN4 BUS4IN5 BUS4IN6 BUS4IN7 BUS4IN8 BUS4IN9 VDD BUS4IN10 BUS4IN11 BUS4IN12 BUS4IN13 VSS BUS4IN14 BUS4IN15 PLAI/O7 PLAI/O6 VSS PLAI/O5 PLAI/O4 PLAI/O3 PLAI/O2 VDD PLAI/O1 PLAI/O0 PLAIN7 PLAIN6 PLAIN5 PLAIN4 PLAIN3 PLAIN2 PLAIN1 PLAIN0 TMS TDI NC NC Pin Diagram (Top View) 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NC NC VSS TDO VSS TCK MS0CTRL0 MS0CTRL1 MS0OE MS0CLK VSS MS0SEND MS0AWAIT VDD MS0I/O0 MS0I/O1 MS0I/O2 MS0I/O3 VSS MS0I/O4 MS0I/O5 MS0I/O6 MS0I/O7 VDD MS0I/O8 MS0I/O9 MS0I/O10 MS0I/O11 VSS VSS MS0I/O12 MS0I/O13 MS0I/O14 MS0I/O15 VDD MS1CTRL0 MS1CTRL1 MS1OE MS1CLK VSS MS1SEND MS1AWAIT NC NC NC NC MS3I/O0 MS3I/O1 VDD MS3I/O2 MS3I/O3 MS3I/O4 MS3I/O5 VSS MS3I/O6 MS3I/O7 MS3I/O8 MS3I/O9 VDD MS3I/O10 MS3I/O11 MS3I/O12 MS3I/O13 VSS MS3I/O14 MS3I/O15 MS1I/O15 MS1I/O14 VSS MS1I/O13 MS1I/O12 MS1I/O11 MS1I/O10 VDD MS1I/O9 MS1I/O8 MS1I/O7 MS1I/O6 VSS MS1I/O5 MS1I/O4 MS1I/O3 MS1I/O2 VDD MS1I/O1 MS1I/O0 NC NC NC NC PRDY PACK VSS PLACLK MS2CTRL0 MS2CTRL1 MS2OE MS2CLK VSS MS2SEND MS2AWAIT VDD MS2I/O0 MS2I/O1 MS2I/O2 MS2I/O3 VSS MS2I/O4 MS2I/O5 MS2I/O6 MS2I/O7 VDD MS2I/O8 MS2I/O9 MS2I/O10 MS2I/O11 VSS VSS MS2I/O12 MS2I/O13 MS2I/O14 MS2I/O15 VDD MS3CTRL0 MS3CTRL1 MS3OE MS3CLK VSS MS3SEND MS3AWAIT NC NC NC = No internal connection 114 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications RAD5A4 PIN Description Following is a complete and detailed listing of each of the RAD5A4 pin connections sorted by function. Power Supply Pins VDD Symbol Type No. of Pins Pin Number VDD Positive Power Supply 12 14, 24, 35, 49, 59, 74, 84, 98, 109, 119, 147, 162 This device must have all VDD pins connected to insure proper operation. VSS Symbol Type No. of Pins Pin Number VSS Power Supply: Ground 19 5, 11, 19, 29, 30, 40, 54, 64, 69, 79, 93, 103, 104, 114, 122, 128, 130, 152, 157 This device must have all VSS pins connected to insure proper operation. Infinite Technology Corporation Phone: 972-437-7800 March 1997 115 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath MacroSequencer Pins Pin Types Summary of MacroSequencer Pins MS0 MS1 MS2 MS3 MS0I/O[15:0] 16 99, 100, 101, 102, 105, 106, 107, 108, 110, 111, 112, 113, 115, 116, 117, 118 MS1I/O[15:0] 16 67, 68, 70, 71, 72, 73, 75, 76, 77, 78, 80, 81, 82, 83, 85, 86 MS2I/O[15:0] 16 34, 33, 32, 31, 28, 27, 26, 25, 23, 22, 21, 20, 18, 17, 16, 15 MS3I/O[15:0] 16 66, 65, 63, 62, 61, 60, 58, 57, 56, 55, 53, 52, 51, 50, 48, 47 I/O Pins: Symbol No of Pins Pin Numbers Control Pins: Symbol No of Pins Pin Numbers AWAIT Pins: Symbol No of Pins Pin Number SEND Pins: MS0CTRL[1:0] MS1CTRL[1:0] MS2CTRL[1:0] MS3CTRL[1:0] 2 125, 126 2 96, 97 2 8, 7 2 37, 36 MS0AWAIT MS1AWAIT MS2AWAIT MS3AWAIT 1 120 1 91 1 13 1 42 MS1SEND MS2SEND MS3SEND 1 92 1 12 1 41 Symbol MS0SEND No of Pins 1 Pin Number 121 Output Enable Pins: 116 Symbol No of Pins Pin Number Clock Pins: MS0OE MS1OE MS2OE MS3OE 1 124 1 95 1 9 1 38 Symbol No of Pins Pin Number MS0CLK MS1CLK MS2CLK MS3CLK 1 123 1 94 1 10 1 39 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications MacroSequencer I/O Pins Output signals from the MacroSequencers are multiplexed with the corresponding MSnI/O input pins to provide the signals for the busns. The busn inputs may be from either the MacroSequencer(n)'s Output Register, OutRegA, or from the MSnI/O pins. MacroSequencer Control Input Pins The MacroSequencer Control signal inputs provide direct control to initialize MacroSequencer(n) operation when the device is configured to use them. MacroSequencer (n) Control Signals MSnCTRL MSnCTRL [0] [1] 0 0 0 1 1 1 0 1 Result Run Continue, Reset Send and Await signals SetSequence0 SetSequence2 These pins are not used if the MacroSequencer Control Signals are from the Dual PLA. MacroSequencer AWAIT Output Pins The Await signal is used by each MacroSequencer(n) to indicate an Await state. MacroSequencer(n) AWAIT Signal MSnAWAIT 0 1 Infinite Technology Corporation Phone: 972-437-7800 Result Normal Operation of MacroSequencer MacroSequencer has stalled and executes an instruction repeatedly until a Continue control state is encountered. March 1997 117 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath MacroSequencer SEND Output Signals The Send signal is used by each MacroSequencer(n) to indicate a Send state. MacroSequencer (n) SEND Signal MSnSEND 0 1 Result Normal Operation of MacroSequencer Normal Operation continues, but SEND remains a "1" until a Continue control state is encountered. MacroSequencer Output Enable Input Pins The MSnOE pins provide direct control of the enable/disable functions for the MSnI/O outputs when the device is configured to use them. MacroSequencer configuration bits select whether the MSnOE pins are active-HIGH or activeLOW. These pins are not used if the oepla[n] Signals are from the Dual PLA. MacroSequencer Clock Signals MSnCLK The MacroSequencer Clock Pins provide positive edge clock signals for the MacroSequencers. Each MacroSequencer has its own independent clock signal. The MacroSequencer clock pins may be externally tied together to use the same clock sources. Bus 4 Input Pins Symbol Type No. of Pins Pin Number BUS4IN[15:0] Input 16 155, 156, 158, 159, 160, 161, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172 During normal operation mode, these pins drive: * PLA Input Bus4[15:0] * MacroSequencer data Bus4[15:0] During active configuration, these pins are used to provide input data for the configuration process. 118 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications PLA Pins PLAI/O[7:0] Symbol Type No. of Pins Pin Number PLAI/O[7:0] I/O 8 154, 153, 151, 150, 149, 148, 146, 145 Input/Output for Dual PLA. They connect to: * PLA Input PLAI/O[7:0] * PLA1 Output Signals : Combinatorial or Registered Outputs selected by Configuration Bits PLAIN[7:0] Symbol Type No. of Pins Pin Number PLAIN[7:0] Input 8 144, 143, 142, 141, 140, 139, 138, 137 Inputs to the Dual PLA connecting to PLAIN[7:0] PLACLK Symbol Type No. of Pins Pin Number PLACLK Input 1 6 The PLACLK provides a positive edge clock signal for the Dual PLA and for device configuration. Infinite Technology Corporation Phone: 972-437-7800 March 1997 119 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath Configuration Pins Symbol: No. of Pins Pin Number Type Function: PGM0 PGM1 PRDY PACK 1 174 Input Configuration mode0 1 173 Input Configuration mode1 1 3 Input Configuration Ready signal 1 4 Output Configuration Acknowledge PGM0 and PGM1: Configuration Mode Pins The PGM0 and PGM1 pins are used as inputs to determine the operation mode of the RAD5A4. They are functionally identical. * When both pins are HIGH, the RAD5A4 is in Active Configuration Mode. In this mode, all I/O outputs are in a high-impedance state, and most internal registers and flip-flops that are used in normal operation mode are held in an initialized state. The PACK pin is enabled for output. * When they are both LOW, the device and all I/O pins are in Normal Operating Mode, and PACK is in a high-impedance state. No configuration of the device may occur. * When one is LOW and one is HIGH (either one), the device is in a Passive Configuration Mode and all I/O outputs and PACK are in a high-impedance state. No configuration of the device may occur. PRDY: Configuration Ready Signal During Active Configuration Mode, external circuitry uses the PRDY input to indicate when a configuration data word is present on BUS4IN[15:0] pins and ready to be loaded into the RAD5A4. PACK: Configuration Acknowledge During Active Configuration Mode, PACK signals from the RAD5A4 when the next configuration action may begin. 120 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Scan Pins Symbol: No. of Pins Pin Number Type Function: TCK TMS TDI TDO 1 127 Input Test Clock Input 1 136 Input Test Mode Select Input 1 135 Input Test Data Input 1 129 Output Test Data Output The IEEE 1149.1a Boundary Scan Protocol provides a low pin count method for testing systems specified in the IEEE Standard Test Access Port and Boundary Scan Architecture, (c) 1993, Institute of Electrical and Electronics Engineers, Inc., New York, ISBN 1-55937-350-4. The Boundary Scan Protocol uses a serial protocol involving four special purpose pins: TDI, TDO, TCK, TMS, which are known as the TAP (Test Access Port) pins. The TAP pins allow the state of all active logic signals to be examined and for the state of most registers in the four MacroSequencers to be examined. TCK: Test Clock Input The TCK pin is the test access port clock which serves as the scan protocol clock. TMS: Test Mode Select Input The TMS pin is the test mode select input. It is sampled on the rising edge of TCK. TDI: Test Data Input The TDI is sampled on the rising edge of TCK. TDO: Test Data Output Changes on TDO occur only on the falling edge of TDK. Infinite Technology Corporation Phone: 972-437-7800 March 1997 121 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath Package Characteristics Operating clock frequency and package characteristics affect power dissipation and junction temperature. Power Dissipation Versus Clock Frequency Power dissipation of a RAD5A4 can vary over a wide range depending on MacroSequencer specific algorithms, clock frequency, number and frequency of outputs switching, output loading, supply voltage and interface type. Graphical representation of power dissipation versus clock frequency for representative RAD5A4 device applications are shown here: Estimated RAD5A4 Power Dissipation versus Clock Input Frequency for Two Typical Applications: TTL-Interface PD- Power Dissipation (mW) 2500 4 MacroSequencers Switching and 32 I/O Outputs Switching at 25% fCLK Frequency VDD = 5 V TA = 25C CL = 50 pF 2000 1500 1000 1 MacroSequencer Switching and 16 I/O Outputs Switching at 25% fCLK Frequency 500 0 0 20 40 60 80 100 fCLK - Clock Frequency (MHz) 122 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Estimated RAD5A4 Power Dissipation versus Clock Input Frequency for Two Typical Applications: 5 V CMOS-Interface 3500 VDD = 5 V TA = 25C CL = 50 pF PD- Power Dissipation (mW) 3000 4 MacroSequencers Switching and 32 I/O Outputs at Switching at 25% fCLK Frequency 2500 2000 1500 1000 1 MacroSequencer Switching and 16 I/O Outputs Switching at 25% fCLK Frequency 500 0 0 10 20 30 40 50 60 70 80 90 100 fCLK - Clock Frequency - MHz Estimated RAD5A4 Power Dissipation versus Clock Input Frequency for Typical Applications: 3.3 V CMOS-Interface PD- Power Dissipation (mW) 900 VDD = 3.3 V T A = 25C CL = 50 pF 800 700 4 MacroSequencers Switching and 32 I/O Outputs Switching at 25% fCLK Frequency 600 500 400 300 1 MacroSequencer Switching and 16 I/O Output Switeching at 25% fCLK Frequency 200 100 0 0 Infinite Technology Corporation Phone: 972-437-7800 10 20 30 40 fCLK - Clock Frequency (MHz) March 1997 50 60 123 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath Thermal Characteristics Virtual junction temperature of the chip may be estimated using thermal characteristics of the device package and the applications system and power dissipation of the device in the application. Calculating Junction Temperature TJ = TA + PD * RJA TJ = TC + PD * RJC where: TJ TA TC PD RJA RJC = = = = = = Virtual junction temperature Free air (ambient) temperature Case temperature Average device power dissipation Junction-to-air (ambient) thermal resistance characteristic Junction-to-case thermal resistance characteristic Package Thermal characteristics for RJA are shown with two different air-flow rates. Package RJC TQFP Power TQFP RJA RJA in still air 300 ft/min 38 23 32 20 2.2 0.6 Unit C/W C/W Maximum Power Dissipation Maximum junction temperature allowable for the RAD5A4 is 150C. However, a maximum junction temperature of 140C is recommended for continuous operation. PD = (TJ - TC) / RJA where: PD TJ TC RJA = = = = Average device power dissipation Virtual junction temperature Case Temperature Junction-to-air (ambient) thermal resistance characteristic A sample calculation of the maximum power dissipation for a power TQFP package in still air at recommended operating conditions is as follows: Max. junction temp (C) - Max. commercial temp (C) R JA (C/W) 124 March 1997 140C - 70C = 3.04W = 23C/W Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Clock Frequency Versus Temperature Switching times increase as junction temperature increases; therefore maximum clock frequency decreases with increased junction temperature. Optimum device speed performance is achieved when chip junction temperature rise is minimized for a given application. Both the TQFP package and the Power TQFP package have identical mechanical dimensions and mechanically may be used interchangeably. The TQFP package may be used in lower power and/or lower performance applications. The Power TQFP package may be used in applications requiring higher power and/or higher performance. A heat sink may be attached directly to the metal slug of the Power TQFP package. Infinite Technology Corporation Phone: 972-437-7800 March 1997 125 RAD5A4 Device Specifications Preliminary Reconfigurable Arithmetic Datapath Package Mechanical Details Thin Quad Flat Pack (TQFP), 176 pins Top View E E1 E 2 132 A 89 a L 88 133 D1 D D 2 45 e b 44 PIN 1 Identification 1 176 0 - 7 A2 A1 Symbol A A1 A2 D D1 E E1 L e b a Minimum 0.05 1.35 0.45 0.17 0.09 Nominal 1.40 26.00 BSC 24.00 BSC 26.00 BSC 24.00 BSC 0.60 0.50 BSC 0.22 Maximum Unit 1.60 0.15 1.45 mm mm mm mm mm mm mm mm mm mm mm 0.75 0.27 0.16 Notes Lead pitch Lead width Lead thickness This package conforms to JEDEC specification MO-136, variation BV. 126 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Preliminary Device Specifications Power TQFP, 176 pins Top View E E1 E 2 132 A 89 Hx a L 88 133 Hy ~ D1 D D 2 PIN 1 Identification 0 - 7 e b 44 45 1 176 Embedded Heat Sink 3.127 x 45 CHAMFER 4 PLACES A2 A1 Symbol A A1 A2 D D1 E E1 Hx Hy L e b a Minimum 0.05 1.35 19.00 REF 19.00 REF 0.45 0.17 0.09 Nominal 1.40 26.00 BSC 24.00 BSC 26.00 BSC 24.00 BSC 19.40 REF 19.40 REF 0.60 0.50 BSC 0.22 Maximum Unit 1.60 0.15 1.45 mm mm mm mm mm mm mm mm mm mm mm mm mm 20.00 REF 20.00 REF 0.75 0.27 0.16 Notes Leadpitch Lead width Lead thickness This package conforms to JEDEC specification MO-136, variation BV. Infinite Technology Corporation Phone: 972-437-7800 March 1997 127 RAD5A4 Revision History Reconfigurable Arithmetic Datapath Revision History This data book replaces: RAD5A4 Data Book May 1996 RAD5A4 Data Book March 1996 RAD5A4 Data Book February 1996 RAD5A4 Data Book January 1996 RAD5A4 Data Book December 1995 RAD5A4 Data sheet April 1995 128 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Terms & Definitions Terms & Definitions Acronyms, terms, and definitions useful in RAD5A4 discussions will be listed in this chapter. Acronyms Acronym DW DWP DWmax High-Z MIMD PLA InRegA InRegB InRegC LIW MAC MIMD MS Meaning Data word Preamble data word Last data word in a data packet High-Impedance Multiple Instructions Multiple Datapath Programmable Logic Array Input Register A Input Register B Input Register C Long Instruction Word Multiply-Accumulate or Multiplier-Accumulator Multiple Instructions on Multiple Data paths MacroSequencer Infinite Technology Corporation Phone: 972-437-7800 March 1997 129 RAD5A4 Terms and Definitions Reconfigurable Arithmetic Datapath Glossary bus0,1,2,3,4 A The RAD5A4 possesses five 16 bit buses which are tied directly to pins. These buses are known as bus0, bus1, bus2, bus3, and bus4. The first four buses also directly connect to the MacroSequencers. They connect to the pins and MacroSequencers as follows: * bus0 connects to MS0I/O and MacroSequencer 0. * bus1 connects to MS1I/O and MacroSequencer 1. * bus2 connects to MS2I/O and MacroSequencer 2. * bus3 connects to MS3I/O and MacroSequencer 3. * bus4 connects to BUS4IN. Active Configuration Mode Device can be configured in this mode. PGM0 and PGM1 are HIGH. Adder Status Signals Equal, Overflow, Sign,and Carry Status bits from the Adder provided for conditional branches. Algorithm A sequence of arithmetic and control functions. AND Array Array of AND gates. There are two AND arrays in the Dual PLA which produce 34 product terms. BUS4IN[15:0] Arithmetic Datapath Bus4 pins to the RAD5A4. This term refers to the arithmetic related elements in the MacroSequencers such as the Multiplier-Accumulator, Shifter, Adder, and Logic unit. Bypass Register This is a 1 bit serial register whose purpose is to bypass the Boundary and other internal scan paths of the chip. Asynchronous hand-shaking C Hand-shaking protocol useful when configuring the RAD5A4 where inputs are not synchronized with a clock signal. Concurrent processing This is the simultaneous operation of processing units ( ie: adder MAC Shifter, Control etc.). B Boundary Scan Path This is the Scan Path which relates to the pins of the RAD5A4. It contains registers capturing not only the pins, but also output enable information. Configuration Bits There are MacroSequencer and PLA programmable configuration bits. Configuration Continue Configuration status that occurs at the end of a data packet after the last data word has been loaded and before the next data packet may be loaded. Branch Operations The MacroSequencer Datapath Controller supports the following branch operations: call, return, jump, jumpcounter0, jumpcounter1, jumpequal, jumpoverflow and jumpsign. These operations may either unconditionally or conditionally alter the state of the Program Counter. 130 Configuration Data Packet Set of configuration data words to program a memory in the RAD5A4 Configuration Data Word March 1997 16-bit data words comprising a configuration data packet. Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Terms and Definitions Configuration Data Word Counter C[ k ] = Used internally by the RAD5A4 to load the configuration data words into the correct memory locations. Counter0, Counter1 These are counters used for loops in the MacroSequencer Controller. Note: the above two are the same. File generated by RADware software for configuring the RAD5A4. When this file is loaded into the RAD5A4 it is configured. Count down Configuration Halt This is a single bit register in the Control component of each Index Register of the MacroSequencer's Datapath Controller. If it contains a `1', then the address component will decrement every time its associated memory access port is accessed. If both Count_up and Count_down contain `0', the address is held. It is illegal for both Count_up and Count_down to both contain `1'. Configuration status that occurs at the end of a data packet after the last data word has been loaded from the configuration file. Configuration Initialization Configuration status that occurs at the beginning of Active Configuration Mode before the configuration file is loaded. Configuration Memories RAD5A4 memories that can be configured or programmed. They include the Dual PLA memory, and a LIW, 3-port, and 1-port memory in each of the 4 MacroSequencers. Count up This is a single bit register in the Control component of each Index Register of the MacroSequencer's Datapath Controller. If it contains a `1', then the address component will increment every time its associated memory access port is accessed. If both Count_up and Count_down contain `0', the address is held. It is illegal for both Count_up and Count_down to both contain `1'. Constant Input see internal signal Continue Command sent to the MacroSequencer Datapath Controller from either external pins or the Dual PLA control signals. The Continue command resets the Send and Await status signals and allows the program counter to operate under control of the LIW sequence. D Data Bus Five buses used for carrying data to and from the MacroSequencers named bus0, bus1, bus2, bus3, and bus4. Control Bus RAD5A4 internal bus for control signals such as the Send and Await signals. Data Memory Data Memory is the memory within each RAD5A4 MacroSequencer which may be used to store data. It is composed of the 1port and 3-port Memories. See also 1-port Memory, 3-port Memory, Index Register and MacroSequencer entries. In the Dual PLA, the Control OR is an OR array that can produce the control signals to the MacroSequencers. Convolution Given two discrete time input streams A[ ] and B[ ], a convolution may be defined as an output stream C[ ] where C[ k ] = Datapath Controller Located in each MacroSequencer, a datapath controller contains the LIW memory, sequences through the instructions, and produces LIW control bits for the MacroSequencer Arithmetic Datapath. a A[n]* B[n - k ] n =- The Finite Impulse Response version of this becomes Infinite Technology Corporation Phone: 972-437-7800 a A[n]* B[n - k ] n= k - M Configuration File Control OR N +k March 1997 131 RAD5A4 Terms and Definitions Reconfigurable Arithmetic Datapath E I External Signals ID Register There are 7 external input buses; bus0 - bus4 , MSnIO pins and MSPair(nm). This is a serial register within the JTAG Boundary Scan Circuit which identifies the RAD5A4. It contains bits which determine whether the chip is 5V TTL, 5V CMOS, 3.3V CMOS, as well as bits which determine which version of the silicon the part is. F Filter Filters will refer specifically to Finite Impulse Response (FIR) Filters. These are digital filters which operate upon a single input data stream and generate a single output data stream. They successively operate on a fixed number of data stream elements in generating each successive element of the output stream. Consider a one dimensional FIR filter: Let A[0,...] represent the input stream data and B[0,...] represent the output stream data. An FIR filter consists of two positive integer constants M and N and a collection of numbers am[0:M] and an[1:N] such that InBusA, InBusB These are outputs of the Input Selector destined for the MAC, Adder and the Logic Unit. InBusC This is an output of the Input Selector destined for the Shifter. Index Address or location within the 3-port or 1port memory held in Index registers. Index Register The index registers hold the memory addresses for reading and writing data to and from the 1-port and 3-port Memories. Each RAD5A4 MacroSequencer contains 5 Index Registers. One Index Register is used for memory access of the 1-port Memory. Four Index Registers are used for access of the 3-port Memory. Each Index Register is composed of two components: A control circuit and address generation circuit. B[M+k] = am[0]*A[M+k]+...+am[M]*A[k] +an[1]*A[k+1]+...+an[N]*A[N+k] Fixed OR0 and Fixed OR1 The fixed OR arrays found in the Dual PLA. FPGA Field programmable gate array Flags Single bits used for communication between the Adder and MS Controller as well as the MS Controller and either the PLA or external pins. Function Arithmetic operations performed in input data to produce output data. `Function' also may refer to the elements or data blocks found within the MacroSequencers. Input Register Block This is made up of both InRegA and InRegB. Input Selectors - PLA The input selectors provide selection of inputs to the arithmetic processing units. Input Selectors - MacroSequencer G H The input selectors provide selection of inputs to the arithmetic processing units. InRegA, InRegB These are two 16 bit registers connected to external data sources. There are 6 input buses; bus0 - bus4 and MSPair(nm). An additional source of data is a constant from the LIW word. Without an instruction for one of these 7 sources the register holds previous contents. Both registers have access to the same data. Handshake Communication between the RAD5A4 and external circuitry used during configuration. Instruction Memory 132 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Terms and Definitions The 32 x 48-bit LIW memory within the Datapath controller that holds the Long instruction words. Load enable This is a single bit register in the Control component of each Index Register of the MacroSequencer's Datapath Controller. If it contains a `1', then the address component will be loaded by the next setindex operation. Instruction Set The set of operations for control of the MacroSequencers. Interface Load write offset Type of connections to the RAD5A4. They include the 5V TTL-level, 5V CMOS-level, and 3.3V CMOS-level. This is a single bit register in the Control component of each Index Register except the 1port Index Register of the MacroSequencer's Datapath Controller. It is only used in the 3-port Read Index Registers. In the Write Address and Write Offset Registers, it is forced to 0 on every clock cycle. When set to `1' in a 3-port Read Index Registers, it allows the Write Offset Address component to be loaded into that Index Register Address component by an indexmode operation. Internal Signals There is one internal signal. Constant comes from the LIW word. I/O Interface Type of I/O pin interface. J JTAG Scan Circuitry Logic Unit This circuitry supports a specific serial protocol documented in IEEE 1149.1a Boundary Scan Protocol document IEEE Standard Test Access Port and Boundary Scan Architecture. Each RAD5A4 MacroSequencer contains one logic unit. The shifter supports all bitwise logic operations on two operands. The operands are two words 16 bits of data, InBusA and InBusB. K loop counter 0, 1 See Counter0, Counter1 L M LIW = Long Instruction Word The RAD5A4 MacroSequencer is operationally controlled by the LIW Register. The LIW Register is defined in terms of the Long Instruction Word Format. The Long Instruction Word Format is 48 bits wide. It is composed of bit fields which initiate operations in the following internal units of the MacroSequencer: Multiplier-Accumulator, Adder, Shifter, Logic Unit, Input and Output Register Blocks, Index Registers, Data Memory Accesses, Program Counter, Return Stack, Send and Await status registers. MAC Multiplier-Accumulator Multiply-Accumulate MacroSequencer The RAD5A4 contains four MacroSequencers and a PLA. Each RAD5A4 MacroSequencer is composed of an Instruction Memory, Multiplier-Accumulator, Adder, Shifter, Logic Unit, Input and Output Register Blocks, Index Registers, Data Memory Accesses, Program Counter, Return Stack, Send and Await status registers. MIMD = Multiple Instruction Multiple Instruction Datapath MIMD systems possess multiple instruction processors which are capable of acting upon multiple data paths or streams in each increment of time. Infinite Technology Corporation Phone: 972-437-7800 March 1997 133 RAD5A4 Terms and Definitions Reconfigurable Arithmetic Datapath Minterms Pairs of inputs to the AND arrays in the Dual PLA arranged to allow all sixteen functions of the the two inputs. O Operations An assembly language command as defined by the MacroSequencer Assembly tables. When combined, these operations become LIWs. MSPair(nm), MSPair(mn) The private buses between the two MacroSequencers in a MacroSequencer pair. multiplicand, multiplier Output Register Block Common terms for operands of a multiply. This is made up of both OutRegA and OutRegB. Multiplier-Accumulator (MAC) Each RAD5A4 MacroSequencer contains one multiplier-accumulator. The multiplieraccumulator can perform one 8 bit by 16 bit multiply or multiply-accumulate per clock cycle. It can also perform a 16 by 16 bit multiply or multiply-accumulate every two clock cycles. The accumulator in the multiplieraccumulator is 48 bits, allowing up to 64K 16 by 16 multiply-accumulate operations and up to 16 Million 8 by 16 bits multiplyaccumulate operations before overflow. OutRegA This is a 16 bit register that holds results and feeds directly to the Output Buffer which is under control of the Output Enable circuitry. OutRegB This is a 16 bit register that holds temporary results in MacroSequencer(n) and feeds directly to the MSPair(nm) input of MacroSequencer(m). P Parallel processing Multiplier Data Conversion Each MacroSequencer's multiplier-accumulator uses an internal integer format which must be converted to standard integer formats. This is done by the MacroSequencer's Adder. This is the simultaneous operation of processing units ( ie: adder MAC Shifter, Control etc.). Passive Configuration Mode One of PGM0 or PGM1 are HIGH and the other is LOW. Configuration may not occur. Device outputs are held in a high-impedence state. N Normal Operating Mode The operating mode used for executing the LIW sequences. Configuration may not occur. PGM_a, PGM_b Terms used to refer to PGM0 and PGM1 since the two pins are identical and may be interchanged. NTSC NTSC stands for National Television System Committee. This committee proposed in 1953 an analog signal protocol which was adopted by law as the national television standard in the U.S., Canada, Mexico and Japan. This protocol was fully specified by the Society of Motion Picture and Television Engineers in 1994. Pipe A path for data within RAD5A4 elements. Pipeline structure Element consisting of pipes such as the Arithmetic Datapath, the MultiplierAccumulator, and the Adder. PLA Programmable Logic Array PLA I/O Buffers Element within the Dual PLA to hold data for the PLAI/O pins. Pointer Holds the address for a memory Positive Handshake 134 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Terms and Definitions Each RAD5A4 MacroSequencer contains 5 Index Registers. The four Index Registers are used for access of the 3-port Memory are known as the Smart Index Registers. Communication between the RAD5A4 and external circuitry used during configuration. Power On Reset Term used to describe the state of the RAD5A4 when it first receives power. Stack Preamble data word A Datapath Controller element that holds program counter values used with call and return operations. The first data word in each data packet loaded during configuration Stack pointer Programmable Logic Device Holds the stack location of the previous call operation. A device containing a programmable elements and logic arrays. State Machine Protected registers A logic element that changes value based on the previous value. These are registers that hold their previous contents in lieu of a specific instruction. Stream processing R Multiple streams of data are transformed by an algorithm and output in another set of streams. Run Command sent to the MacroSequencer Datapath Controller from either external pins or the Dual PLA control signals. The Run command allows the Datapath controller to operate under control of the LIW sequence. T Test Access Port (TAP) This is a collection of four pins TDI, TDO, TMS, TCK. These pins support a specific serial protocol documented in IEEE 1149.1a Boundary Scan Protocol document IEEE Standard Test Access Port and Boundary Scan Architecture. S Scan Instruction Register This is a serial register within the JTAG Boundary Scan Circuit which holds the internal scan system control state. Please see the IEEE 1149.1a Boundary Scan Protocol document IEEE Standard Test Access Port and Boundary Scan Architecture for further details. TAP Controller This is a serial protocol controller which controls the interface of the Test Access Port Pins. V SetSequence0, SetSequence2 Command sent to the MacroSequencer Datapath Controller from either external pins or the Dual PLA control signals. The Setsequence commands sets the program counter to either `0' or `2' to begin execution of a sequence of LIWs. VHDL Shifter This is a computer language developed by the U.S. Department of Defense. It is an acronym for the VHSIC Hardware Description Language. Currently the language specifies and models digital electronic systems. Each RAD5A4 MacroSequencer contains one shifter. The shifter supports all standard shift operations: logic shift left and right, rotate left and right and arithmetic shifts right. It operates on 16 bits of data from InBusC. Smart Index Register Infinite Technology Corporation Phone: 972-437-7800 March 1997 135 RAD5A4 Terms and Definitions Reconfigurable Arithmetic Datapath 0-9 1-port Memory The 1-port Memory is a 32 by 16 bit RAM. It is capable of one memory access per clock cycle. This access may either be a read or a write operation. See also Data Memory, Index Register and MacroSequencer entries. 3-port Memory The 3-port Memory is a 16 by 16 bit 3-port RAM. It supports 2 read and one write operation in each clock cycle. Note that if more than one of these operations address the same memory location, the results are not guaranteed. See also Data Memory, Index Register and MacroSequencer entries. 32/16 bit configuration bit MacroSequencer programmable bit that sets the Adder for either 32-bit operation or 16-bit operation. 136 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Table of Signals Appendix Table of Signal Names Signal Name No. of Bits From To Referenced in these Figures Figure # Adder Status Bits 4 MSn Arithmetic Datapath Adder MSn Arithmetic Controller, Datapath Shifter MacroSequencer, MacroSequencer Datapath Block Diagram, Adder, Shifter, Datapath Controller 9, 10, 14, 15, 22 BUS4IN 16 BUS4IN[15:0] Bus4 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, Dual PLA Block Diagram, PLA Input Selector 2, 8, 23, 24 bus0 16 MS0 MS0, MS1, MS2, MS3 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers, I/O Interface 2, 8, 9, 10, 11, 21 bus2 16 MS1 MS0, MS1, MS2, MS3 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers, I/O Interface 2, 8, 9, 10, 11, 21 bus3 16 MS2 MS0, MS1, MS2, MS3 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers, I/O Interface 2, 8, 9, 10, 11, 21 bus4 16 MS3 MS0, MS1, MS2, MS3 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers 2, 8, 9, 10, 11 Control Bus 32 MS0, MS1, MS2, MS3, Dual PLA, MSn Direct Control Pins MS0, MS1, MS2, MS3, Dual PLA, MSn Direct Control Pins Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram 2, 8 CtrlReg 8 PLA0 Control Registers PLA0, PLA1 Dual PLA Block Diagram, PLA Input Selector, CtrlReg Register 23, 24, 33, Infinite Technology Corporation Phone: 972-437-7800 March 1997 137 RAD5A4 Table of Signals Signal Name Reconfigurable Arithmetic Datapath No. of Bits From To Referenced in these Figures Figure # C0 8 Control OR Control Registers Dual PLA Block Diagram, Control OR, CtrlReg Register 23, 31, 33 C1 8 Output OR Output Registers Dual PLA Block Diagram Output OR, OutReg Register, PLAI/O Buffers 23, 34, 36, 37 Constant 16 MSn Datapath Controller MSn Input Register MacroSequencer Datapath Block Diagram, Input Registers, 10, 11 FO0 8 Fixed OR Array 0 Control OR 0 Dual PLA Block Diagram, Fixed OR 0, Control OR 23, 27, 31 FO1 14 Fixed OR Array 1 Output OR 1 Dual PLA Block Diagram, Fixed OR 1, Control OR, Output OR 23, 29, 31, 34 InBusA 16 MSn Input Selector MSn MAC, Adder, Logic Unit MacroSequencer Datapath Block Diagram, Input Selector, 16 by 8 Multiplier-Accumulator, Adder, Logic Unit 10, 12, 13, 14, 16 InBusB 16 MSn Input Selector MSn MAC, Adder, Logic Unit MacroSequencer Datapath Block Diagram, Input Selector, 16 by 8 Multiplier-Accumulator, Adder, Logic Unit 10, 12, 13, 14, 16 InBusC 16 MSn Input Selector MSn Shifter MacroSequencer Datapath Block Diagram, Input Selector, Shifter, 10, 12, 15 InRegA 16 MSn Input Register MSn Input Selector MacroSequencer Datapath Block Diagram, Input Registers, Input Selector, 10, 11, 12 InRegB 16 MSn Input Register MSn Input Selector, MSn Output Selector MacroSequencer Datapath Block Diagram, Input Registers, Input Selector, Output Selector 10, 11, 12, 20 LIW Control Bits 48 16 MSn Arithmetic Datapath MSn Input Selector, MAC MacroSequencer mem0 MSn Arithmetic Controller MSn 1-port Memory MacroSequencer Datapath Block Diagram, Input Selector, 16 by 8 Multiplier-Accumulator, 1-Port Memory 10, 12, 13, 17 mem1 16 MSn 3-port Memory MSn Input Selector MacroSequencer Datapath Block Diagram, Input Selector, 3-Port Memory 10, 12, 18 mem2 16 MSn 3-port Memory MSn Input Selector MacroSequencer Datapath Block Diagram, Input Selector, 3-Port Memory 10, 12, 18 MultOutA, MultOutB 32 MSn MAC MSn Adder MacroSequencer Datapath Block Diagram, 16 by 8 MultiplierAccumulator, Adder, 10, 13, 14 MS0AWAIT 1 9 1 MacroSequencer 9 MS2AWAIT 1 MacroSequencer 9 MS3AWAIT 1 MS0AWAIT, Dual PLA MS1AWAIT, Dual PLA MS2AWAIT, Dual PLA MS3AWAIT, Dual PLA MacroSequencer MS1AWAIT MS0 Datapath Controller MS1 Datapath Controller MS2 Datapath Controller MS3 Datapath Controller MacroSequencer 9 138 March 1997 9 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Signal Name No. of Bits From Table of Signals To Referenced in these Figures Figure # MS0CTRL 2 MS0 Datapath Controller MS0CTRL MacroSequencer, Datapath Controller 22 MS1CTRL 2 MS1 Datapath Controller MS1CTRL MacroSequencer, Datapath Controller 22 MS2CTRL 2 MS2 Datapath Controller MS2CTRL MacroSequencer, Datapath Controller 22 MS3CTRL 2 MS3 Datapath Controller MS3CTRL MacroSequencer, Datapath Controller 22 MS0I/O 16 MS0I/O[15:0], MS0 OutRegA MS0I/O[15:0], bus0 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Output Selector, I/O Interface 2, 8, 9, 10, 20, 21 MS1I/O 16 MS1I/O[15:0], MS1 OutRegA MS1I/O[15:0], bus0 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Output Selector, I/O Interface 2, 8, 9, 10, 20, 21 MS2I/O 16 MS2I/O[15:0], MS2 OutRegA MS2I/O[15:0], bus0 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Output Selector, I/O Interface 2, 8, 9, 10, 20, 21 MS3I/O 16 MS3I/O[15:0], MS3 OutRegA MS3I/O[15:0], bus0 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Output Selector, I/O Interface 2, 8, 9, 10, 20, 21 MS0OE 1 MS0OE MacroSequencer 9 MS1OE 1 MS1OE MacroSequencer 9 MS2OE 1 MS2OE MacroSequencer 9 MS3OE 1 MS3OE MS0 Datapath Controller MS1 Datapath Controller MS2 Datapath Controller MS3 Datapath Controller MacroSequencer 9 Infinite Technology Corporation Phone: 972-437-7800 March 1997 139 RAD5A4 Table of Signals Signal Name Reconfigurable Arithmetic Datapath No. of Bits MS0SEND 1 MS1SEND 1 MS2SEND 1 MS3SEND 1 MSPair01 From To 16 MS0 Datapath Controller MS1 Datapath Controller MS2 Datapath Controller MS3 Datapath Controller MS0 OutRegB MS0SEND, Dual PLA MS1SEND, Dual PLA MS2SEND, Dual PLA MS3AWAIT, Dual PLA MS1 Input Register MSPair10 16 MS1 OutRegB MSPair23 16 MSPair32 Referenced in these Figures Figure # MacroSequencer 9 MacroSequencer 9 MacroSequencer 9 MacroSequencer 9 Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers 8, 9, 10, 11 MS0 Input Register Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers 8, 9, 10, 11 MS2 OutRegB MS3 Input Register Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers 8, 9, 10, 11 16 MS3 OutRegB MS2 Input Register Simplified RAD5A4 Control and Data Flow Diagram, MacroSequencer, MacroSequencer Datapath Block Diagram, Input Registers 8, 9, 10, 11 mt 64 Minterm Generators AND Arrays Dual PLA Block Diagram, Product Terms 23, 25 oepla[n] 1 Dual PLA MSn MacroSequencer, I/O Interface, Dual PLA Block Diagram 9, 21, 23 OutCom 8 Output OR PLAI/O Buffers Dual PLA Block Diagram OutReg 8 PLA1 Output Registers PLA0, PLA1 Dual PLA Block Diagram, PLA Input Selector, OutReg Register 23, 24, 36 OutRegA 16 MSn Output Selector MSn I/O Interface, 1-port memory, Input Selector MacroSequencer Datapath Block Diagram, Input Selector, 1-Port Memory, Output Selector, I/O Interface 10, 12, 17, 20, 21 OutRegB 16 MSn Output Selector MSn MSPair(nm), Input Selector, 3port memory MacroSequencer Datapath Block Diagram, Input Selector, 16 by 8 Multiplier-Accumulator, 3-Port Memory, Output Selector 10, 13, 18, 20 140 March 1997 23 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Signal Name No. of Bits From Table of Signals To Referenced in these Figures Figure # PLACtrl0 2 Dual PLA MS0 Datapath Controller MacroSequencer, Datapath Controller, Dual PLA Block Diagram 9, 22, 23 PLACtrl1 2 Dual PLA MS1 Datapath Controller MacroSequencer, Datapath Controller, Dual PLA Block Diagram 9, 22, 23 PLACtrl2 2 Dual PLA MS2 Datapath Controller MacroSequencer, Datapath Controller, Dual PLA Block Diagram 9, 22, 23 PLACtrl3 2 Dual PLA MS3 Datapath Controller MacroSequencer, Datapath Controller, Dual PLA Block Diagram 9, 22, 23 PLAI/O 8 PLAI/O[7:0], PLA0, PLA1 PLAI/O[7:0], PLA1 Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, Dual PLA Block Diagram, PLA Input Selector, PLAI/O Buffers 2, 8, 23, 24, 37 PLAIN 8 PLA1 PLAIN[7:0] Simplified RAD5A4 Operational Block Diagram, Simplified RAD5A4 Control and Data Flow Diagram, Dual PLA Block Diagram, PLA Input Selector 2, 8, 23, 24 PT0 32 AND Array 0 Fixed OR 0 Dual PLA Block Diagram, Product Terms, Fixed OR 0 23, 25, 27 PT1 32 AND Array 1 Fixed OR 1 Dual PLA Block Diagram, Product Terms, Fixed OR 1 23, 25, 29 Output Selector 16 Adder, Shifter, Logic Unit Output Selector Adder, Shifter, Logic Unit 14, 15, 16 Infinite Technology Corporation Phone: 972-437-7800 March 1997 141 RAD5A4 LIW Reconfigurable Arithmetic Datapath MacroSequencer Long Instruction Word The RAD5A4 MacroSequencer is composed of elements within the datapath that are controlled by Long Instruction Word (LIW) bits. LIWs are programmed into MacroSequencer LIW memory during device configuration. The Datapath Controller executes the LIWs which control the arithmetic datapath. The LIW bits are used to control the MacroSequencer Arithmetic Datapath. The LIW bit settings are changed according to the programmed operations. The assembly operations use one of seven multiplexers for selecting the source parameters. The LIW settings that control the multiplexer selections and the assembly operation LIW settings are presented in this section. Multiplexers These seven (7) multiplexers in the MacroSequencer Arithmetic Datapath are controlled by different operations resulting in conflicts. Only one source or or destination may be assigned to these seven multiplexers per LIW. Input Registers * InRegA * InRegB Input Selector * InBusA * InBusB * InBusC Output Selector * OutRegA * OutRegB The LIWs that control these multiplexers are shared among operations. For example, when the inrega input source parameter is selected for an add1 operation, the InBusA multiplexer control bits LIW[9:8] are set. InBusA's resources are committed, and other operations cannot select a different InBusA related input signal in the same instruction word. 142 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath LIW The following tables specify the LIW settings for each of the seven MacroSequencer multiplexers: InRegA <src> LIW[4:2] hold bus4 constant (LIW[43:28]) bus0 bus1 bus2 bus3 pair table LIW-1 000 (default) 001 010 011 100 101 110 111 InRegB <src> LIW[7:5] hold bus4 constant (LIW[43:28]) bus0 bus1 bus2 bus3 pair table LIW-2 000 (default) 001 010 011 100 101 110 111 The InBusA signal is used by the multiplier, adder, and logic unit which are controlled by these operations: mult1, add1, sub1, and logic. InBusA <src> LIW[9:8] inrega outrega outregb mem1 00 (default) 01 10 11 table LIW-3 Infinite Technology Corporation Phone: 972-437-7800 March 1997 143 RAD5A4 LIW Reconfigurable Arithmetic Datapath The InBusB signal is used by the multiplier, adder, and logic unit which are controlled by these operations: mult1, add1, sub1, and logic. InBusB <src> LIW[12:10] 0 mem0 inregb outrega outregb mem2 000 (default) 001 100 101 110 111 table LIW-4 InBusC <src> LIW[14] outrega inrega 0 (default) 1 table LIW-5 The OutRegA signal may be selected as a destination for results from the logic unit, shifter and adder. The destinations for these units are controlled by the: add2, sub2, shift, and logic operations. When these operations select the destination to be outrega, LIW[18:17] are affected as follows: OutRegA <src> LIW[18:17] hold logic shifter adder 00 (default) 01 10 11 table LIW-6 144 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath LIW The OutRegB signal may be selected as a destination for the InRegB input register (in operation), MSnIO[15:0] pins (pins operation), adder, shifter, and logic unit. The destinations for these units are controlled by the: move, in, add2, sub2, shift, and logic operations. When these operations select the destination to be outregb, LIW[21:19] are affected as follows: OutRegB Source / operation LIW[21:19] hold InRegB pins logic shifter adder 000 (default) 001 100 101 x10 x11 table LIW-7 Assembly Operations LIW settings for each MacroSequencer assembler operation are listed in the tables that follow. Some LIW bits are set by only one operation; some are shared by operations and are set depending on the operation parameter selection. nop The nop operation is the default setting and sets all 48 LIW bits: LIW[47:0] in binary: 1001 0001 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 LIW[47:0] in hexadecimal: 0x9100,0000,1000 in <src>,<dest> If <dest> = inrega, LIW[4:2] bits are set according to the InRegA table to select the source. If <dest> = inregb, LIW[7:5] bits are set according to the InRegB table to select the source. in pins, outregb This operation sets LIW[21:19] to `100' in accordance with the OutRegB table. Infinite Technology Corporation Phone: 972-437-7800 March 1997 145 RAD5A4 LIW Reconfigurable Arithmetic Datapath mult1 <srca>,<srcb> The Multiplier source parameter multiplexers are controlled by LIW[47,44]. If a source is selected from the InBusA and/or InBusB signals, then LIW[9:8] and/or LIW[12:10] are also set in accordance with the InBusA and InBusB tables. <srca> LIW[47,44] InBusA multiplexer selection (inrega, outrega, outregb, mem1) mem0 hold table LIW-8 <srcb> 00 01 or 10 11 (default) LIW[47,44] 00 or 01 InBusB multiplexer selection (0, mem0, inregb, outrega, outregb, mem2) outregb 10 hold 11 (default) table LIW-9 The multiplier input multiplexers are controlled with the same two LIW[47,44] bits. Therefore, the LIW control bits for the two inputs must have the same values. Operand A is multiplied by the most significant byte of operand B. The least significant byte of operand B is stored for possible use in a mult1 hold operation on the next cycle. mult1 hold LIW[47,44] is set to `11'. This forces the previous cycle's operand A to be used with the least significant byte of the last cycle's operand B. mult3 <weight>, <enable> The mult3 operation sets LIW[23] to `1'; otherwise LIW[23] is `0'. <weight> low high LIW[40] 0 (default) 1 table LIW-10 <enable> LIW[43] clr 0 (default) acc 1 table LIW-11 add1 <oper1>, <oper2> An add1 operation other than an add1 mult sets LIW[15,13] to [0,0]. LIW[9:8] bits are set by the <oper1> as shown in the InBusA table LIW-3. 146 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath LIW LIW[12:10] bits are set by the <oper2> as shown in the InBusB table LIW-4. add1 mult, <pos> An add1 mult operation sets LIW[15] to `1'; otherwise LIW[15] is `0'. <pos> LIW[42:41] low norm mid high 00 01 10 11 table LIW-12 add2 [<dest1> [, <dest2>]] The add2 operation sets the carry in bit LIW[16] to `0'. LIW[18:17] bits are set to [11] when the <dest1> or <dest2> is outrega for the add2 operation. LIW[21:19] bits are set to [x11] when the <dest1> or <dest2> is outregb for the add2 operation. sub1 <srca>, <srcb> The sub1 operation sets LIW[15,13] to [0,1]. LIW[9:8] bits are set by the <oper1> as shown in the InBusA table LIW-3. LIW[12:10] bits are set by the <oper2> as shown in the InBusB table LIW-4. Infinite Technology Corporation Phone: 972-437-7800 March 1997 147 RAD5A4 LIW Reconfigurable Arithmetic Datapath sub2 [<dest1> [, <dest2>]] The sub2 operation sets the carry in bit LIW[16] to `1'. LIW[18:17] bits are set to [11] when the <dest1> or <dest2> is outrega for the sub2 operation. LIW[21:19] bits are set to [x11] when the <dest1> or <dest2> is outregb for the sub2 operation. shift <src>, <type>,<length>, <dest1>[, <dest2>] shift <src>, normal, <dest1>[, <dest2>] The shift operation parameters set LIW[14, 34:32, 38:35, 18:17, and/or 21:19] bits as listed here: LIW[14] is set by the <src> parameter in accordance with the InBusC table <type> LIW[34:32] <length> in LIW[38:35] logicright logicleft normal arithmetic rotate 001 010 011 101 110 table LIW-13 0-15 or 0x0-0xf 0-15 or 0x0-0xf 0001 0-15 or 0x0-0xf 0-15 or 0x0-0xf LIW[18:17] bits are set to [10] when the <dest1> or <dest2> is outrega for the shift operation. LIW[21:19] bits are set to [x10] when the <dest1> or <dest2> is outregb for the shift operation. 148 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath LIW logic <oper>, <dest1>, [<dest2>] logic <oper>, <srca>, dest1>, [<dest2>] logic <oper>, <srcb>, dest1>, [<dest2>] logic <oper>, <srca>, <srcb>, dest1>, [<dest2>] The logic operation parameters set LIW[14, 34:32, 38:35, 18:17, and/or 21:19] bits as listed here: <oper> LIW[31:28] 0 1 nota a notb b nor notab anotb xor nand and xnor notaorb aornotb or 0000 1111 0011 1100 0101 1010 0001 0010 0100 0110 0111 1000 1001 1011 1101 1110 table LIW-14 LIW[9:8] bits are set by the <srca> as shown in the InBusA table LIW-3. LIW[12:10] bits are set by the <srcb> as shown in the InBusB table LIW-4. LIW[18:17] bits are set to [01] when the <dest1> or <dest2> is outrega for the logic operation. LIW[21:19] bits are set to [101] when the <dest1> or <dest2> is outregb for the logic operation. When neither operand <srca> or <srcb> is needed there are no constraints on LIW[12:8]. When only <srca> is needed there are no constraints on LIW[12:10]. When only <srcb> is needed, there are no constraints on LIW[9:8] Infinite Technology Corporation Phone: 972-437-7800 March 1997 149 RAD5A4 LIW Reconfigurable Arithmetic Datapath oneport <oper> <oper> LIW[1:0] write read default not allowed 10 01 00 11 table LIW-15 memwrite, memread1, memread2 The memwrite operation sets LIW[22] to `1'. The memread1 operation sets LIW[45] to `1'. The memread2 operation sets LIW[46] to `1'. move - moves the contents of InRegB to OutRegB LIW[21:19] is set to `001'. 150 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath LIW Datapath Controller Operations Operation indexmode The datapath controller operations determine the values for LIW[27:24]. The Parameters determine LIW[39:28]. LIW Parameters LIW Arguments LIW [27:24] [39:28] bits 0001 <m0>: none, reset <mw>: none, resetoffset, resetall <m1>: none, reset, align <m2>: none reset, align send await setcounter0 <value> 0010 0011 0100 no arguments no arguments <value>: 0-31 or 0x0-0x1f setcounter1 <value> 0101 <value>: 0-31 or 0x0-0x1f setindex <value> 0110 <value>: 0-31 or 0x0-0x1f setindex 0110 <valuew>: 0-15 or 0x0-0xf <value1>: 0-15 or 0x0-0xf <value2>: 0-15 or 0x0-0xf indexdirect 0111 [28] [31:30] [33:32] [35:34] [39:36] = 0 none none [32:28], [39:33] = 0 [32:28], [39:33] = 0 [32:28], [39:33] = 0 [39:36] [35:32] [31:28] <d0>: none, inc, dec <dw>: none, inc, dec, rev <d1>: none, inc, dec, rev <d2>: none, inc, dec, rev <index>: readwrite0, write, read1, read2, all3port [29:28] [31:30] [33:32] [35:34] [38:36] [32:28], [39:33] = 0 [32:28], [39:33] = 0 none [32:28], [39:33] = 0 [32:28], [39:33] = 0 [32:28], [39:33] = 0 [32:28], [39:33] = 0 [32:28], [39:33] = 0 jump <address> 1000 0-31 or 0x0-0x1f call <address> 1001 0-31 or 0x0-0x1f return jumpequal <address> 1010 1011 no arguments 0-31 or 0x0-0x1f jumpoverflow <address> 1100 0-31 or 0x0-0x1f jumpsign <address> 1101 0-31 or 0x0-0x1f jumpcounter0 <address> 1110 0-31 or 0x0-0x1f jumpcounter1 <address> 1111 0-31 or 0x0-0x1f none reset align resetoffset resetall none inc dec rev readwrite0 write read1 read2 all3port 0 01 10 01 01 00 01 10 11 000 001 010 011 100 table LIW-16 Infinite Technology Corporation Phone: 972-437-7800 March 1997 151 RAD5A4 LIW Reconfigurable Arithmetic Datapath LIW Setting Summary The tables that follow summarize which MacroSequencer functional units affect which LIW bits. LIW Operational Unit Definition Continued Operational Unit 47 46 45 44 43 42 41 40 39 38 37 36 1-port memory access 1-port index register X X X operation 3-port memory access X X 3-port index register operation set index mode index directions X X X Input Bus Mux A & B Input Mux A & B Adder Pipe 1 Adder Pipe 2 Output Mux 0 & 1 Multiplier pipe 1 X X Multiplier pipe 2(Acc) X X X X Sequence Controller Constant X X X X X X X X logic unit control shifter X X X Operational Unit 1-port memory access 1-port index register operation 3-port memory access 3-port index register operation set index mode index directions Input Bus Mux A & B Input Mux A & B Adder Pipe 1 Adder Pipe 2 Output Mux 0 & 1 Multiplier pipe 1 Multiplier pipe 2(Acc) Sequence Controller Constant logic unit control 152 LIW Operational Unit Definition 35 34 33 32 31 30 29 X X X X X X X X X X X X X X X X X X X X X March 1997 28 X X X X X X 27 26 25 24 X X X X Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath shifter Infinite Technology Corporation Phone: 972-437-7800 X X LIW X X March 1997 153 RAD5A4 LIW Reconfigurable Arithmetic Datapath LIW Operational Field Definition Continued Operational Fields 1-port memory access 1-port index register operation 3-port memory access 3-port index register operation Input Bus Mux A & B to inrega,b Input Mux A, B & C Adder Pipe 1 Adder Pipe 2 Output Mux 0 & 1 to outrega,b Multiplier pipe 1 Multiplier pipe 2(Acc) Sequence Controller Constant logic unit control shifter 23 22 21 20 19 18 17 16 15 14 13 12 X X X X X X X X X X X X LIW Operational Field Definition Operational Fields 11 10 1-port memory access 1-port index register operation 3-port memory access 3-port index register operation Input Bus Mux A & B to inrega,b Input Mux A, B & C Adder Pipe 1 Adder Pipe 2 Output Mux 0 & 1 to outrega,b Multiplier pipe 1 Multiplier pipe 2(Acc) Sequence Controller Constant logic unit control shifter X X 154 9 8 7 X X X X 6 X 5 X 4 X 3 X 2 1 0 X X X X March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath JTAG Scan Circuitry JTAG Scan Circuitry The RAD5A4 JTAG Scan circuitry complies with the IEEE standard 1149.1a Boundary Scan Protocol providing a reasonable test interface to a complex system. The active logic pins not involved in the protocol itself are accessible via the JTAG Scan circuitry. Many registers in each MacroSequencer are also accessible. The JTAG Scan circuitry supports production testing of the printed circuit boards, remote site diagnosis of system conditions and the development of applications software. The IEEE 1149.1a Boundary Scan Protocol provides a low pin count method for testing systems specified in the IEEE Standard Test Access Port and Boundary Scan Architecture, (c) 1993, Institute of Electrical and Electronics Engineers, Inc., New York, ISBN 1-55937-350-4. The Boundary Scan Protocol uses a serial protocol involving four special purpose pins: TDI, TDO, TCK, TMS, which are known as the TAP (Test Access Port) pins. The TAP pins allow the state of all active logic signals to be examined and for the state of many registers in the four MacroSequencers to be examined. RAD5A4 Scan Circuitry Components and Features The primary components of the scan circuitry are the TAP Controller, the ID Register, the BYPASS Register, the Scan Instruction Register, the Boundary Scan Path and the four MacroSequencer Scan Paths. The TAP Controller is documented in the IEEE standard 1149.1a as referenced. The ID Register identifies which component is present. The BYPASS Register is a single register which is active when the Scan Instruction Register contains the BYPASS instruction and the TAP Controller is in data transfer mode. The BYPASS Register captures the TDI pin input on the rising edge of TCK. The TDO output signal is the state of the BYPASS register. Note that the TDO pin changes state after the falling edge of TCK. The Scan Instruction Register provides overall control for the scan circuitry. It has a five-bit code which is discussed later in this chapter. The Boundary Scan Path is a collection of registers connected to form a shift register which is capable of capturing and (for most pins) asserting the state of the pins and the directionality of the bi-directional I/O pins. The four MacroSequencer Scan Paths allow the state of many registers of each MacroSequencer to be examined and potentially modified. The Infinite Technology Corporation Phone: 972-437-7800 March 1997 155 RAD5A4 JTAG Scan Circuitry Reconfigurable Arithmetic Datapath MacroSequencer Scan Path circuitry can be made to feed back the shifted data pattern from the MacroSequencer, creating a circular shift register network from each MacroSequencer Scan Path. This supports a simple observe-only emulator interface. While scanning the contents of any scan path, none of the five clock pins should change state. The MSnCLK input must be maintained LOW when testing the MacroSequencern scan path. Boundary Scan Path Map In the following tables, the bus signals are denoted Bus[a:b] where Bus[a] is the first bit read out, and the last bit read out is Bus[b]. Thus, the first bit scanned in is Bus[a] and the last bit scanned in is Bus[b]. Pin types include Input, Output, I/O, and Clock. A dash `-' is used to denote no entry or not applicable. The following terms in the table include: * * 156 Observe Only signals are signals which cannot be altered by the Boundary Scan Registers but can be observed. The Observe and Assert signals can not only be observed, but may also be altered by the Boundary Scan Registers. March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath JTAG Scan Circuitry Boundary Scan Path Map Scan Signal Bits[0:137] 0,1 2 3 4 5 6 - 21 22 Signal Name and Signal Source Pin Internal MS0CTRL[0:1] MS0OE MS0CLK MS0SEND MS0AWAIT MS0I/O[0:15] oems0 Scan Scan Cell Function Cell Observe Observe Type and Assert Only Input X Input X Clock X Output X Output X I/O X Input X - 23,24 25 26 27 28 29 - 44 45 MS1CTRL[0:1] MS1OE MS1CLK MS1SEND MS1AWAIT MS1I/O[0:15] - oems1 Input Input Clock Output Output I/O Input X X X X X X X - - oems3 Input X - MS3I/O[15:0] MS3AWAIT MS3SEND MS3CLK MS3OE MS3CTRL[1:0] - oems2 I/O Output Output Clock Input Input Input X X X X X X X - 46 47 - 62 63 64 65 66 67,68 69 Comments Output enable for MS0I/O[15:0] Output enable for MS1I/O[15:0] Output enable for MS3I/O[15:0] Output enable for MS2I/O[15:0] 70 - 85 MS2I/O[15:0] I/O X 86 MS2AWAIT Output X 87 MS2SEND Output X 88 MS2CLK Clock X 89 MS2OE Input X 90,91 MS2CTRL[1:0] Input X Note: XXX[a:b] means XXX[a] is scanned out first, and XXX[b] is scanned out last. For all output enable signals in Internal column: `1' = output enabled, `0' = output disabled. table JTAG-1 Infinite Technology Corporation Phone: 972-437-7800 March 1997 157 RAD5A4 JTAG Scan Circuitry Reconfigurable Arithmetic Datapath Boundary Scan Path Map, Continued Scan Signal Bits[0:137] 92 93 94 95 96 97 98 - 113 114 115 Signal Name and Signal Source Pin Internal PLACLK PACK packoe PRDY PGM0 PGM1 BUS4IN[0:15] PLAI/O[7] plaoe[7] Scan Scan Cell Function Cell Observe Observe Type and Assert Only Input X Output X Input X Input X Input X Input X Input X I/O X Input X - 116 117 PLAI/O[6] - plaoe[6] I/O Input X X - 118 119 PLAI/O[5] - plaoe[5] I/O Input X X - 120 121 PLAI/O[4] - plaoe[4] I/O Input X X - 122 123 PLAI/O[3] - plaoe[3] I/O Input X X - 124 125 PLAI/O[2] - plaoe[2] I/O Input X X - 126 127 PLAI/O[1] - plaoe[1] I/O Input X X - 128 129 PLAI/O[0] - plaoe[0] I/O Input X X - Comments Output enable for PACK Output enable for PLAI/O[7] Output enable for PLAI/O[6] Output enable for PLAI/O[5] Output enable for PLAI/O[4] Output enable for PLAI/O[3] Output enable for PLAI/O[2] Output enable for PLAI/O[1] Output enable for PLAI/O[0] 130 - 137 PLAIN[7:0] Input X Note: XXX[a:b] means XXX[a] is scanned out first, and XXX[b] is scanned out last. For all output enable signals in Internal column: `1' = output enabled, `0' = output disabled. table JTAG-1, continued 158 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath JTAG Scan Circuitry Scan Map within each MacroSequencer(n) Scan Signal Bits [0:190] Signal Name 0-15 16-31 32-34 InRegA[0:15] InRegB[0:15] 1-port Index Ctrl[0:2] 35-39 40-43 1-port Index Adr[4:0] 3-port Read 2 Index Ctrl[0:3] 44-47 48-51 3-port Read 2 Index Adr[3:0] 3-port Read 1 Index Ctrl[0:3] 52-55 56-59 3-port Read 1 Index Adr[3:0] 3-port Write Index Ctrl[0:3] 60-63 64-67 3-port Write Index Adr[3:0] 3-port Write Offset Ctrl[0:3] 68-71 72-80 81-105 106-112 113-119 120-124 125-126 127-131 132-136 137-141 142-146 147-148 149-153 154-158 159-174 175-190 3-port Write Offset Adr[3:0] LIW[7:2, 46:45, 22] LIW[1:0, 14:8, 39:24] LIW[47,44:40,23] LIW[16:15,21:17] PC[4:0] Stack pointer [1:0] Stack wd3[4:0] Stack wd2[0:4] Stack wd1[4:0] Stack wd0[0:4] PLACtrln[1:0] Counter1 [4:0] Counter0 [4:0] OutRegB[15:0] OutRegA[15:0] Comments Input Registers Input Registers Datapath Controller: I1P Control Register Ctrl[0]=>lden, Ctrl[1] => count_up, Ctrl[2] => count_down Datapath Controller: I1P Address Register Datapath Controller: I3PR2 Control Register Ctrl[0] => lden, Ctrl[1] => ldwo, Ctrl[2] => count_up, Ctrl[3] => count_down Datapath Controller: I3PR2 Address Register Datapath Controller: I3PR1 Control Register Ctrl[0] => lden, Ctrl[1] => ldwo, Ctrl[2] => count_up, Ctrl[3] => count_down Datapath Controller: I3PR1 Address Register Datapath Controller: I3PW Control Register Ctrl[0] => lden, Ctrl[1] => ldwo, Ctrl[2] => count_up, Ctrl[3] => count_down See note 3. Datapath Controller: I3PW Address Register Datapath Controller: I3PWO Control Register Ctrl[0] => lden, Ctrl[1] => ldwo, Ctrl [2] => count_up, Ctrl[3] => count_down See note 3. Datapath Controller: I3PWO Address Register Datapath Controller: LIW Register Datapath Controller: LIW Register Datapath Controller: LIW Register Datapath Controller: LIW Register Datapath Controller: Program Counter Datapath Controller: Stack Pointer Registers Datapath Controller: Stack Word 3 Datapath Controller: Stack Word 2 Datapath Controller: Stack Word 1 Datapath Controller: Stack Word 0 Datapath Controller: PLACtrl Registers Datapath Controller: Loop Counter 1 Datapath Controller: Loop Counter 0 Output Selector: Registers Output Selector: Registers Note 1: XXX[a:b] means XXX[a] is scanned out first, and XXX[b] is scanned out last. Note 2: lden = load enable, ldwo = load write offset. Note 3: During normal operation, Ctrl[1] (ldwo) of the 3-port Write Index Control and the 3-port Write Offset Control is set to `0' on each MSnCLK clock cycle. Do not put `1' into Ctrl[1] of these registers using scan and then clock the relevent MSnCLK. table JTAG-2 Infinite Technology Corporation Phone: 972-437-7800 March 1997 159 RAD5A4 JTAG Scan Circuitry Reconfigurable Arithmetic Datapath Instruction Register The Instruction Register (INSTREG) contains 5 bit cells, labeled INSTREG[4:0] where INSTREG[4] is the most significant bit. INSTREG[0], the least significant bit, is the first bit scanned in and the first bit scanned out. The scan instruction codes used in the RAD5A4 are listed here: Scan Instruction Code Definition Selection Name Boundary Mode Bit Number Observe Observe /Assert Observe/ Assert/ 4 3 2 1 0 0 1 0 0 0 1 1 0 X 1 0 0 1 0 0 X X 1 0 1 0 0 X X X 1 X 0 Extest Normal Input Pins - Output Pins - - INTEST 0 1 0 0 0 0 0 Intest Input Pins - SAMPLE/PRELOAD 0 1 0 1 1 Sample/ Preload - - Observe Boundary 0 1 0 1 0 Normal Output Pins (High Z) All Input and Output Pins All Input and Output Pins - - - EXTEST BYPASS Default Codings Restore ID Register (IDCODE) 0 1 0 0 1 Normal CLAMP 0 1 1 0 0 Clamp HIGHZ 0 1 1 0 1 HighZ MS0 with TDI input 1 0 0 0 0 Clamp MS0 MS0 with Wraparound 1 0 1 0 0 Clamp MS1 with TDI input 1 0 0 0 1 Clamp MS1 MS1 with Wraparound 1 0 1 0 1 Clamp MS2 with TDI input 1 0 0 1 0 Clamp MS2 MS2 with Wraparound 1 0 1 1 0 Clamp MS3 with TDI input 1 0 0 1 1 Clamp MS3 MS3 with Wraparound 1 0 1 1 1 Clamp Notes: * The instruction register is asynchronously forced to IDCODE during Power On Reset. * Boundary Modes are defined in the IEEE standard 1149.1a Scan Document. * MS0 represents MacroSequencer 0, MS1 represents MacroSequencer 1, MS2 represents MacroSequencer 2, and MS3 represents MacroSequencer 3. table JTAG-3 160 March 1997 MS0 MS1 MS2 MS3 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath JTAG Scan Circuitry Device Identification Register Specification The Device Identification Register (IDREG) contains 32 bit cells, labeled IDREG[0:31] where IDREG[31] is the most significant bit, and IDREG[0] is the first bit scanned in and scanned out. IDREG[0] is `1'. IDREG[31:28] contains the design version number which is `0000' for initial design silicon and will be incremented for any later redesigns. For example,the first redesign silicon would contain the code `0001'. IDREG[27:12] contains the Part Number. The coding used in the RAD5A4 is 0000,0000,0000,000a where "a" = 0 for CMOS-compatible interface, and "a" = 1 for TTL-compatible interface. IDREG[11:1] contains the Manufacturer Number. The coding initially used in the RAD5A4 is 000,0111,1111. Infinite Technology Corporation Phone: 972-437-7800 March 1997 161 RAD5A4 Reconfigurable Arithmetic Datapath 162 March 1997 Infinite Technology Corporation Phone: 972-437-7800 RAD5A4 Reconfigurable Arithmetic Datapath Infinite Technology Corporation 2425 N. Central Expressway, Suite 323 Richardson, TX 75080 Phone: Fax: 972-437-7800 972-437-7810 INFINITE TECHNOLOGY CORPORATION reserves the right to make changes to the products contained in this data book in order to improve the design or performance and to supply the best possible products. Infinite Technology Corporation assumes no responsibility for the use of any circuits shown in this data book, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any device shown in this data book are for illustration only and Infinite Technology Corporation makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. Infinite Technology Corporation Phone: 972-437-7800 March 1997 163