HEF4014BT,652 - NEXPERIA - Datasheet.Global

HEF4014B

8-bit static shift register

Rev. 10 — 17 October 2018 Product data sheet

1. General description

The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight

synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a synchronous

parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP) and buffered parallel

outputs from the last three stages (Q5 to Q7).

Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH transition of CP.

Each register stage is of a D-type master-slave flip-flop type. When PE is HIGH, data is loaded into

the register from D0 to D7 on the LOW-to-HIGH transition of CP. When PE is LOW, data is shifted

to the first position from DS, and all the data in the register is shifted one position to the right on the

LOW-to-HIGH transition of CP. The clock input’s Schmitt trigger action makes it highly tolerant of

slower clock rise and fall times.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually

ground). Unused inputs must be connected to VDD, VSS, or another input.

2. Features and benefits

•Tolerant of slow clock rise and fall times

•Fully static operation

•5 V, 10 V, and 15 V parametric ratings

•Standardized symmetrical output characteristics

•Specified from -40 °C to +85 °C

•Complies with JEDEC standard JESD 13-B

3. Applications

•Parallel-to-serial converter

•Serial data queueing

•General purpose register

4. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

HEF4014BT -40 °C to +85 °C SO16 plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

Nexperia HEF4014B

8-bit static shift register

5. Functional diagram

001aae556

10 CP SHIFT REGISTER

8 BITS

Q5 Q6 Q7

0D 1D 2D 3D 4D 5D 6D 7D

D5 D6 D7

Fig. 1. Functional diagram

001aae558

Q6 Q7

D0 D5 D6 D7PE

FF 0

FF 5

FF 6

FF 7

Fig. 2. Logic diagram

Product data sheet Rev. 10 — 17 October 2018 2 / 12

Nexperia HEF4014B

8-bit static shift register

6. Pinning information

6.1. Pinning

HEF4014B

D7 VDD

Q5 D6

Q7 D5

D3 D4

D2 Q6

D1 DS

D0 CP

VSS PE

001aae557

Fig. 3. Pin configuration SOT109-1 (SO16)

6.2. Pin description

Table 2. Pin description

Symbol Pin Description

Q5 to Q7 2, 12, 3 output

D0 to D7 7, 6, 5, 4, 13, 14, 15, 1 parallel data input

VSS 8 ground supply voltage

PE 9 parallel enable input

CP 10 clock input (LOW-to-HIGH edge-triggered)

DS 11 serial data input

VDD 16 supply voltage

Product data sheet Rev. 10 — 17 October 2018 3 / 12

Nexperia HEF4014B

8-bit static shift register

7. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;

↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition;

Inputs OutputsNumber of clock

transitions CP DS PE Q5 Q6 Q7

Serial operation

1 ↑ 1D L X X X

2 ↑ 2D L X X X

3 ↑ 3D L X X X

6 ↑ X L 1D X X

7 ↑ X L 2D 1D X

↑ X L 3D 2D 1D8

↓ X X no change no change no change

Parallel operation

↑ X H D5 D6 D71

↓ X X no change no change no change

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage -0.5 +18 V

IIK input clamping current VI < -0.5 V or VI > VDD + 0.5 V - ±10 mA

VIinput voltage -0.5 VDD + 0.5 V

IOK output clamping current VO < -0.5 V or VO > VDD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature -65 +150 °C

Tamb ambient temperature -40 +85 °C

Ptot total power dissipation Tamb = -40 °C to +85 °C [1] - 500 mW

P power dissipation per output - 100 mW

[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

Product data sheet Rev. 10 — 17 October 2018 4 / 12

Nexperia HEF4014B

8-bit static shift register

9. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VDD supply voltage 3 - 15 V

VIinput voltage 0 - VDD V

Tamb ambient temperature in free air -40 - +85 °C

VDD = 5 V - - 3.75 μs/V

VDD = 10 V - - 0.5 μs/V

Δt/ΔV input transition rise and fall rate

VDD = 15 V - - 0.08 μs/V

10. Static characteristics

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD unless otherwise specified.

Tamb = -40 °C Tamb = +25 °C Tamb = +85 °CSymbol Parameter Conditions VDD

Min Max Min Max Min Max

Unit

5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

VIH HIGH-level input voltage |IO| < 1 μA

15 V 11.0 - 11.0 - 11.0 - V

5 V - 1.5 - 1.5 - 1.5 V

10 V - 3.0 - 3.0 - 3.0 V

VIL LOW-level input voltage |IO| < 1 μA

15 V - 4.0 - 4.0 - 4.0 V

5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

VOH HIGH-level output voltage |IO| < 1 μA

15 V 14.95 - 14.95 - 14.95 - V

5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

VOL LOW-level output voltage |IO| < 1 μA

15 V - 0.05 - 0.05 - 0.05 V

VO = 2.5 V 5 V - -1.7 - -1.4 - -1.1 mA

VO = 4.6 V 5 V - -0.52 - -0.44 - -0.36 mA

VO = 9.5 V 10 V - -1.3 - -1.1 - -0.9 mA

IOH HIGH-level output current

VO = 13.5 V 15 V - -3.6 - -3.0 - -2.4 mA

VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

IOL LOW-level output current

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA

5 V - 20 - 20 - 150 μA

10 V - 40 - 40 - 300 μA

IDD supply current IO = 0 A

15 V - 80 - 80 - 600 μA

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 10 — 17 October 2018 5 / 12

Nexperia HEF4014B

8-bit static shift register

11. Dynamic characteristics

Table 7. Dynamic characteristics

Tamb = 25 °C; VSS = 0 V.

Symbol Parameter Conditions VDD Extrapolation formula [1] Min Typ Max Unit

5 V 103 ns + (0.55 ns/pF)CL- 130 260 ns

10 V 44 ns + (0.23 ns/pF)CL- 55 110 ns

tPHL HIGH to LOW

propagation delay

CP to Qn;

see Fig. 4

15 V 32 ns + (0.16 ns/pF)CL- 40 80 ns

5 V 88 ns + (0.55 ns/pF)CL- 115 230 ns

10 V 39 ns + (0.23 ns/pF)CL- 50 100 ns

tPLH LOW to HIGH

propagation delay

CP to Qn;

see Fig. 4

15 V 32 ns + (0.16 ns/pF)CL- 40 80 ns

5 V [2] 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL- 30 60 ns

tttransition time Qn output;

see Fig. 4

15 V 6 ns + (0.28 ns/pF)CL- 20 40 ns

5 V 70 35 - ns

10 V 30 15 - ns

tWpulse width CP input;

minimum width;

see Fig. 5

15 V 24 12 - ns

5 V 40 10 - ns

10 V 25 5 - ns

PE to CP;

see Fig. 5

15 V 15 0 - ns

5 V +35 -5 - ns

10 V +25 -5 - ns

DS to CP;

see Fig. 5

15 V 25 0 - ns

5 V +35 -5 - ns

10 V +25 -5 - ns

tsu set-up time

Dn to CP;

see Fig. 5

15 V 25 0 - ns

5 V +25 -5 - ns

10 V 20 0 - ns

PE to CP;

see Fig. 5

15 V 15 0 - ns

5 V 30 15 - ns

10 V 20 10 - ns

DS to CP;

see Fig. 5

15 V 15 7 - ns

5 V 30 15 - ns

10 V 20 10 - ns

thhold time

Dn to CP;

see Fig. 5

15 V 15 7 - ns

5 V 6 13 - MHz

10 V 15 30 - MHz

fclk(max) maximum clock

frequency

see Fig. 5

15 V 20 40 - MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

[2] tt is the same as tTHL and tTLH.

Product data sheet Rev. 10 — 17 October 2018 6 / 12

Nexperia HEF4014B

8-bit static shift register

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.

Symbol Parameter VDD Typical formula for PD (μW) Where:

5 V PD = 900 × fi + ∑(fo × CL) × VDD

10 V PD = 4300 × fi + ∑(fo × CL) × VDD

PDdynamic power

dissipation

15 V PD = 12000 × fi + ∑(fo × CL) × VDD

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

∑(CL × fo) = sum of the outputs.

11.1. Waveforms and test circuit

001aaj456

tPHL

tttt

CP input

Qn output

VSS

VOH

VOL

90 %

10 %

tPLH

Measurement points are given in Table 9.

Fig. 4. CP to Qn propagation delays and output transition times

001aae559

CP input

VSS

D input

PE input

DS input

tsu

50 %

50 % 50 % 50 %

fclk(max)

thth

tsu tsu

50 % 50 %

tsu

50 %

The shaded areas indicate where change is permitted for predictable output performance.

Set-up and hold times are shown as positive values but may be specified as negative values.

Measurement points are given in Table 9.

Fig. 5. Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Product data sheet Rev. 10 — 17 October 2018 7 / 12

Nexperia HEF4014B

8-bit static shift register

VDD

VIVO

001aag182

DUT

Test data is given in Table 10;

Definitions for test circuit:

DUT = Device Under Test.

CL = load capacitance including jig and probe capacitance.

RT = termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig. 6. Test circuit for measuring switching times

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD ≤ 20 ns 50 pF

Product data sheet Rev. 10 — 17 October 2018 8 / 12

Nexperia HEF4014B

8-bit static shift register

12. Package outline

w M

detail X

v M A

(A )

pin 1 index

UNIT A

max. A

1 A

2 A

3 b

p c D

(1) E

(1) (1)

e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Fig. 7. Package outline SOT109-1 (SO16)

Product data sheet Rev. 10 — 17 October 2018 9 / 12

Nexperia HEF4014B

8-bit static shift register

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4014B v.10 20181017 Product data sheet - HEF4014B v.9

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

HEF4014B v.9 20160321 Product data sheet - HEF4014B v.8

Modifications: •Type number HEF4014BP (SOT38-4) removed.

HEF4014B v.8 20111121 Product data sheet - HEF4014B v.7

Modifications: •Legal pages updated.

•Changes in "General description" and "Features and benefits".

HEF4014B v.7 20110914 Product data sheet - HEF4014B v.6

HEF4014B v.6 20091102 Product data sheet - HEF4014B v.5

HEF4014B v.5 20090624 Product data sheet - HEF4014B v.4

HEF4014B v.4 20090122 Product data sheet - HEF4014B_CNV v.3

HEF4014B_CNV v.3 19950101 Product specification - HEF4014B_CNV v.2

HEF4014B_CNV v.2 19950101 Product specification - -

Product data sheet Rev. 10 — 17 October 2018 10 / 12

Nexperia HEF4014B

8-bit static shift register

14. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

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data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

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multiple devices. The latest product status information is available on

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the Absolute Maximum Ratings System of IEC 60134) will cause permanent

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Product data sheet Rev. 10 — 17 October 2018 11 / 12

Nexperia HEF4014B

8-bit static shift register

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Applications.................................................................. 1

4. Ordering information....................................................1

5. Functional diagram.......................................................2

6. Pinning information......................................................3

6.1. Pinning.........................................................................3

6.2. Pin description............................................................. 3

7. Functional description................................................. 4

8. Limiting values............................................................. 4

9. Recommended operating conditions..........................5

10. Static characteristics..................................................5

11. Dynamic characteristics.............................................6

11.1. Waveforms and test circuit........................................ 7

12. Package outline.......................................................... 9

13. Revision history........................................................10

14. Legal information......................................................11

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 17 October 2018

Product data sheet Rev. 10 — 17 October 2018 12 / 12