LM555CN - ON SEMICONDUCTOR - Datasheet.Global

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LM555 — Single Timer

LM555 Rev. 1.1.0 1

January 2013

LM555

Single T i mer

Features

• High-Current Drive Capabili ty: 200 mA

• Adjustable Duty Cycle

• Temperature Stability of 0.005%/°C

• Timing From μs to Hours

• Turn off Time Less Than 2 μs

Applications

• Precision Timing

• Pulse Generati on

• Delay Generati on

• Sequential Timing

Ordering Information

Part Number Operating Temperature Range Top Mark Package Packing Method

LM555CN 0 ~ +70°C LM555CN DIP 8L Rail

LM555CM LM555CM SOIC 8L Rail

LM555CMX LM555CM SOIC 8L Tape & Reel

Description

The LM555 is a highly stable controller capable of pro-

ducing accura te timing pulse s. With a mon ostabl e opera-

tion, the delay is controlled by one external resistor and

one capacitor. With astable operation, the frequency and

duty cycle are accurately controlled by two external

resistors and one capacitor.

8-DIP

8-SOIC

LM555 — Single Timer

LM555 Rev. 1.1.0 2

Block Diagram

Figure 1. Block Diagram

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-

ble above the re co mmen ded operating conditions and s tres si ng the parts to these level s i s not recommended. In addi-

tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The

absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.

Symbol Parameter Value Unit

VCC Supply Voltage 16 V

TLEAD Lead Temperature (S oldering 10s) 300 °C

PDPower Dissipation 600 mW

TOPR Operating Temperature Range 0 ~ +70 °C

TSTG Storage Temperature Range -65 ~ +150 °C

F/F

OutPut

Stage

RRR

Comp.

Discharging Tr.

Vref

Vcc

Discharge

Threshold

Control

Voltage

GND

Trigger

Output

Reset

GND

Trigger

Output

Reset

VCC

Discharge

ThresholdControl

Voltage

Threshold

VREF

Discharging Tr ansistor

LM555 — Single Timer

LM555 Rev. 1.1.0 3

Electrical Characteristics

Values are at TA = 25°C, VCC = 5 ~ 15 V unless otherwise specified.

Notes:

1. When the output is high, the supply current is typically 1 mA less than at VCC = 5 V.

2. Tested at VCC = 5.0 V and VCC = 15 V.

3. These parameters, although guaranteed, are not 100% tested in production.

4. This determines the maximum value of RA + RB for 15 V operation, the maximum total R = 20 MΩ, and for 5 V

operation, the maximum total R = 6.7 MΩ.

Parameter Symbol Conditions Min. Typ. Max. Unit

Supply Voltage VCC 4.5 16.0 V

Supply Current (Low Stable) (1) ICC VCC = 5 V, RL = ∞36mA

VCC = 15 V, RL = ∞7.5 15.0 mA

Timing Error (Monostable)

Initial Accuracy (2) ACCUR RA = 1 kΩ to100 kΩ

C = 0.1 μF

1.0 3.0 %

Drift with Temperature (3) Δt / ΔT50ppm / °C

Drift with Supply Voltage (3) Δt / ΔVCC 0.1 0.5 % / V

Timing Error (Astable)

InItial Accuracy (2) ACCUR RA = 1 kΩ to 100kΩ

C = 0.1 μF

2.25 %

Drift with Temperature (3) Δt / ΔT 150 ppm / °C

Drift with Supply Voltage (3) Δt / ΔVCC 0.3 % / V

Control Voltage VCVCC = 15 V 9.0 10.0 11.0 V

VCC = 5 V 2.60 3.33 4.00 V

Threshold Voltage VTH VCC = 15 V 10.0 V

VCC = 5V 3.33 V

Threshold Current (4) ITH 0.10 0.25 μA

Trigger Voltage VTR VCC = 5 V 1.101.672.20 V

VCC = 15 V 4.5 5.0 5.6 V

Trigger Current ITR VTR = 0 V 0.01 2.00 μA

Reset Voltage VRST 0.4 0.7 1.0 V

Reset Current IRST 0.1 0.4 mA

Low Output Voltage VOL VCC = 15 V ISINK = 10 mA 0.06 0.25 V

ISINK = 50 mA 0.30 0.75 V

VCC = 5 V, ISINK = 5 mA 0.05 0.35 V

High Output Voltage VOH VCC = 15 V ISOURCE = 200 mA 12.5 V

ISOURCE = 100 mA 12.75 13.30 V

VCC = 5 V, ISOURCE = 100 mA 2.75 3.30 V

Rise Time of Output(3) tR100 ns

Fall Time of Output(3) tF100 ns

Discharge Leaka ge Curre nt ILKG 20 100 nA

LM555 — Single Timer

LM555 Rev. 1.1.0 4

Application Information

Table 1 below is the basic operating t able of 555 timer.

When the low signa l input is appli ed to the reset te rminal, the timer outpu t remains low reg ardless of the thr eshold vo lt-

age or the trig ger volt age. Only when the high s ignal is app lied to the res et terminal, the timer's output ch anges acco rd-

ing to threshol d voltage and trigger voltage.

When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal dis-

charge transi sto r turns on, lowering the thresho ld voltage to below 1/3 of the supply voltage. Du rin g th is ti me , t he timer

output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply volt-

age, the timer's internal discharge transistor turns off, increasing the threshold voltage and driving the timer output

again at high.

1. Monostable Operation

Table 1. Basic Operating Table

Reset

(PIN 4) VTR

(PIN 2) VTH

(PIN 6) Output

(PIN 3)

Discharging

Transistor

(PIN 7)

Low X X Low ON

High < 1/3 VCC XHighOFF

High > 1/3 VCC > 2/3 VCC Low ON

High > 1/3 VCC < 2/3 VCC Previous State

Figure2. Monostable Circuit Figure 3. Resistance and Capacitance vs.

Time Delay (tD)

Figure 4. Waveforms of Monostable Operation

RESET Vcc

DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

C2RL

Trigger

10-5 10-4 10-3 10-2 10-1 100101102

10-3

10-2

10-1

100

101

102

10MΩ

1MΩ

10kΩ

100kΩ

RA=1kΩ

Capacitance(uF)

Time Delay(s)

LM555 — Single Timer

LM555 Rev. 1.1.0 5

1. Monostable Operation

Figure 2 illustrates a mono stable circuit. In this mode, the timer genera tes a fixe d pul se whe nev er the trigg er voltage

falls below VCC/3. When the trigger pulse voltage applied to the #2 pin falls below VCC/3 while the timer output is low,

the timer's intern al flip -flo p turns the discharging transistor off and causes the timer output to be co me hig h by cha rgi ng

the external capacitor C1 and setting the flip-flop output at the same time.

The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t = RA*C and

reaches 2 VCC/3 at tD = 1.1 RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant

RAC, the longer it takes for the VC1 to reac h 2 VCC/3. In other words, the time constant RAC controls the output pulse

width.

When the applied vo ltage to the capacitor C1 reaches 2 VCC/3, the compa rato r on t he tri gg er te rmi na l res ets the flip-

flop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low.

In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant rela-

tionship based on RA and C. Figure 4 shows the general waveforms during the monostable operation.

It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of VCC/3 before

the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied

while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at

the end of the output pulse remains at below VCC/3. Figure 5 shows such a timer output abnormality.

2. Astable Operation

Figure 5. Waveforms of Monostable Operation

(abnormal)

Figure 6. A Stable Circuit Figure 7. Capacitance and Resistance vs. Frequency

RESET Vcc

DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

C2RL

100m 1 10 100 1k 10k 100k

1E-3

0.01

0.1

100

10MΩ

1MΩ

100kΩ

10kΩ

1kΩ

(RA+2RB)

Capacitance(uF)

Frequency(Hz)

LM555 — Single Timer

LM555 Rev. 1.1.0 6

An astab le timer ope ration is ac hieved b y adding res istor RB to Figure 2 a nd config uring as shown on Fi gure 6. In t he

astable operati on, the trig ger terminal and the thresh old termin al are con necte d so that a se lf-trig ger is formed , operat-

ing as a multi -vi brator . Whe n the timer output is high, its internal discharging tran si st or. turns off and the VC1 increases

by exponential function with the time constant (RA+RB)*C.

When the VC1, or the threshold voltage, reaches 2 VCC/3; the comparator output on the trigger terminal becomes

high, resetti ng the F/ F and causing the timer o utp ut to bec ome lo w. This turns on the d is ch arg ing tra ns is tor an d the C1

discharges through the discharging channel formed by RB and the discharging transistor. When the VC1 falls below

VCC/3, the comparator output on the trigger terminal becomes high and the timer output becomes high again. The dis-

charging transistor turns off and the VC1 rises again.

In the above proc ess, the secti on where the timer o utput is high is t he time it t akes for the V C1 to rise from VCC/3 to 2

VCC/3, and the section where the timer output is low is the time it takes for the VC1 to drop from 2 VCC/3 to VCC/3.

When timer output is high, the equivalent circuit for charging capacitor C1 is as follows:

Since the duration of the timer output high state (tL) is the amount of time it takes for the VC1(t) to reach 2 VCC/3,

Figure 8. Waveforms of Astable Operation

Vcc

RARB

C1 Vc1

(0-)=Vcc/3

C1dvc1

------------- Vcc V0-()–

RARB

-------------------------------=1()

VC1 0+() VCC 3⁄=2()

VC1 t() VCC 12

---e

-t

RARB

+()C1

-------------------------------------

–





–







=3()

VC1 t() 2

---VCC V= CC 12

---e

-tH

RARB

+()C1

-------------------------------------

–







–







=4()

tHC1RARB

+()In2 0.693 RARB

+()C1

==5()

LM555 — Single Timer

LM555 Rev. 1.1.0 7

The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows:

Since the duration of the timer output low state (tL) is the amount of time it takes for the VC1(t) to reach VCC/3,

Since RD is normally RB>>RD although related to the size of discharging transistor,

tL = 0.693RBC1 (10)

Consquently, if the timer operates in astable, the period is the same with

't = tH+tL = 0.693(RA+RB)C1+0.693RBC1 = 0.693(RA+2RB)C1'

because the period is the sum of the charge time and discharge time. Since frequency is the reciprocal of the period,

the following applies:

VC1(0-)=2Vcc/3

C1dvC1

---------------1

RARB

----------------------- VC1 0=+6()

VC1 t() 2

---VCCe

-t

RARD

+()C1

-------------------------------------

=7()

--- VCC 2

--- VCCe

-tL

RARD

+()C1

-------------------------------------

=8()

tLC1RBRD

+()In2 0.693 RBRD

+()C1

== 9()

frequency, f 1

---1.44

RA2RB

+()C1

----------------------------------------== 11()

LM555 — Single Timer

LM555 Rev. 1.1.0 8

3. Frequency Divider

By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider.

Figure 9. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing

cycle.

4. Pulse Width Modulation

The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and chang-

ing the referenc e of the timer's internal comparators. Figure 10 illustrates the pulse width modulation circuit.

When the continu ous trigger puls e train is appli ed in the monost able mode , the timer outp ut width is modulated ac cord-

ing to the signal applied to the control terminal. Sine wave, as well as other waveforms, may be applied as a signal to

the control terminal. Figure 11 shows the example of pulse width modulation waveform.

Figure 9. Waveforms of Frequency Divider Operation

Figure 10. Circuit for Pulse Width Modulation Figure 11. Waveforms of Pulse Width Modulation

CONT

GND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc

Trigger

Output Input

LM555 — Single Timer

LM555 Rev. 1.1.0 9

5. Pulse Position Modulation

If the modulating signal is applied to the control terminal while the timer is connected for the astable operation, as in

Figure 12, the timer becomes a pulse position modulator.

In the pulse position modulator, the reference of the timer's internal comparators is modulated, which modulates the

timer output ac cording to the modulation signal applied to the control terminal.

Figure 13 illu strates a si ne wave for mo dulation si gnal and the resulting ou tput pulse po sition modula tion; howe ver, any

wave shape be used.

6. Linear Ramp

When the pull -up resistor RA in the monostable circuit shown in Figure 2 is replaced with constant current source, the

VC1 increases linearly, generating a linear ramp. Figure 14 shows the linea r ramp generating c ircuit and Fig ure 15 illus-

trates the generated linear ramp waveforms.

Figure 12. Circuit for Pulse Position Modluation Figure 13. Wafeforms of pulse position modulation

Figure 14. Circuit for Linear Ramp Figure 15. Waveforms of Linear Ramp

CONT

GND

Vcc

DISCH

THRES

RESET

TRIG

OUT

+Vcc

Modulation

Output

RESET Vcc

DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

Output

LM555 — Single Timer

LM555 Rev. 1.1.0 10

In Figure 14, current source is created by PNP transistor Q1 and resistor R1, R2, and RE.

For example, if VCC = 15 V, RE = 20 kΩ, R1 = 5 kΩ, R2 = 10 kΩ, and VBE = 0.7 V,

VE=0.7 V+10 V=10.7 V, and

IC=(15-10.7) / 20 k=0.215 mA.

When the trigg er st art s in a time r con figured as s hown i n Fig ure 14 , the cu rrent fl owing through cap a citor C1 bec omes

a constant current generated by PNP transistor and re sistors.

Hence, the VC is a linea r ramp func tion a s sh own in Figu re 15. The g radien t S of the line ar ramp f uncti on is defin ed as

follows:

Here the Vp-p is the peak-to-peak voltage.

If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:

V = Q/C (15)

The above equation divided on both sides by t gives:

and may be simplified into the following equation:

S = I/C (17)

In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the

constant current flowing through the capacitor.

If the const a nt cu rrent flow through the capaci tor is 0.215 mA an d th e ca pacitance is 0.02 μF, the gradient of the ra mp

function at both ends of the capacitor is S = 0.215 m / 0.022 μ = 9.77 V/ms.

ICVCC VE

–

---------------------------=12()

Here, VE is

VEVBE R2

R1R2

----------------------VCC

+=13()

SVpp–

----------------=14()

----Qt§

-------------=16()

LM555 — Single Timer

LM555 Rev. 1.1.0 11

Physical Dimensions

Figure 16. 8-Lead, DIP, JEDEC MS-001, 300" WIDE

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notic e. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor represe ntative to verify or

obtain the most recent revision. Package specifica tions do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild produ cts.

Always visit Fairchild Semiconduct or’s online packaging are a for the most recent package drawings :

http://www.fairchildsemi.com/packaging/.

For current tape an d reel specifications, visit Fair child Semiconductor’s online pac kaging area:

http://www.fairchildsemi.com/products/discrete/pdf/8dip_tr.pdf.

7° TYP

.430 MAX

[10.92]

A.400

.373 [10.15

9.46 ]

.250±.005 [6.35±0.13]

.036 [0.9 TYP]

.070

.045 [1.78

1.14]

.100

[2.54]

.300

[7.62]

.060 MAX

[1.52]

.310±.010 [7.87±0.25]

.130±.005 [3.3±0.13]

.210 MAX

[5.33]

.140

.125 [3.55

3.17]

.015 MIN

[0.38]

.021

.015 [0.53

0.37]

.010+.005

-.000 [0.254+0.127

-0.000 ]

PIN #1

(.032) [R0.813]

(.092) [Ø2.337]

TOP VIEW

OPTION 1

TOP VIEW

OPTION 2

.001[.025] C

N08EREVG

C. DOES NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

DAMBAR PROTRUSIONS SHALL NOT EXCEED

D. DOES NOT INCLUDE DAMBAR PROTRUSIONS.

B. CONTROLING DIMENSIONS ARE IN INCHES

A. CONFORMS TO JEDEC REGISTRATION MS-001,

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED

VARIATIONS BA

E. DIMENSIONING AND TOLERANCING

NOTES:

REFERENCE DIMENSIONS ARE IN MILLIMETERS

.010 INCHES OR 0.25MM.

PER ASME Y14.5M-1994.

8-DIP

LM555 — Single Timer

LM555 Rev. 1.1.0 12

Physical Dimensions (continued)

Figure 17. 8-Lead, SOIC,JEDEC MS-012, 150" NARROW BODY

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notic e. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor represe ntative to verify or

obtain the most recent revision. Package specifica tions do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild produ cts.

Always visit Fairchild Semiconduct or’s online packaging are a for the most recent package drawings :

http://www.fairchildsemi.com/packaging/.

For current tape an d reel specifications, visit Fair child Semiconductor’s online pac kaging area:

http://www.fairchildsemi.com/dwg/M0/M08A.pdf.

8-SOIC

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Rev. I63

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