Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
DS1302
Trickle Charge Timekeeping Chip
DS1302
041697 1/12
FEATURES
•Real time clock counts seconds, minutes, hours, date
of the month, month, day of the week, and year with
leap year compensation valid up to 2100
•31 x 8 RAM for scratchpad data storage
•Serial I/O for minimum pin count
•2.5–5.5 volt full operation
– Optional 2.0–5.5 volt full operation also available
•Uses less than 300 nA at 2.5 volts
•Single–byte or multiple–byte (burst mode) data trans-
fer for read or write of clock or RAM data
•8–pin DIP or optional 8–pin SOIC’s for surface mount
•Simple 3–wire interface
•TTL–compatible (VCC = 5V)
•Optional industrial temperature range –40°C to +85°C
•DS1202 compatible
•Added features over DS1202
– Optional trickle charge capability to VCC1
– Dual power supply pins for primary and backup
power supplies
– Backup power supply pin can be used for battery
or super cap input
– Additional scratchpad memory (7 bytes)
PIN ASSIGNMENT
DS1302
VCC1
SCLK
I/O
RST
VCC2
X1
X2
GND
1
2
3
4
8
7
6
5
VCC1
SCLK
I/O
RST
VCC2
X1
X2
GND
1
2
3
4
8
7
6
5
DS1302S 8–PIN SOIC (200 MIL)
8–PIN DIP (300 MIL)
DS1302Z 8–PIN SOIC (150 MIL)
PIN DESCRIPTION
X1, X2 – 32.768 kHz Crystal Pins
GND – Ground
RST – Reset
I/O – Data Input/Output
SCLK – Serial Clock
VCC1, VCC2 – Power Supply Pins
ORDERING INFORMATION
PART # DESCRIPTION
DS1302 Serial T imekeeping Chip; 8–pin DIP
DS1302S Serial T imekeeping Chip;
8–pin SOIC (200 mil)
DS1302Z Serial T imekeeping Chip;
8–pin SOIC (150 mil)
DESCRIPTION
The DS1302 Trickle Charge Timekeeping Chip contains
a real time clock/calendar and 31 bytes of static RAM. It
communicates with a microprocessor via a simple serial
interface. The real time clock/calendar provides
seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically
adjusted for months with less than 31 days, including
corrections for leap year. The clock operates in either
the 24–hour or 12–hour format with an AM/PM indicator.
Interfacing the DS1302 with a microprocessor is simpli-
fied by using synchronous serial communication. Only
three wires are required to communicate with the clock/
RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK
(Serial clock). Data can be transferred to and from the
clock/RAM one byte at a time or in a burst of up to 31
bytes. The DS1302 is designed to operate on very low
power and retain data and clock information on less
than 1 microwatt.
1
76
A4
5
A3
4
A2
3
A1
2
A0
1
RD
0
W
RAM
CK
DS1302
041697 2/12
The DS1302 is the successor to the DS1202. In addi-
tion to the basic timekeeping functions of the DS1202,
the DS1302 has the additional features of dual power
pins for primary and back–up power supplies, program-
mable trickle charger for VCC1, and seven additional
bytes of scratchpad memory.
OPERATION
The main elements of the Serial Timekeeper are shown
in Figure 1: shift register, control logic, oscillator, real
time clock, and RAM. To initiate any transfer of data,
RST is taken high and eight bits are loaded into the shift
register providing both address and command informa-
tion. Data is serially input on the rising edge of the SCLK.
The first eight bits specify which of 40 bytes will be
accessed, whether a read or write cycle will take place,
and whether a byte or burst mode transfer is to occur.
After the first eight clock cycles have loaded the com-
mand word into the shift register, additional clocks will
output data for a read or input data for a write. The num-
ber of clock pulses equals eight plus eight for byte mode
or eight plus up to 248 for burst mode.
COMMAND BYTE
The command byte is shown in Figure 2. Each data
transfer is initiated by a command byte. The MSB (Bit 7)
must be a logic “1”. If it is zero, writes to the DS1302 will
be disabled. Bit 6 specifies clock/calendar data if logic
“0” or RAM data if logic “1”. Bits one through five specify
the designated registers to be input or output, and the
LSB (Bit 0) specifies a write operation (input) if logic “0”
or read operation (output) if logic “1”. The command
byte is always input starting with the LSB (Bit 0).
DS1302 BLOCK DIAGRAM Figure 1
32.768 kHz
X2X1
OSCILLATOR
AND DIVIDER
REAL TIME
CLOCK
DATA BUS
INPUT SHIFT
REGISTERS
COMMAND AND
CONTROL LOGIC ADDRESS BUS 31 X 8 RAM
I/O
SCLK
RST
POWER
CONTROL
VCC1
VCC2
GND
ADDRESS/COMMAND BYTE Figure 2
DS1302
041697 3/12
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input
high. The RST input serves two functions. First, RST
turns on the control logic which allows access to the shift
register for the address/command sequence. Second,
the RST signal provides a method of terminating either
single byte or multiple byte data transfer.
A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, data must be valid during
the rising edge of the clock and data bits are output on
the falling edge of clock. If the RST input is low all data
transfer terminates and the I/O pin goes to a high imped-
ance state. Data transfer is illustrated in Figure 3. At
power–up, RST must be a logic “0” until VCC2.5 volts.
Also SCLK must be at a logic “0” when RST is driven to a
logic “1” state.
DATA INPUT
Following the eight SCLK cycles that input a write com-
mand byte, a data byte is input on the rising edge of the
next eight SCLK cycles. Additional SCLK cycles are
ignored should they inadvertently occur. Data is input
starting with bit 0.
DATA OUTPUT
Following the eight SCLK cycles that input a read com-
mand byte, a data byte is output on the falling edge of
the next eight SCLK cycles. Note that the first data bit to
be transmitted occurs on the first falling edge after the
last bit of the command byte is written. Additional SCLK
cycles retransmit the data bytes should they inadver-
tently occur so long as RST remains high. This opera-
tion permits continuous burst mode read capability.
Also, the I/O pin is tri–stated upon each rising edge of
SCLK. Data is output starting with bit 0.
BURST MODE
Burst mode may be specified for either the clock/calen-
dar or the RAM registers by addressing location 31 deci-
mal (address/command bits one through five = logical
one). As before, bit six specifies clock or RAM and bit 0
specifies read or write. There is no data storage capac-
ity at locations 9 through 31 in the Clock/Calendar Reg-
isters or location 31 in the RAM registers. Reads or
writes in burst mode start with bit 0 of address 0.
As in the case with the DS1202, when writing to the
clock registers in the burst mode, the first eight registers
must be written in order for the data to be transferred.
However, when writing to RAM in burst mode it is not
necessary to write all 31 bytes for the data to transfer.
Each byte that is written to will be transferred to RAM
regardless of whether all 31 bytes are written or not.
CLOCK/CALENDAR
The clock/calendar is contained in seven write/read reg-
isters as shown in Figure 4. Data contained in the clock/
calendar registers is in binary coded decimal format
(BCD).
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt
flag. When this bit is set to logic “1”, the clock oscillator is
stopped and the DS1302 is placed into a low–power
standby mode with a current drain of less than 100
nanoamps. When this bit is written to logic “0”, the clock
will start.
AM-PM/12-24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10 hour bit (20 – 23 hours).
WRITE PROTECT BIT
Bit 7 of the control register is the write protect bit. The
first seven bits (bits 0 – 6) are forced to zero and will
always read a zero when read. Before any write opera-
tion to the clock or RAM, bit 7 must be zero. When high,
the write protect bit prevents a write operation to any
other register.
TRICKLE CHARGE REGISTER
This register controls the trickle charge characteristics
of the DS1302. The simplified schematic of Figure 5
shows the basic components of the trickle charger. The
trickle charge select (TCS) bits (bits 4 – 7) control the
selection of the trickle charger . In order to prevent acci-
dental enabling, only a pattern of 1010 will enable the
trickle charger . All other patterns will disable the trickle
charger. The DS1302 powers up with the trickle charger
disabled. The diode select (DS) bits (bits 2 – 3) select
whether one diode or two diodes are connected
between VCC2 and VCC1. If DS is 01, one diode is
selected or if DS is 10, two diodes are selected. If DS is
00 or 11, the trickle charger is disabled independent of
DS1302
041697 4/12
TCS. The RS bits (bits 0 – 1) select the resistor that is
connected between VCC2 and VCC1. The resistor
selected by the resistor select (RS) bits is as follows:
RS Bits Resistor Typical V alue
00 None None
01 R1 2KΩ
10 R2 4KΩ
11 R3 8KΩ
If RS is 00, the trickle charger is disabled independent
of TCS.
Diode and resistor selection is determined by the user
according to the maximum current desired for battery or
super cap charging. The maximum charging current
can be calculated as illustrated in the following example.
Assume that a system power supply of 5V is applied to
VCC2 and a super cap is connected to VCC1. Also
assume that the trickle charger has been enabled with 1
diode and resistor R1 between VCC2 and VCC1. The
maximum current Imax would therefore be calculated as
follows:
Imax = (5.0V – diode drop) / R1
~ (5.0V – 0.7V) / 2KΩ
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop
between VCC2 and VCC1 will decrease and therefore the
charge current will decrease.
CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst
mode operation. In this mode the first eight clock/calen-
dar registers can be consecutively read or written (see
Figure 4) starting with bit 0 of address 0.
If the write protect bit is set high when a write clock/cal-
endar burst mode is specified, no data transfer will occur
to any of the eight clock/calendar registers (this includes
the control register). The trickle charger is not accessi-
ble in burst mode.
RAM
The static RAM is 31 x 8 bytes addressed consecutively
in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode opera-
tion. In this mode, the 31 RAM registers can be consec-
utively read or written (see Figure 4) starting with bit 0 of
address 0.
REGISTER SUMMARY
A register data format summary is shown in Figure 4.
CRYSTAL SELECTION
A 32.768 kHz crystal can be directly connected to the
DS1302 via pins 2 and 3 (X1, X2). The crystal selected
for use should have a specified load capacitance (CL) of
6 pF.
POWER CONTROL
VCC1 provides low power operation in single supply and
battery operated systems as well as low power battery
backup.
VCC2 provides the primary power in dual supply sys-
tems where VCC1 is connected to a backup source to
maintain the time and data in the absence of primary
power.
The DS1302 will operate from the larger of VCC1 or
VCC2. When VCC2 is greater than VCC1 + 0.2V , VCC2 will
power the DS1302. When VCC2 is less than VCC1, VCC1
will power the DS1302.
DS1302
041697 5/12
DATA TRANSFER SUMMARY Figure 3
SCLK
I/O
RST
012345670123456 7
R/W A0 A1 A2 A3 A4 1
ADDRESS COMMAND DATA INPUT/OUTPUT
SINGLE BYTE TRANSFER
SCLK
I/O
01234567012 456 7
11111 1
ADDRESS COMMAND DATA I/O BYTE N
BURST MODE TRANSFER
RST
R/W
DATA I/O BYTE 1
R/C
R/C
FUNCTION BYTE N SCLK n
CLOCK 8 72
RAM 31 256
DS1302
041697 6/12
REGISTER ADDRESS/DEFINITION Figure 4
1
76
0
5
0
4
0
3
0
2
0
1
RD
0
W
REGISTER ADDRESS REGISTER DEFINITION
0
1 0 0 0 0 1 RD
0W
1 0 0 0 1 0 RD
0
1 0 0 0 1 1 RD
0
W
W
1 0 0 1 0 0 RD
0
1 0 0 1 0 1 RD
0
1 0 0 1 1 0 RD
0
1 0 0 1 1 1 RD
0
W
W
W
W
1 0 1 0 0 0 RD
0W
1 0 0 0 0 0 RD
1
1 1 1 1 1 0 RD
1
1 1 1 1 1 1 RD
1
W
W
W
A. CLOCK
B. RAM
SEC
MIN
HR
DATE
MONTH
DAY
YEAR
CONTROL
TRICKLE
CH SEC10 SEC
0
12/ HR HR0
010 DATE0
0 0 10
0
0 0 00
10 YEAR
00–59
00–59
01–12
01–28/29
01–12
01–07
00–99
RAM 0
RAM 30
RAM
BURST
RAM DATA 0
RAM DATA 30
MIN10 MIN
00–23 24 10
A/P
01–30
01–31 DATE
MMONTH
YEAR
DAY0
WP 0 0 0 0 000
111111
RD
0W
CLOCK
BURST
TCS TCS TCS DS DS RSTCS RS
CHARGER
DS1302
041697 7/12
DS1302 PROGRAMMABLE TRICKLE CHARGER Figure 5
1 OF 3
SELECT
1 OF 2
SELECT
1 OF 16 SELECT
(NOTE: ONLY 1010 CODE ENABLES CHARGER
VCC2
PIN #1
VCC1
PIN #8
TRICKLE CHARGER SELECT
DIODE SELECT
RESISTOR SELECT
=
=
=
TCS
DS
RS
TRICKLE TCS TCS TCS TCS DS DS RS RS
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
R1
R2
R3
2KΩ
4KΩ
8KΩ
CHARGE
REGISTER
DS1302
041697 8/12
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground –0.5V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –55°C to +125°C
Soldering Temperature 260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
The Dallas Semiconductor DS1302 is built to the highest quality standards and manufactured for long term reliability .
All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods. However,
standard versions of the DS1302 are not exposed to environmental stresses, such as burn–in, that some industrial
applications require. Products which have successfully passed through this series of environmental stresses are
marked IND or N, denoting their extended operating temperature and reliability rating. For specific reliability informa-
tion on this product, please contact the factory in Dallas at (972) 371–4448.
RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC1, VCC2 VCC1,
VCC2 2.5 5.5 V 1, 11
Logic 1 Input VIH 2.0 VCC+0.3 V 1
Logic 0 Input
VIL
VCC=2.5V –0.3 +0.3
V
1
L
og
i
c
0
I
npu
t
V
IL VCC=5V –0.3 +0.8
V
1
DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 2.5 to 5.5V*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage ILI +500 µA 6
I/O Leakage ILO +500 µA 6
Logic 1 Output
VOH
VCC=2.5V 1.6
V
2
L
og
i
c
1
O
u
t
pu
t
V
OH VCC=5V 2.4
V
2
Logic 0 Output
VOL
VCC=2.5V 0.4
V
3
L
og
i
c
0
O
u
t
pu
t
V
OL VCC=5V 0.4
V
3
Active Supply Current
ICC1A
VCC1=2.5V 0.4
mA
512
A
c
ti
ve
S
upp
l
y
C
urren
t
I
CC1A VCC1=5V 1.2 m
A
5
,
12
Timekeeping Current
ICC1T
VCC1=2.5V 0.3
µA
412
Ti
me
k
eep
i
ng
C
urren
t
I
CC1T VCC1=5V 1 µ
A
4
,
12
Standby Current
ICC1S
VCC1=2.5V 100
nA
10, 12,
St
an
db
y
C
urren
t
I
CC1S VCC1=5V 100 n
A
10
,
12
,
14
Active Supply Current
ICC2A
VCC2=2.5V 0.425
mA
513
A
c
ti
ve
S
upp
l
y
C
urren
t
I
CC2A VCC2=5V 1.28 m
A
5
,
13
*Unless otherwise noted.
DS1302
041697 9/12
DC ELECTRICAL CHARACTERISTICS (cont’d) (0°C to 70°C; VCC = 2.5 to 5.5V*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Timekeeping Current
ICC2T
VCC2=2.5V 25.3
µA
413
Ti
me
k
eep
i
ng
C
urren
t
I
CC2T VCC2=5V 81 µ
A
4
,
13
Standby Current
ICC2S
VCC2=2.5V 25
µA
10 13
St
an
db
y
C
urren
t
I
CC2S VCC2=5V 80 µ
A
10
,
13
T rickle Charge Resistors R1
R2
R3
2
4
8
KΩ
KΩ
KΩ
T rickle Charger Diode V oltage Drop VTD 0.7 V
*Unless otherwise noted.
CAPACITANCE (tA = 25°C)
PARAMETER SYMBOL CONDITION TYP MAX UNITS NOTES
Input Capacitance CI10 pF
I/O Capacitance CI/O 15 pF
Crystal Capacitance CX6 pF
AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = +5V ± 10%*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Data to CLK Setup
tDC
VCC=2.5V 200
ns
7
D
a
t
a
t
o
CLK
S
e
t
up
t
DC VCC=5V 50 ns
7
CLK to Data Hold
tCDH
VCC=2.5V 280
ns
7
CLK
t
o
D
a
t
a
H
o
ld
t
CDH VCC=5V 70 ns
7
CLK to Data Delay
tCDD
VCC=2.5V 800
ns
789
CLK
t
o
D
a
t
a
D
e
l
ay
t
CDD VCC=5V 200 ns
7
,
8
,
9
CLK Low Time
tCL
VCC=2.5V 1000
ns
7
CLK
L
ow
Ti
me
t
CL VCC=5V 250 ns
7
CLK High Time
tCH
VCC=2.5V 1000
ns
7
CLK
Hi
g
h
Ti
me
t
CH VCC=5V 250 ns
7
CLK Frequency
tCLK
VCC=2.5V 0.5
MHz
7
CLK
F
requency
t
CLK VCC=5V DC 2.0
MH
z
7
CLK Rise and Fall
tRtF
VCC=2.5V 2000
ns
CLK
Ri
se an
d
F
a
ll
t
R,
t
FVCC=5V 500 ns
RST to CLK Setup
tCC
VCC=2.5V 4
µs
7
RST
t
o
CLK
S
e
t
up
t
CC VCC=5V 1 µs
7
*Unless otherwise noted.
DS1302
041697 10/12
AC ELECTRICAL CHARACTERISTICS (cont’d) (0°C to 70°C; VCC = +5V ± 10%*)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CLK to RST Hold
tCCH
VCC=2.5V 240
ns
7
CLK
t
o
RST
H
o
ld
t
CCH VCC=5V 60 ns
7
RST Inactive Time
tCWH
VCC=2.5V 4
µs
7
RST
I
nac
ti
ve
Ti
me
t
CWH VCC=5V 1 µs
7
RST to I/O High Z
tCDZ
VCC=2.5V 280
ns
7
RST
t
o
I/O
Hi
g
h
Z
t
CDZ VCC=5V 70 ns
7
SCLK to I/O High Z
tCCZ
VCC=2.5V 280
ns
7
SCLK
t
o
I/O
Hi
g
h
Z
t
CCZ VCC=5V 70 ns
7
*Unless otherwise noted.
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
tCC
tCDD
tCCZ
tCDH
tDC
017
RST
SCLK
I/O
WRITE COMMAND BYTE READ DATA BIT
0 1
tCDD tCDZ
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
tCC
01
RST
SCLK
I/O 7
tCWH
tCCH
tCDH
tDC
tF
tR
tCH
tCL
WRITE COMMAND BYTE WRITE DATA
0
DIM MIN MAX
8–PINPKG
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
0.360
9.14 0.400
10.16
0.240
6.10 0.260
6.60
0.120
3.05 0.140
3.56
0.300
7.62 0.325
8.26
0.015
0.38 0.040
1.02
0.120
3.04 0.140
3.56
0.090
2.29 0.110
2.79
0.320
8.13 0.370
9.40
0.008
0.20 0.012
0.30
0.015
0.38 0.021
0.53
B
C
EF
G
H
J
K
D
14
85
A
DS1302
041697 11/12
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2.5V, VOH=VCC for
capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.5V, VOL=GND for
capacitive loads.
4. ICC1T and ICC2T are specified with I/O open, RST set to a logic “0”, and clock halt flag=0 (oscillator enabled).
5. ICC1A and ICC2A are specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500 kHz,
VCC=2.5V and clock halt flag=0 (oscillator enabled).
6. RST, SCLK, and I/O all have 40KΩ pulldown resistors to ground.
7. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.
8. Measured at VOH=2.4V or VOL=0.4V.
9. Load capacitance = 50 pF.
10.ICC1S and ICC2S are specified with RST , I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator
disabled).
11. VCC=VCC2, when VCC2>VCC1+0.2V; VCC=VCC1, when VCC1>VCC2.
12.VCC2=0 volts.
13.VCC1=0 volts.
14.Typical values are at 25°C.
DS1302 SERIAL TIMEKEEPER 8–PIN DIP
DS1302
041697 12/12
DS1302S SERIAL TIMEKEEPER 8–PIN SOIC (150 MIL AND 200 MIL)
DIM MIN MAX
8–PIN
(150 MIL)
PKG
A IN.
MM
B IN.
MM
C IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
0.188
4.78 0.196
4.98
0.150
3.81 0.158
4.01
0.048
1.22 0.062
1.57
0.004
0.10 0.010
0.25
0.053
1.35 0.069
1.75
0.230
5.84 0.244
6.20
0.007
0.18 0.011
0.28
0.012
0.30 0.020
0.51
0.016
0.41 0.050
1.27
L IN.
MM
phi 0°8°
MIN MAX
0.203
5.16 0.213
5.41
0.203
5.16 0.213
5.41
0.070
1.78 0.074
1.88
0.004
0.10 0.010
0.25
0.074
1.88 0.084
2.13
0.302
7.67 0.318
8.08
0.006
0.15 0.010
0.25
0.013
0.33 0.020
0.51
0.019
0.48 0.030
0.76
0°8°
0.050 BSC
1.27 BSC
8–PIN
(200 MIL)
56–G2008–001
56–G4010–001
