1
LT1161
1161fa
Quad Protected High-Side
MOSFET Driver
■
8V to 48V Power Supply Range
■
Protected from – 15V to 60V Supply Transients
■
Fully Enhances N-Channel MOSFET Switches
■
Individual Short-Circuit Protection
■
Individual Automatic Restart Timers
■
Programmable Current Limit, Delay Time, and
Auto-Restart Period
■
Voltage-Limited Gate Drive
■
Defaults to OFF State with Open Input
■
Flowthrough Input to Output Pinout
■
Available in 20-Lead DIP or SOL Package
The LT1161 is a quad high-side gate driver allowing the
use of low cost N-channel power MOSFETs for high-side
switching applications. It has four independent switch
channels, each containing a completely self-contained
charge pump to fully enhance an N-channel MOSFET
switch with no external components.
Also included in each switch channel is a drain sense
comparator that is used to sense switch current. When a
preset current level is exceeded, the switch is turned off.
The switch remains off for a period of time set by an
external timing capacitor and then automatically attempts
to restart. If the fault is still present, this cycle repeats until
the fault is removed, thus protecting the MOSFET.
The LT1161 has been specifically designed for harsh
operating environments such as industrial, avionics, and
automotive applications where poor supply regulation
and/or transients may be present. The device will not
sustain damage from supply voltages of –15V to 60V.
■
Industrial Control
■
Avionics Systems
■
Automotive Switches
■
Stepper Motor and DC Motor Control
■
Electronic Circuit Breaker
+
CT
0.1µF
0.1µF
0.1µF
0.1µF
0.01Ω
IRFZ34
24V
INPUTS
1161 F01
IRFZ34
IRFZ34
IRFZ34
RS
0.01Ω
0.01Ω
0.01Ω
LOAD
#1
50µF
50V
LOAD
#2
LOAD
#3
LOAD
#4
DS1
G1
DS2
G2
DS3
G3
DS4
G4
V+V+
T1
T2
T3
T4
GND
GND
IN1
IN2
IN3
IN4
LT1161
Switch Drop vs Load Current
LOAD CURRENT (A)
0
TOTAL DROP (V)
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
04
1161 TA01
1235
Figure 1. Protected Quad High-Side Switch
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
DESCRIPTIO
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2
LT1161
1161fa
1
2
3
4
5
6
7
8
9
10
TOP VIEW
N PACKAGE
20-LEAD PLASTIC DIP
SW PACKAGE
20-LEAD PLASTIC SO
20
19
18
17
16
15
14
13
12
11
GND
TIMER1
INPUT 1
TIMER 2
INPUT 2
TIMER 3
INPUT 3
TIMER 4
INPUT 4
GND
V
+
SENSE 1
GATE 1
SENSE 2
GATE 2
SENSE 3
GATE 3
SENSE 4
GATE 4
V
+
Supply Voltages (Pins 11, 20) ................... –15V to 60V
Input Voltages (Pins 3, 5, 7, 9) ...... (GND – 0.3V) to 15V
Gate Voltages (Pins 12, 14, 16, 18) ........................ 75V
Sense Voltages (Pins 13, 15, 17, 19) .................V
+
±5V
Current (Any Pin).................................................. 50mA
Operating Temperature Range
LT1161C............................................... 0°C to 70°C
LT1161I ............................................ – 40°C to 85°C
Junction Temperature Range (Note 1)
LT1161C.............................................. 0°C to 125°C
LT1161I ......................................... – 40°C to 150°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
θ
JA
= 70°C/ W (N)
θ
JA
= 110°C/ W (S)
ORDER PART
NUMBER
LT1161CN
LT1161CSW
LT1161IN
LT1161ISW
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
S
Supply Current All Channels OFF (Note 2) 3 4.5 6.5 mA
∆I
S(ON)
Delta Supply Current (ON State) Measure Increase in I
S
per Channel 1 1.35 mA
V
INH
Input High Voltage ●2V
V
INL
Input Low Voltage ●0.8 V
I
IN
Input Current V
IN
= 2V ●15 30 50 µA
V
IN
= 5V ●55 110 185 µA
C
IN
Input Capacitance 5pF
V
T(TH)
Timer Threshold Voltage V
IN
= 2V, Adjust V
T
●2.7 3 3.3 V
V
T(CL)
Timer Clamp Voltage V
IN
= 0.8V 3.2 3.5 3.8 V
I
T
Timer Charge Current V
IN
= V
T
= 2V 9 14 20 µA
V
SEN
Drain Sense Threshold Voltage 50 65 80 mV
Temperature Coefficient +0.33 %/°C
I
SEN
Drain Sense Input Current V
+
= 48V, V
SEN
= 65mV 0.5 1.5 µA
V
GATE
– V
+
Gate Voltage Above Supply V
+
= 8V 4 4.5 6 V
V
+
= 12V ●7 8.5 10 V
V
+
= 24V ●10 12 14 V
V
+
= 48V ●10 12 14 V
t
ON
Turn-ON Time V
+
= 24V, V
GATE
> 32V, C
GATE
= 1000pF 100 220 400 µs
t
OFF
Turn-OFF Time V
+
= 24V, V
GATE
< 2V, C
GATE
= 1000pF 75 200 µs
t
OFF(CL)
Current Limit Turn-OFF Time V
+
= 24V, (V
+
– V
SENSE
) → 0.1V, C
GATE
= 1000pF 25 50 µs
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 12V to 48V each channel, unless otherwise noted.
Note 2: Both V
+
pins (11, 20) must be connected together and both
ground pins (1, 10) must be connected together.
3
LT1161
1161fa
Supply Current
TYPICAL PERFORMANCE CHARACTERISTICS
UW
INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
20
18
16
14
12
10
8
6
4
2
040
1161 G01
10 20 30 50
ALL CHANNELS ON
ALL CHANNELS OFF
Automatic Restart Period
INPUT VOLTAGE (V)
0
VGATE – V+
30 50
1161 G02
10 20 40
16
14
12
10
8
6
4
2
0
TJ = 85°C
TJ = –40°C
TJ = 25°C
MOSFET Gate Voltage Above V+
GATE VOLTAGE ABOVE V+ (V)
024 8
GATE DRIVE CURRENT (µA)
100
10
1
0.1
610121416
1161 G03
V+ ≥ 24V
V+ = 8V
V+ = 12V
MOSFET Gate Drive Current
TEMPERATURE (°C)
–50
SUPPLY CURRENT (mA)
–25 025 50
1161 G04
75
20
18
16
14
12
10
8
6
4
2
0100
V
+
= 24V
ALL CHANNELS ON
ALL CHANNELS OFF
Supply Current
TEMPERATURE (°C)
–50
INPUT THRESHOLD VOLTAGE (V)
–25 025 50
1161 G05
75
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4 100
V
+
= 24V
TURN-ON
TURN-OFF
Input Threshold Voltage
TEMPERATURE (°C)
–50
DRAIN SENSE THRESHOLD VOLTAGE (mV)
–25 025 50
1161 G06
75
110
100
90
80
70
60
50
40
30
20
10 100
V
+
= 24V
Drain Sense Threshold Voltage
INPUT VOLTAGE (V)
0
TURN-ON TIME (µs)
500
450
400
350
300
250
200
150
100
50
040
1161 G07
10 20 30 50
IRFZ34
Turn-ON Time Driving MOSFET
INPUT VOLTAGE (V)
0
TURN-OFF TIME (µs)
100
90
80
70
60
50
40
30
20
10
040
1161 G08
10 20 30 50
IRFZ34
NORMAL
CURRENT LIMIT
Turn-OFF Time Driving MOSFET
TEMPERATURE (°C)
–50
10
RESTART PERIOD (ms)
100
1000
25–25 0 50 75 100
1161 G09
V
+
= 24V C
T
= 3.3µF
C
T
= 1µF
C
T
= 0.33µF
C
T
= 0.1µF
4
LT1161
1161fa
Supply Pins: The two supply pins are internally connected
and must also be externally connected. In addition to
providing the operating current for the LT1161, the supply
pins also serve as the Kelvin connection for the current
sense comparators. The supply pins must be connected to
the positive side of the drain sense resistors for proper
operation of the current sense.
Input Pins: The input pins are active high and each pin
activates a separate internal charge pump when switched
ON. The input threshold is TTL/CMOS compatible but may
be taken as high as 15V with or without the supply
powered. Each input has approximately 200mV of hyster-
esis and an internal 75k pull-down resistor.
Gate Pins: The gate pins drive the power MOSFET gates.
When an input is ON, the corresponding gate pin is
pumped approximately 12V above the supply. These pins
have a relatively high impedance when above the rail (the
equivalent of a few hundred kilohms). Care should be
taken to minimize any loading by parasitic resistance to
ground or supply.
Sense Pins: Each sense pin connects to the input of a
supply-referenced comparator with a 65mV nominal off-
set. When a sense pin is taken more than 65mV below
PIN FUNCTIONS
UUU
supply, the MOSFET gate for that channel is driven low and
the corresponding timing capacitor discharged. Each cur-
rent-sense comparator operates completely independently.
The 65mV typical threshold has a +0.33%/°C temperature
coefficient, which closely matches the TC of drain sense
resistors formed from copper PC traces.
Some loads require high in-rush currents. An RC time
delay can be added between the drain sense resistor and
the sense pin to ensure that the current-sense comparator
does not false trigger during start-up (see Applications
Information). However, a maximum of 10kΩ can be in-
serted between a drain sense resistor and the sense pin. If
current sense is not required in any channel, the sense pin
for that channel is tied to supply.
Timer Pins: A timing capacitor C
T
from each timer pin to
ground sets the restart time following overcurrent detec-
tion. C
T
is rapidly discharged to less than 1V and then
recharged by a 14µA nominal current source back to the
timer threshold, whereupon restart is attempted. If current
sense is not required in any channel, the timer pin for that
channel is left open.
Ground Pins: The two ground pins are internally con-
nected and must also be externally connected.
FUNCTIONAL DIAGRA
UU
W
–
+
–
+
–
+
–
+
OSCILLATOR
AND
CHARGE PUMP
1.4V
75k
75k
1.4V
3V
TIMER
14µA
INPUT
65mV
V+
SENSE
GATE
1161 FD
(Each Channel)
5
LT1161
1161fa
OPERATIO
U
When the MOSFET gate voltage is less than 1.4V, the timer
pin is released. The 14µA current source then slowly
charges the timing capacitor back to 3V where the charge
pump again starts to drive the gate pin high. If a fault still
exists, such as a short circuit, the sense comparator
threshold will again be exceeded and the timer cycle will
repeat until the fault is removed (see Figure 2).
The LT1161 gate pin has two states, OFF and ON. In the
OFF state it is held low, while in the ON state it is pumped
to 12V above supply by a self-contained 750kHz charge
pump. The OFF state is activated when either the input pin
is below 1.4V or the timer pin is below 3V. Conversely, for
the ON state to be activated, both the input and timer pins
must be above their thresholds.
If left open, the input pin is held low by a 75k resistor, while
the timer pin is held a diode drop above 3V by a 14µA pull-
up current source. Thus the timer pin automatically re-
verts to the ON state, subject to the input also being high.
The input has approximately 200mV of hysteresis.
The sense pin normally connects to the drain of the power
MOSFET, which returns through a low valued drain sense
resistor to supply. When the gate is ON and the MOSFET
drain current exceeds the level required to generate a
65mV drop across the drain sense resistor, the sense
comparator activates a pull-down NPN which rapidly pulls
the timer pin below 3V. This in turn causes the timer
comparator to override the input pin and activate the gate
pin OFF state, thus protecting the power MOSFET. In order
for the sense comparator to accurately sense MOSFET
drain current, the LT1161 supply pins must be connected
directly to the positive side of the drain sense resistors.
INPUT
1161 F02
OFF NORMAL OVERCURRENT NORMAL
12V
V
+
GATE
0V
3V
0V
TIMER
Figure 2. Timing Diagram
APPLICATIONS INFORMATION
WUUU
Input/Supply Sequencing
There are no input/supply sequencing requirements for
the LT1161. The input may be taken up to 15V with the
supply at 0V. When the supply is turned on with an input
high, the MOSFET turn-on will be inhibited until the timing
capacitor charges to 3V (i.e., for one restart cycle). The
two V
+
pins (11, 20) must always be connected to each
other.
Isolating the Inputs
Operation in harsh environments may require isolation to
prevent ground transients from damaging control logic.
The LT1161 easily interfaces to low cost opto-isolators.
The network shown in Figure 3 ensures that the input will
be pulled above 2V, but not exceed the absolute maximum
LT1161
12V TO 48V
IN
GND
100k
1161 F03
2k
LOGIC
INPUT
1/4 NEC PS2501-4
LOGIC
GND POWER
GROUND
51k
GND
(Each Channel, Refer to Functional Diagram)
Figure 3. Isolating the Inputs
rating, for supply voltages of 12V to 48V over the entire
temperature range. In order to maintain the OFF state, the
opto must have less than 20µA of dark current (leakage)
hot.
6
LT1161
1161fa
APPLICATIONS INFORMATION
WUUU
Drain Sense Configuration
The LT1161 uses supply-referenced current sensing. One
input of each channel’s current-sense comparator is con-
nected to a drain sense pin, while the second input is offset
65mV below the supply bus inside the device. For this
reason, Pins 11 and 20 of the LT1161 must be treated not
only as supply pins, but as the reference inputs for the
current-sense comparators.
Figure 4 shows the proper drain sense configuration for
the LT1161. Note that the sense pin goes to the drain end
of the sense resistor, while the two V
+
pins are tied to each
other and connected to supply at the same point as the
positive ends of the sense resistors. Local supply
decoupling at the LT1161 is important at high input
voltages (see Protecting Against Supply Transients).
The drain sense threshold voltage has a positive tempera-
ture coefficient, allowing PTC sense resistors to be used
(see Printed Circuit Board Shunts). The selection of R
S
should be based on the minimum threshold voltage:
RmV
I
S
SET
=50
Thus the 0.02Ω drain sense resistor in Figure 4 would yield
a minimum trip current of 2.5A. This simple configuration
is appropriate for resistive or inductive loads which do not
generate large current transients at turn-on.
Automatic Restart Period
The timing capacitor C
T
shown in Figure 4 determines the
length of time the power MOSFET is held off following a
current limit trip. Curves are given in the Typical Perfor-
mance Characteristics to show the restart period for
various values of C
T
. For example, C
T
= 0.33µF yields a
50ms restart period.
Defeating Automatic Restart
Some applications are required to remain off after a fault
occurs. When the LT1161 is being driven from CMOS
logic, this can be easily implemented by connecting
resistor R1 between the input and timer pins as shown in
Figure 5. R1 supplies the sustaining current for an SCR
which latches the timer pin low. This prevents the MOSFET
gate from turning ON until the input has been recycled.
Figure 5. Latch-Off Input Network (Auto-Restart Defeated)
Inductive vs Capacitive Loads
Turning on an inductive load produces a relatively benign
ramp in MOSFET current. However, when an inductive
load is turned off, the current stored in the inductor needs
somewhere to decay. A clamp diode connected directly
across each inductive load normally serves this purpose.
If a diode is not employed the LT1161 clamps the MOSFET
gate 0.7V below ground. This causes the MOSFET to
resume conduction during the current decay with (V
+
+
V
GS
+ 0.7V) across it, resulting in high dissipation peaks.
Capacitive loads exhibit the opposite behavior. Any load
that includes a decoupling capacitor will generate a cur-
rent equal to C
LOAD
× (∂V/∂t) during capacitor in-rush.
With large electrolytic capacitors, the resulting current
Figure 4. Drain Sense Configuration
LT1161
T1
V
+
V
+
1161 F04
24V
10µF
100µF
50V
24V, 2A
SOLENOID
IRFZ34
R
S
0.02Ω
(PTC)
C
T
1µFGND
G1
DS1
GND
+
+
LT1161
ON = 5V
OFF = 0V
TIMER
R1
2k
1161 F05
INPUT
5V
CMOS
LOGIC
7
LT1161
1161fa
spike can play havoc with the power supply and false trip
the current-sense comparator.
Turn-on ∂V/∂t is controlled by the addition of the simple
network shown in Figure 6. This network takes advantage
of the fact that the MOSFET acts as a source follower
during turn-on. Thus the ∂V/∂t on the source can be
controlled by controlling the ∂V/∂t on the gate:
∂
∂
V
t
VV
C
TH
=−
×
+
10 1
5
where V
TH
is the MOSFET gate threshold voltage. Multiply-
ing C
LOAD
times this ∂V/∂t yields the value of the current
spike. For example, if V
+
= 24V, V
TH
= 2V, and C1 = 0.1µF,
∂V/∂t = 2.2V/ms, resulting in a 2.2A turn-on spike into
1000µF. The diode and second resistor in the network
ensure fast current limit turn-off.
When turning off a capacitive load, the source of the
MOSFET can “hang up” if the load resistance does not
discharge C
LOAD
as fast as the gate is being pulled down.
If this is the case, a diode may have to be added from
source to gate to prevent V
GS(MAX)
from being exceeded.
and C
D
delay the overcurrent trip for drain currents up to
approximately 10 × I
SET
, above which the diode conducts
and provides immediate turn-off (see Figure 7).
To ensure
proper operation of the timer, C
D
must be
≤
C
T
.
MOSFET DRAIN CURRENT (1 = SET CURRENT)
1
TRIP DELAY TIME (1 = R
D
C
D
)
10
1
0.1
0.01
10 100
L1161 F07
Printed Circuit Board Shunts
The sheet resistance of 1oz. copper clad is approximately
5 × 10
–4
Ω/square with a temperature coefficient of
+0.39%/°C. Since the LT1161 drain sense threshold has a
similar temperature coefficient (+0.33%/°C), this offers
the possibility of nearly zero TC current sensing using
“free” drain sense resistors made out of PC trace material.
A conservative approach is to use 0.02" of width for each
1A of current for 1oz. copper. Combining the LT1161 drain
sense threshold with the 1oz. copper sheet resistance
results in a simple expression for width and length:
Width (1oz. Cu) = 0.02" × I
SET
Length (1oz. Cu) = 2"
The width for 2oz. copper would be halved while the length
would remain the same.
Bends may be incorporated into the resistor to reduce
space; each bend is equivalent to approximately 0.6 ×
width of straight length. Kelvin connections should be
employed by running separate traces from the ends of the
resistors back to the LT1161 V
+
and sense pins. See
Application Note 53 for further information on printed
circuit board shunts.
Adding Current Limit Delay
When capacitive loads are being switched or in very noisy
environments, it is desirable to add delay in the drain
current-sense path to prevent false tripping (inductive
loads normally do not need delay). This is accomplished
by the current limit delay network shown in Figure 6. R
D
LT1161
24V
V
+
V
+
DS
C
D
C1
1161 F06
R
D
(≤10k)
1RFZ24
C
LOAD
CURRENT LIMIT
DELAY NETWORK
∂V/∂t CONTROL NETWORK
1N4148
1N4148
100k 100k
G
+
+
Figure 6. ∂V/∂t Control and Current Limit Delay
Figure 7. Current Limit Delay Time
APPLICATIONS INFORMATION
WUUU
8
LT1161
1161fa
APPLICATIONS INFORMATION
WUUU
Low Voltage/Wide Supply Range Operation
When the supply is <12V, the LT1161 charge pumps do
not produce sufficient gate voltage to fully enhance stan-
dard N-channel MOSFETs. For these applications, logic-
level MOSFETs can be used to extend operation down to
8V. If the MOSFET has a maximum V
GS
rating of 15V or
greater, then it can also be used up to the 60V (absolute
maximum) rating of the LT1161. MOSFETs are available
from both Motorola and Siliconix which meet these
criteria.
Protecting Against Supply Transients
The LT1161 is 100% tested and guaranteed to be safe
from damage with 60V applied between the V
+
and ground
pins. However, when this voltage is exceeded, even for a
few microseconds, the result can be a catastrophic failure.
For this reason
it is imperative that the LT1161 not be
exposed to supply transients above 60V
.
For proper current-sense operation, the V
+
pins are re-
quired to be connected to the positive side of the drain
sense resistors (see Drain Sense Configuration). There-
fore, the best way to prevent supply transients is to ensure
that the supply is adequately decoupled at the point where
the V
+
pins and drain sense resistors meet. Several
hundred microfarads may be required with high current
switches.
When operating voltages approach the 60V absolute maxi-
mum rating of the LT1161, local supply decoupling be-
tween the V
+
pins (11, 20) and ground pins (1, 10) is highly
recommended. A small ferrite bead between the supply
connection and local capacitor can also be effective in
suppressing transients. Note however, that resistance
should not be added in series with the V
+
pins because it
will cause an error in the current sense threshold.
Fault Feedback
Two methods can be used to derive switch status. First,
the timer pin voltage can be monitored to indicate when
the switch is turned off due to current limit. During normal
operation (ON or OFF), the timer voltage is 3.5V and only
during current limit does the voltage drop below 3V.
The second method shown in Figure 8 uses a quad
exclusive-NOR gate to indicate when the output of the
switch has not obeyed the input command (i.e., output low
when it should be high or vice versa). In addition to current
limit, this gives a fault indication if the switch is shorted or
if the load is open.
Figure 8. Fault Feedback Using Exclusive-NOR Gate
24V
R
S
R
OL
ADD FOR
OPEN-LOAD
DETECTION
1161 F08
FAULT
INPUT
1/4 MM74HC266A
100k
LT1161
V
+
V
+
DS
G
IN
LOAD
Low-Side Driving
Although the LT1161 is primarily targeted at high-side
(grounded load) switch applications, it can also be used
for low-side (supply-connected load), or mixed high- and
low-side switch applications. Figures 9a and 9b illustrate
LT1161 switch channels driving low-side power MOSFETs.
Because the LT1161 charge pump tries to pump the gate
of the N-channel MOSFET
above
supply, a clamp zener is
required to prevent the V
GS
(absolute maximum) of the
MOSFET from being exceeded. The LT1161 gate drive is
current limited for this purpose so that no resistance is
needed between the gate pin and zener.
Figure 9a. Low-Side Driver with Load Current Sensing
100µF
IRFZ44
1µF
R
S
0.01Ω
(PTC)
1161 F09a
15V
1N4744
LT1161
12V TO 48V
V
+
V
+
DS
G
4A
LOAD
T
+
9
LT1161
1161fa
APPLICATIONS INFORMATION
WUUU
10µF
R
S1
0.2Ω
R
S2
0.02Ω
1µF
1161 F09b
15V
1N4744
15V
1N4744
1N4148
51Ω
51Ω
51Ω
LT1161
8V TO 24V
V
+
V
+
DS1
G1
G2
DS2
HV
LOAD
HV
LOAD
T1
1µF
T2
IRF630
IRF630
HV
2N2222
–
+
1/2
LT1013
2N2222
Figure 9b. Low-Side Drivers with Two Approaches
for Source Current Sensing
Current sensing for protecting low-side drivers can be
done in several different ways. In the Figure 9a circuit, the
supply voltage for the load is assumed to be within the
supply operating range of the LT1161. This allows the load
to be returned to supply through current-sense resistor
R
S
, providing normal operation of the LT1161 protection
circuitry.
If the load cannot be returned to supply through R
S
, or the
load supply voltage is higher than the LT1161 supply, the
current sense must be moved to the source of the low-side
MOSFET. Figure 9b shows two approaches to source
sensing. On channel 1, current limit occurs when the
voltage across sense resistor R
S1
thresholds the V
BE
of the
NPN transistor, causing the LT1161 drain sense pin to be
pulled down.
The channel 2 circuit of Figure 9b uses an operational
amplifier (must common mode to ground) to level shift the
voltage across R
S2
up to the drain sense pin. This ap-
proach allows the use of a much smaller sense resistor
which could be made from PC trace material. In both
cases, the LT1161 restart timers function the same as in
high-side switch applications.
TYPICAL APPLICATIONS
U
1µF
LT1161
1161 TA05
IRFZ44
IRFZ44
IRFZ44
24V
RS
INPUTS
(MAY BE PARALLELED)
GND
T1
IN1
T2
IN2
T3
IN3
T4
IN4
GND
V+
DS1
G1
DS2
G2
DS3
G3
DS4
G4
V+
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
10µF
50V
OUTPUTS
(MAY BE PARALLELED)
15k
100k
Using an Extra Channel to Do Common Current Limit for Multiple/Paralleled Switches
10
LT1161
1161fa
TYPICAL APPLICATIONS
U
Protected Quad Switch with Mixed Low- and High-Side Driving
0.33µF
MTD3055EL
5.1k 10k
1N4148
1N4148
1N4148
1N4148
LT1161
1161 TA03
0.03Ω
MTD3055EL
0.03Ω
MTD3055EL
0.03Ω
MTD3055EL
0.03Ω
8V TO 28V OPERATING
32V TO 60V SHUTDOWN
30V
1N6011B
INPUTS
GND
T1
IN1
T2
IN2
T3
IN3
T4
IN4
GND
V
+
DS1
G1
DS2
G2
DS3
G3
DS4
G4
V
+
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
10µF
100V
0.33µF
0.33µF
0.33µF
2N3904
+
0.33µF
10µF
MTP36N06E
MTP36N06E
MTP10N40E
MTP10N40E
2k LT1161
1161 TA04
15V
1N4744
0.01Ω
0.01Ω
51Ω
0.4Ω
1N4148
150V
24V
HIGH-SIDE DRIVER
INPUTS
(SEE NOTE 1)
GND
T1
IN1
T2
IN2
T3
IN3
T4
IN4
GND
V
+
DS1
G1
DS2
G2
DS3
G3
DS4
G4
V
+
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
100µF
50V
0.33µF
0.4Ω
LOW-SIDE DRIVER
INPUTS
(SEE NOTE 2)
NOTE 1: THE HIGH-SIDE DRIVER CHANNELS ARE CONFIGURED
TO AUTOMATICALLY RESTART FOLLOWING A FAULT.
NOTE 2: THE LOW-SIDE DRIVER CHANNELS ARE CONFIGURED
TO LATCH OFF FOLLOWING A FAULT. 5V CMOS LOGIC INPUTS
ARE REQUIRED.
51Ω
1N4148
15V
1N4744
2k
2N2222
24V/3A
LOAD
24V/3A
LOAD
150V/1A
LOAD
150V/1A
LOAD
2N2222
+
Protected Quad 1A Automotive Solenoid Driver with Overvoltage Shutdown
11
LT1161
1161fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
TYPICAL APPLICATIONS
U
Protected Quad 2A Industrial Switch with Isolated Inputs and Fault Output
1µF
1µF
0.1µF
+
1µF
1µF
RFD16N05
RFD16N05
RFD16N05
RFD16N05
5.1k
18k
5.1k
5.1k
5.1k
5.1k
2k
4N28
NEC PS2501-4
MM74HC266A
LT1161
1161 TA02
0.015Ω
24V
24V
FAULT
OUTPUT
5.6V
1N5994B
INPUTS
0.015Ω
0.015Ω
0.015Ω
GND
T1
IN1
T2
IN2
T3
IN3
T4
IN4
GND
V+
DS1
G1
DS2
G2
DS3
G3
DS4
G4
V+
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LOAD
#1
50µF
50V
100k
100k
100k
100k
LOAD
#2
LOAD
#3
LOAD
#4
2N3904
N Package
20-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
N20 0405
.020
(0.508)
MIN
.120
(3.048)
MIN
.125 – .145
(3.175 – 3.683)
.065
(1.651)
TYP
.045 – .065
(1.143 – 1.651)
.018 ± .003
(0.457 ± 0.076)
.005
(0.127)
MIN
.008 – .015
(0.203 – 0.381)
.300 – .325
(7.620 – 8.255)
.325 +.035
–.015
+0.889
–0.381
8.255
()
.255 ± .015*
(6.477 ± 0.381)
1.060*
(26.924)
MAX
12345678910
19 1112
131416 1517
18
20
NOTE:
1. DIMENSIONS ARE INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
.100
(2.54)
BSC
PACKAGE DESCRIPTION
U
12
LT1161
1161fa
LT 0406 REV A • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 1994
PACKAGE DESCRIPTION
U
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
SW Package
20-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
S20 (WIDE) 0502
NOTE 3
.496 – .512
(12.598 – 13.005)
NOTE 4
20
N
19 18 17 16 15 14 13
12345678
.394 – .419
(10.007 – 10.643)
910
N/2
1112
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC
.014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
123 N/2
.050 BSC
.030 ±.005
TYP
.005
(0.127)
RAD MIN
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1158 Half-Bridge N-Channel Power MOSFET Driver Single Input, Continuous Current Protection and Internal Charge
Pump for DC Operation
LT1336 Half-Bridge N-Channel Power MOSFET Driver with Onboard Boost Regulator to Supply the High Side Driver
Boost Regulator
LT1910 Protected High Side MOSFET Driver V
IN
= 8V to 48V, Protected from –15V to 60V Transients, Auto
Restart, Fault Indication
LTC1922-1 Synchronous Phase Modulated Full-Bridge Controller Output Power from 50W to Kilowatts, Adaptive Direct Sense Zero
Voltage Switching Compensates for External Component Tolerances
LTC1923 Full-Bridge Controller for Thermoelectric Coolers High Efficiency, Adjustabe Slew Rate Reduces EMI
5mm × 5mm QFN and 28-Pin SSOP
