64-Position OTP Digital Potentiometer AD5171 APPLICATIONS For applications that program the AD5171 in factories, Analog Devices offers device programming software that operates across Windows(R) 95 to XP(R) platforms including Windows NT(R). This software application effectively replaces the need for external I2C controllers or host processors and therefore significantly reduces users' development time. An AD5171 evaluation kit is available, which includes the software, connector, and cable that can be converted for factory programming applications. The AD5171 is available in a compact SOT-23-8 package. All parts are guaranteed to operate over the automotive temperature range of -40C to +125C. Besides its unique OTP feature, the AD5171 lends itself well to other general-purpose digital potentiometer applications due to its temperature performance, small form factor, and low cost. Systems calibrations Electronics level settings Mechanical potentiometers and trimmers(R) replacements Automotive electronics adjustments Gain control and offset adjustments Transducer circuits adjustments Programmable filters up to 1.5 MHz BW SCL SDA W AD0 B WIPER REGISTER VDD GENERAL DESCRIPTION GND The AD5171 is a 64-position, one-time programmable (OTP) digital potentiometer2 that uses fuse link technology to achieve the memory retention of the resistance setting function. OTP is a cost-effective alternative over the EEMEM approach for users who do not need to reprogram new memory settings in the digital potentiometer. This device performs the same electronic adjustment function as most mechanical trimmers and variable resistors. The AD5171 is programmed using a 2-wire I2C compatible digital control. It allows unlimited adjustments before permanently setting the resistance value. During the OTP activation, a permanent fuse blown command is sent after the final value is determined, therefore freezing the wiper position at a given setting (analogous to placing epoxy on a A I2C INTERFACE AND CONTROL LOGIC FUSE LINK AD5171 03437-0-001 64 positions OTP (one-time programmable)1 set-and-forget resistance setting--low cost alternative over EEMEM Unlimited adjustments prior to OTP activation 5 k, 10 k, 50 k, 100 k end-to-end resistance Low tempco 5 ppm/oC in potentiometer mode Low tempco 35 ppm/C in rheostat mode Compact standard SOT-23-8 package Low power, IDD = 10 A max Fast settling time, ts = 5 s typ in power-up I2C compatible digital interface Computer software replaces C in factory programming applications Full read/write of wiper register Extra I2C device address pin Power-on preset to midscale 6 V one-time programming voltage Low operating voltage, 2.7 V to 5.5 V OTP validation check function Automotive temperature range -40C to +125C mechanical trimmer). When this permanent setting is achieved, the value does not change regardless of supply variations or environmental stresses under normal operating conditions. To verify the success of permanent programming, Analog Devices patterned the OTP validation such that the fuse status can be discerned from two validation bits in read mode. Figure 1. Functional Block Diagram W 1 VDD 2 AD5171 8 A 7 B TOP VIEW 6 AD0 (Not to Scale) 5 SDA SCL 4 GND 3 03437-0-002 FEATURES Figure 2. Pin Configuration 1 One-time programmable (OTP)--Unlimited adjustments before permanent setting. 2 The terms digital potentiometer and RDAC are used interchangeably. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD5171 TABLE OF CONTENTS Electrical Characteristics ................................................................. 3 Software Programming ............................................................. 14 Absolute Maximum Ratings............................................................ 5 I2C Controller Programming.................................................... 15 ESD Caution.................................................................................. 5 Controlling Two Devices on One Bus ..................................... 16 Pin Configuration and Functional Descriptions.......................... 6 Applications..................................................................................... 17 Typical Performance Characteristics ............................................. 7 DAC.............................................................................................. 17 Theory of Operation ...................................................................... 11 Gain Control Compensation .................................................... 17 One-Time Programming (OTP) .............................................. 11 Programmable Voltage Source with Boosted Output............ 17 Power Supply Considerations ................................................... 11 Level Shifting for Different Voltage Operation ...................... 17 ESD Protection ........................................................................... 12 Resistance Scaling ...................................................................... 17 Terminal Voltage Operating Range.......................................... 12 Resolution Enhancement .......................................................... 18 Power-Up/Power-Down Sequences......................................... 12 RDAC Circuit Simulation Model............................................. 18 Determining the Variable Resistance and Voltage ................ 12 AD5171 Evaluation Board ........................................................ 19 Rheostat Mode Operation......................................................... 12 Outline Dimensions ....................................................................... 20 Potentiometer Mode Operation ............................................... 13 Ordering Guide .......................................................................... 20 Controlling the AD5171 ............................................................ 14 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD5171 ELECTRICAL CHARACTERISTICS 5 k, 10 k, 50 k, and 100 k versions, VDD = 3 V to 5 V 10%, VA = VDD, VB = 0 V, -40C < TA < +125C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all RDACs) Resolution Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance6 A, B Capacitance6 W Common-Mode Leakage DIGITAL INPUTS Input Logic High (SDA and SCL) Input Logic Low (SDA and SCL) Input Logic High (AD0) Input Logic Low (AD0) Input Current Input Capacitance6 DIGITAL OUTPUTS Output Logic Low (SDA) Three-State Leakage Current (SDA) Output Capacitance6 POWER SUPPLIES Power Supply Range OTP Power Supply7 Supply Current OTP Supply Current8 Power Dissipation9 Power Supply Sensitivity Symbol Conditions Min Typ1 Max Unit R-DNL RWB, VA = no connect, RAB = 10 k, 50 k, and 100 k RWB, VA = no connect, RAB = 5 k RWB, VA = no connect, RAB = 10 k, 50 k, and 100 k RWB, VA = no connect, RAB = 5 k -0.5 0.1 +0.5 LSB -1 -1.5 0.25 0.35 +1 +1.5 LSB LSB -1.5 -30 0.5 +1.5 +30 LSB % ppm/C R-INL RAB/RAB (RAB/RAB)/T RW N DNL INL (VW/VW)/T VWFSE VWFSE VWZSE VA, B, W CA, B CW ICM VIH VIL VIH VIL IIL CIL VOL IOZ COZ VDD VDD_OTP IDD IDD_OTP PDISS PSSR 35 60 VDD = 5 V -0.5 -1 Code = 0x20 Code = 0x3F, RAB = 10 k, 50 k, and 100 k Code = 0x3F, RAB= 5 k Code = 0x00, RAB=10 k, 50 k, and 100 k Code = 0x00, RAB = 5 k VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 0 Bits LSB LSB ppm/C LSB 0 1 LSB LSB 2 LSB VDD 25 V pF 55 pF 1 nA -1 0.1 0.2 5 -0.5 -1.5 0 0.5 0 With respect to GND f = 1 MHz, measured to GND, Code = 0x20 f = 1 MHz, measured to GND, Code = 0x20 VA = VB = VDD/2 115 6 +0.5 +1 VDD + 0.5 0.7 VDD -0.5 3.0 0 0.3 VDD VDD 1.0 1 3 IOL = 6 mA VIN = 0 V or 5 V 0.4 1 V A pF 4 5.5 6.5 10 0.02 +0.001 0.04 +0.025 V V A mA mW %/% 3 TA = 25C VIH = 5 V or VIL = 0 V VDD_OTP = 6 V, TA = 25C VIH = 5 V or VIL = 0 V, VDD = 5 V 2.7 6 100 -0.025 Rev. 0 | Page 3 of 20 V V V V A pF AD5171 Parameter DYNAMIC CHARACTERISTICS 6, 10, 11 Bandwidth -3 dB Symbol Conditions Total Harmonic Distortion BW_5k BW_10k BW_50k BW_100k THD Adjustment Settling Time tS1 OTP Settling Time12 tS_OTP Power-Up Settling Time--Post Fuses Blown tS2 Resistor Noise Voltage eN_WB RAB = 5 k, Code = 0x20 RAB = 10 k, Code = 0x20 RAB = 50 k, Code = 0x20 RAB = 100 k, Code = 0x20 VA = 1 V rms, RAB = 10 k, VB = 0 V DC, f = 1 kHz VA= 5 V 1 LSB error band, VB = 0 V, measured at VW VA = 5 V 1 LSB error band, VB = 0 V, measured at VW VA = 5 V 1 LSB error band, VB = 0 V, measured at VW RAB = 5 k, f = 1 kHz, Code = 0x20 RAB = 10 k, f = 1 kHz, Code = 0x20 INTERFACE TIMING CHARACTERISTICS (Apply to all parts6, 12) SCL Clock Frequency tBUF Bus Free Time between Start and Stop tHD;STA Hold Time (Repeated Start) fSCL t1 t2 tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Start Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for Stop Condition t3 t4 t5 t6 t7 t8 t9 t10 Typ1 Min Max 1500 600 110 60 0.05 kHz kHz kHz kHz % 5 s 400 ms 5 s 8 nV/Hz 12 nV/Hz 400 After this period, the first clock pulse is generated 1.3 0.6 1.3 0.6 0.6 50 0.9 0.1 0.3 0.3 0.6 1 Unit kHz s s s s s s s s s s Typicals represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Different from operating power supply, power supply for OTP is used one-time only. 8 Different from operating current, supply current for OTP lasts approximately 400 ms for one-time needed only. 9 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 10 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 11 All dynamic characteristics use VDD = 5 V. 12 Different from settling time after fuse is blown. The OTP settling time occurs once only. 2 t6 t9 t8 SCL t4 t2 t3 t5 t10 t7 t9 SDA t1 P S P Figure 3. Interface Timing Diagram Rev. 0 | Page 4 of 20 03437-0-024 t8 AD5171 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDD to GND VA, VB, VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB 1 k, A open)1 IWA Continuous (RWA 1 k, B open)1 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ max) Storage Temperature Lead Temperature (Soldering, 10 sec) Vapor Phase (60 sec) Infrared (15 sec) Thermal Resistance2 JA Rating -0.3, +7 V GND, VDD 20 mA 5 mA 5 mA 0 V, VDD -40C to +125C 150C -65C to +150C 300C 215C 220C 230C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1 Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2 Package Power Dissipation = (TJ max - TA) / JA ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 20 AD5171 W 1 VDD 2 AD5171 8 A 7 B TOP VIEW 6 AD0 (Not to Scale) 5 SDA SCL 4 GND 3 03437-0-003 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Figure 4. SOT-23-8 Table 3. Pin Function Descriptions Pin No. 1 2 Mnemonic W VDD 3 4 5 6 7 8 GND SCL SDA AD0 B A Description Wiper Terminal W. GND VW VDD. Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, VDD needs to be a minimum of 6 V and 100 mA driving capability. Common Ground. Serial Clock Input. Requires pull-up resistor. Serial Data Input/Output. Requires pull-up resistor. I2C Device Address Bit. Allows maximum of two AD5171s to be addressed. Resistor Terminal B. GND VB VDD. Resistor Terminal A. GND VA VDD. Rev. 0 | Page 6 of 20 AD5171 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.10 VDD = 5V VDD = 5V 0.08 -40C 0.04 0.02 0 -0.02 -0.04 +125C -0.06 +25C -0.10 0 8 16 24 32 0.04 +125C 0.02 0 -0.02 -0.04 +25C -40C -0.06 -0.08 40 48 56 64 CODE (DECIMAL) -0.10 03437-0-004 -0.08 0.06 0 8 16 24 32 40 48 56 03437-0-007 0.06 POTENTIOMETER MODE DNL (LSB) RHEOSTAT MODE INL (LSB) 0.08 64 CODE (DECIMAL) Figure 5. R-INL vs. Code vs. Temperature Figure 8. DNL vs. Code vs. Temperature 0.10 0 VDD = 5V -0.1 +25C 0.06 +125C -0.2 0.04 0.02 FSE (LSB) 0 -0.02 VDD = 5V -0.3 -0.4 VDD = 3V -40C -0.04 -0.5 -0.06 -0.6 -0.10 0 8 16 24 32 40 48 56 64 CODE (DECIMAL) 03437-0-005 -0.08 -0.7 -40 -20 0 20 40 60 80 100 120 140 100 120 140 TEMPERATURE (C) Figure 6. R-DNL vs. Code vs. Temperature 03437-0-008 RHEOSTAT MODE DNL (LSB) 0.08 Figure 9. Full-Scale Error 0.10 0.6 VDD = 5V 0.5 0.06 0.04 +25C 0.4 +125C ZSE (LSB) 0.02 0 -0.02 -40C VDD = 3V 0.3 VDD = 5V 0.2 -0.04 -0.06 0.1 -0.10 0 8 16 24 32 40 48 CODE (DECIMAL) 56 64 Figure 7. INL vs. Code vs. Temperature 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) Figure 10. Zero-Scale Error Rev. 0 | Page 7 of 20 03437-0-009 -0.08 03437-0-006 POTENTIOMETER MODE INL (LSB) 0.08 AD5171 6 10 0 VDD = 5V 0x20 1 MAGNITUDE (dB) IDD SUPPLY CURRENT (A) -6 VDD = 3V 0x10 -12 0x08 -18 0x04 -24 0x02 -30 0x01 -36 0x00 03437-0-013 -42 -48 -20 0 20 40 60 80 100 120 140 TEMPERATURE (C) -54 100 03437-0-010 0.1 -40 180 6 160 0 140 -6 MAGNITUDE (dB) 120 100 80 60 40 1M 10M -12 -18 -24 0x3F 0x20 0x10 0x08 0x04 0x02 -30 0x01 -36 0 -42 -20 -48 -40 0 8 16 24 32 40 48 56 64 CODE (DECIMAL) -54 100 0x00 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. Rheostat Mode Tempco (RAB/RAB)/ T vs. Code 03437-0-001 20 03437-0-011 Figure 15. Gain vs. Frequency vs. Code, RAB = 10 k 6 25 0 0x3F 0x20 20 MAGNITUDE (dB) -6 15 10 5 -12 -18 -24 -30 -36 0x10 0x08 0x04 0x02 0x01 -42 0 -48 0 8 16 24 32 40 48 56 64 CODE (DECIMAL) -54 100 03437-0-012 -5 0x00 1k 10k 100k FREQUENCY (Hz) Figure 16. Gain vs. Frequency vs. Code, RAB = 50 Figure 13. Potentiometer Mode Tempco (VW /VW)/ T vs. Code Rev. 0 | Page 8 of 20 1M 03437-0-015 RHEOSTAT MODE TEMPCO (ppm/C) 10k 100k FREQUENCY (Hz) Figure 14. Gain vs. Frequency vs. Code, RAB = 5 k Figure 11. Supply Current vs. Temperature RHEOSTAT MODE TEMPCO (ppm/C) 1k AD5171 6 0x20 -6 MAGNITUDE (dB) VDD = 5.5V VA = 5.5V VB = GND 0x3F 0 VW = 5V/DIV 0x08 -18 0x3F fCLK = 400kHz 0x10 -12 DATA 0x00 0x04 -24 0x02 -30 SCL = 5V/DIV 0x01 -36 -42 0x00 1k 10k 100k 5V 03437-0-016 -54 100 1M FREQUENCY (Hz) 5V 5s 03437-0-019 -48 Figure 20. Settling Time Figure 17. Gain vs. Frequency vs. Code, RAB = 100 k TA = 25C CODE = 0x20 VA = 2.5V, VB = 0V VDD = 5.5V VA = 5.5V VB = GND 60 fCLK = 100kHz VDD = 5V DC 1.0V p-p AC VW = 50mV/DIV DATA 0x20 0x1F VDD = 3V DC 0.6V p-p AC 40 20 10k 100k 50mV 03437-0-017 1k 1M FREQUENCY (Hz) 200ns Figure 21. Midscale Glitch Energy Figure 18. PSRR vs. Frequency fCLK = 100kHz VDD = 5.5V VA = 5.5V VB = GND 5V 03437-0-020 SCL = 5V/DIV 0 100 OTP PROGRAMMED AT MS VDD = 5.5V VA = 5.5V RAB = 10k VW = 10mV/DIV VW = 1V/DIV 10mV 5V 500ns 1V Figure 19. Digital Feedthrough vs. Time 5V 5s Figure 22. Power-Up Settling Time, after Fuses Blown Rev. 0 | Page 9 of 20 03437-0-021 VDD = 5V/DIV SCL = 5V/DIV 03437-0-018 POWER SUPPLY REJECTION RATIO (-dB) 80 AD5171 10.00 RAB = 5k 1.00 RAB = 10k RAB = 50k 0.10 RAB = 100k 0.01 0 8 16 24 32 40 48 CODE (DECIMAL) 56 64 03437-0-022 THEORETICAL IWB_MAX (mA) VA = VB = OPEN TA = 25C Figure 23. IWB_max vs. Code Rev. 0 | Page 10 of 20 AD5171 THEORY OF OPERATION The AD5171 allows unlimited 6-bit adjustments, except for onetime programmable, set-and-forget resistance setting. OTP technology is a proven cost-effective alternative over EEMEM in one-time memory programming applications. AD5171 employs fuse link technology to achieve the memory retention of the resistance setting function. It comprises six data fuses, which control the address decoder for programming the RDAC, one user mode test fuse for checking setup error, and one programming lock fuse for disabling any further programming once the data fuses are blown. which prohibits further programming. As a result, users must discard the unit. This error status can also occur if the OTP supply voltage droops below 6 V, the OTP supply current is limited, or both the voltage and current ramp times are slow. If the output and stored code match, the programming lock fuse is blown so that no further programming is possible. In the meantime, E1 and E0 issue 11, indicating the lock fuse is blown successfully. All the fuse latches are enabled at power-on, and therefore the output corresponds to the stored setting from this point on. Figure 24 shows a detailed functional block diagram. ONE-TIME PROGRAMMING (OTP) A Table 4. Validation Status E1 0 0 E0 0 1 1 0 1 1 Status Ready for Programming Test Fuse Not Blown Successfully. For factory setup checking purpose only. Users should not see these combinations. Fatal Error. Some fuses are not blown. Do not retry. Dicard the unit. Successful. No further programming is possible. This section discusses the fuse operation in detail. When the OTP T bit is set, the internal clock is enabled. The program attempts to blow a test fuse. The operation stops if the test fuse is not blown properly. The validation Bits E1 and E0 show 01. This status is intended for factory setup checking purposes only; users should not see this status. If the test fuse is blown successfully, the data fuses are programmed next. The six data fuses are programmed in six clock cycles. The output of the fuses is compared with the code stored in the DAC register. If they do not match, E1 and E0 of 10 are issued as fatal error and the operation stops. Users should never try blowing the fuses more than once because the fuse structure may have changed, SDA MUX DAC REG. I2C INTERFACE DECODER W B COMPARATOR FUSES EN FUSE REG. ONE-TIME PROGRAM/TEST CONTROL BLOCK 03437-0-025 The device control circuit has two validation bits, E1 and E0, that can be read back in the read mode for checking the programming status as shown in Table 4. Users should always read back the validation bits to ensure that the fuses are properly blown. SCL Figure 24. Detailed Functional Block Diagram POWER SUPPLY CONSIDERATIONS To minimize the package pin count, both the one-time programming and normal operating voltage supplies are applied to the same VDD terminal of the AD5171. The AD5171 uses fuse link technology that requires 6 V to blow the internal fuses to achieve a given setting. The user has only one opportunity to blow the fuses. Once programming is completed, power supply voltage must be reduced to the normal operating range of 2.7 V to 5.5 V. Such dual voltage requires isolation between supplies. The fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 6 V and must provide 100 mA transient current for 400 ms for successful one-time programming. Once programming is complete, the 6 V supply must be removed to allow normal operation of 2.7 V to 5.5 V. Figure 25 shows the simplest implementation using a jumper. This approach saves one voltage supply, but draws additional current and requires manual configuration. CONNECT J1 HERE FOR OTP 6V R1 50k R2 250k J1 5V C1 1F C2 1nF VDD AD5171 CONNECT J1 HERE AFTER OTP Figure 25. Power Supply Requirement Rev. 0 | Page 11 of 20 03437-0-030 Prior to OTP activation, the AD5171 presets to midscale during power on. After the wiper is set at the desired position, the resistance can be permanently set by programming the T bit to high along with the proper coding (Table 7). Note that the fuse link technology requires 6 V to blow the internal fuses to achieve a given setting. The user has only one opportunity to blow the fuses. Once programming is completed, the power supply voltage must be reduced to the normal operating range of 2.7 V to 5.5 V. AD5171 An alternate approach in 3.5 V to 5.5 V systems adds a signal diode between the system supply and the OTP supply for isolation, as shown in Figure 26. ESD PROTECTION Digital inputs SDA and SCL are protected with a series input resistor and parallel Zener ESD structures (Figure 28). APPLY FOR OTP ONLY 6V 340 LOGIC 3.5V-5.5V C2 1nF VDD AD5171 Figure 28. ESD Protection of Digital Pins 03437-0-031 C1 1F 03437-0-027 D1 TERMINAL VOLTAGE OPERATING RANGE Figure 26. Isolating the 6 V OTP Supply from the 3.5 V to 5.5 V Normal Operating Supply. The 6 V supply must be removed once OTP is complete. 6V APPLY FOR OTP ONLY There are also ESD protection diodes between VDD and the RDAC terminals. The VDD of the AD5171 therefore defines their voltage boundary conditions, see Figure 29. Supply signals present on terminals A, B, and W that exceed VDD are clamped by the internal forward-biased diodes and should be avoided. R1 VDD 10k C1 1F P1 = P2 = FDV302P, NDS0610 C2 1nF VDD A AD5171 W B GND Figure 27. Isolating the 6 V OTP Supply from the 2.7 V Normal Operating Supply. The 6 V supply must be removed once OTP is complete. For users who operate their systems at 2.7 V, it is recommended to use the bidirectional low-threshold P-Ch MOSFETs for the supplies isolation. Figure 27 assumes the 2.7 V system voltage is first applied. The gates of P1 and P2 are pulled to ground, which turns on P1 and subsequently P2. As a result, the VDD of the AD5171 approaches 2.7 V. When the AD5171 setting is found, the factory tester applies the 6 V to VDD and also to the gates of P1 and P2 to turn them off. While the OTP command is executing at this time to program AD5171, the 2.7 V source is therefore protected. Once the OTP is complete, the tester withdraws the 6 V, and AD5171 setting is permanently fixed. The AD5171 achieves the OTP function by blowing internal fuses. Users should always apply the 6 V one-time programming voltage requirement at the first program command. Noncompliance with this requirement may change the fuse structures, rendering programming inoperable. Figure 29. Maximum Terminal Voltages Set by VDD POWER-UP/POWER-DOWN SEQUENCES Similarly, because of the ESD protection diodes, it is important to power VDD first before applying any voltages to terminals A, B, and W. Otherwise, the diode is forward-biased such that VDD is powered unintentionally and may affect the remainder of the users' circuits. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD. Similarly, VDD should be powered down last. DETERMINING THE VARIABLE RESISTANCE AND VOLTAGE Rheostat Mode Operation If only the W-to-B or W-to-A terminals are used as variable resistors, the unused terminal can be opened or shorted with W. This operation is called rheostat mode (Figure 30). Poor PCB layout introduces parasitics, which may also affect the fuse programming. Therefore, it is recommended to add a 1 nF ceramic capacitor in parallel with a 1 F tantalum capacitor as close as possible to the VDD pin. These capacitors provide the extra transient currents that make the PCB layout variations less sensitive to the OTP programming errors. A A W B A W B W B 03437-0-050 P2 03437-0-029 P1 03437-0-052 2.7V Figure 30. Rheostat Mode Configuration The nominal resistance (RAB) of the RDAC has 64 contact points accessed by the wiper terminal, plus the B terminal contact if RWB is considered. The 6-bit data in the RDAC latch is Rev. 0 | Page 12 of 20 AD5171 The typical distribution of the resistance tolerance from device to device is process lot dependent; it is possible to have 30% tolerance. decoded to select one of the 64 settings. Assuming that a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Such a connection yields a minimum of 60 resistance between terminals W and B because of the 60 wiper contact resistance. The second connection is the first tap point, which corresponds to 219 (RWB = 1 x RAB/63 + RW) for data 0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10060 ((63) x RAB/63 + RW). Figure 31 shows a simplified diagram of the equivalent RDAC circuit. The general equation determining RWB is RWB (D) = D x RAB + RW 63 A D5 D4 D3 D2 D1 D0 RS RS W (1) where: Figure 31. AD5171 Equivalent RDAC Circuit Table 5. RWB vs. Codes; RAB = 10 k and the A Terminal Is Opened RWB () 10060 5139 219 60 B 03437-0-026 D is the decimal equivalent of the 6-bit binary code. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on-resistance of the internal switch. D (Dec) 63 32 1 0 RS RDAC LATCH AND DECODER Potentiometer Mode Operation If all three terminals are used, the operation is called the potentiometer mode. The most common configuration is the voltage divider operation (Figure 32). Output State Full-Scale (RAB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance) VI A B Figure 32. Potentiometer Mode Configuration Ignoring the effect of the wiper resistance, the transfer function Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a complementary resistance RWA. When these terminals are used, the B terminal can be opened or shorted to W. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is RWA ( D) = 63 - D x R AB + RW 63 Table 6. RWA vs. Codes; RAB =10 k and B Terminal Is Opened D (Dec) 63 32 1 0 RWA () 60 4980 9901 10060 Output State Full-Scale Midscale 1 LSB Zero-Scale VO 03437-0-051 W Since a finite wiper resistance of 60 is present in the zeroscale condition, care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. is simply VW (D) = D VA 63 (3) A more accurate calculation, which includes the wiper resistance effect, yields D R AB + RW VW ( D) = 63 VA R AB + 2 RW (2) (4) Unlike in rheostat mode operation where the absolute tolerance is high, potentiometer mode operation yields an almost ratiometric function of D/63 with a relatively small error contributed by the RW terms, and therefore the tolerance effect is almost cancelled. Although the thin film step resistor RS and CMOS switches resistance RW have very different temperature coefficients, the ratiometric adjustment also reduces the overall temperature coefficient effect to 5 ppm/C, except at low value codes where RW dominates. Rev. 0 | Page 13 of 20 AD5171 CONTROLLING THE AD5171 There are two ways of controlling the AD5171. Users can either program the devices with computer software or external I2C controllers. Software Programming Due to the advantage of the one-time programmable feature, users may consider programming the device in the factory before shipping to end users. ADI offers device programming software that can be implemented in the factory on PCs running Windows 95 to XP platforms. As a result, external controllers are not required, which significantly reduces development time. The program is an executable file that does not require any programming languages or user programming skills. It is easy to set up and use. Figure 33 shows the software interface. The software can be downloaded from www.analog.com. Read To read the validation bits and data out from the device, the user may simply press the Read button. The user may also set the bit pattern in the upper screen and press the Run button. The format of reading data out from the device is shown in Table 8. To apply the device programming software in the factory, users need to modify a parallel port cable and configure Pins 2, 3, 15, and 25 for SDA_write, SCL, SDA_read, and DGND, respectively, for the control signals (Figure 34). Users should also lay out the PCB of the AD5171 with SCL and SDA pads, as shown in Figure 35, such that pogo pins can be inserted for the factory programming. 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 R3 SCL 100 R2 READ 100 SDA R1 WRITE 100 03437-0-033 Potentiometer mode operations include others such as op amp input, feedback resistor networks, and other voltage scaling applications. A, W, and B terminals can in fact be input or output terminals provided that |VAB|, |VWA|, and |VWB| do not exceed VDD to GND. Figure 34. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND W VDD GND SCL Write The AD5171 starts at midscale after power-up prior to the OTP programming. To increment or decrement the resistance, the user may simply move the scrollbar on the left. To write any specific values, the user should use the bit pattern control in the upper screen and press the Run button. The format of writing data to the device is shown in Table 7. Once the desired setting is found, the user may press the Program Permanent button to blow the internal fuse links for permanent setting. The user may also set the programming bit pattern in the upper screen and press the Run button to achieve the same result. A B AD0 SDA 03437-0-034 Figure 33. AD5171 Computer Software Interface Figure 35. Recommended AD5171 PCB Layout. The SCL and SDA pads allow pogo pins to be inserted so that signals can be communicated through the parallel port for programming (Figure 34). Rev. 0 | Page 14 of 20 AD5171 Table 7. SDA Write Mode Bit Format S 0 1 0 1 1 0 AD0 Slave Address Byte 0 A T X X X X X Instruction Byte X X A X X D5 D4 D3 D2 Data Byte D1 D0 D0 A A P Table 8. SDA Read Mode Bit Format S 0 1 0 1 1 0 Slave Address Byte AD0 1 A E1 E0 D5 D4 D3 Data Byte D2 D1 P Table 9. SDA Bits Definitions and Descriptions Bit S P A AD0 X T D5, D4, D3, D2, D1, D0 E1, E0 0, 0 0, 1 Description Start Condition. Stop Condition. Acknowledge. I2C Device Address Bit. Allows maximum of two AD5171s to be addressed. Don't Care. OTP Programming Bit. Logic 1 programs wiper position permanently. Data Bits. OTP Validation Bits. Ready to Program. Test Fuse Not Blown Successfully. For factory setup checking purpose only. Users should not see these combinations. Fatal Error. Do not retry. Discard the unit. Programmed Successfully. No further adjustments possible. 1, 0 1, 1 I2C Controller Programming Write Bit Pattern Illustrations 1 9 9 1 1 9 SDA 0 1 1 0 0 1 AD0 R/W 0 X X X X X X X ACK. BY AD5171 FRAME 1 SLAVE ADDRESS BYTE START BY MASTER X X D5 D4 D3 D2 D1 ACK. BY AD5171 03437-0-035 SCL D0 ACK. BY AD5171 FRAME 2 INSTRUCTION BYTE FRAME 1 DATA BYTE STOP BY MASTER Figure 36. Writing to the RDAC Register 9 9 1 1 9 SDA 0 1 0 1 0 1 1 AD0 R/W X X X X X X X ACK. BY AD5171 START BY MASTER X X D4 D5 D3 D2 D1 ACK. BY AD5171 FRAME 1 SLAVE ADDRESS BYTE ACK. BY AD5171 FRAME 2 INSTRUCTION BYTE FRAME 1 DATA BYTE STOP BY MASTER Figure 37. Activating One-Time Programming Read Bit Pattern Illustration 9 1 9 SCL SDA 0 1 0 1 1 0 AD0 R/W E1 E0 D5 D4 D3 D2 ACK. BY AD5171 START BY MASTER FRAME 1 SLAVE ADDRESS BYTE D0 NO ACK. BY MASTER FRAME 2 RDAC REGISTER Figure 38. Reading Data from RDAC Register Rev. 0 | Page 15 of 20 D1 03437-0-037 1 D0 03437-0-036 1 SCL STOP BY MASTER AD5171 1. The master initiates data transfer by establishing a start condition, which is when SDA goes from high-to-low while SCL is high (Figure 36 and Figure 37). The following byte is the slave address byte, which consists of the 6 MSBs as a slave address defined as 010110. The next bit is AD0, which is an I2C device address bit. Depending on the states of their AD0 bits, two AD5171 can be addressed on the same bus (Figure 39). The last LSB is the R/W bit, which determines whether data is read from or written to the slave device. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the 9th clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. 3. The write operation contains one more instruction byte than the read operation. The instruction byte in the write mode follows the slave address byte. The MSB of the instruction byte labeled T is the one-time programming bit. After acknowledging the instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an Acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (Figure 36). 4. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In the write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (Figure 36 and Figure 37). In the read mode, the master issues a No Acknowledge for the 9th clock pulse, i.e., the SDA line remains high. The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (Figure 38). A repeated write function gives the user flexibility to update the RDAC output a number of times, except after permanent programming, addressing, and instructing the part only once. During the write cycle, each data byte updates the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output updates after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte updates the output of the selected slave device. If different instructions are needed, the write mode has to be started with a new slave address, instruction, and data bytes. Similarly, a repeated read function of the RDAC is also allowed. CONTROLLING TWO DEVICES ON ONE BUS Figure 39 shows two AD5171 devices on the same serial bus. Each has a different slave address since the state of each AD0 pin is different. This allows each device to be operated independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C compatible interface. In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (slight difference with the write mode; there are eight data bits followed by a No Acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (Figure 38). Rev. 0 | Page 16 of 20 5V Rp Rp SDA MASTER SCL SDA SCL AD0 AD5171 5V SDA SCL AD0 AD5171 Figure 39. Two AD5171 Devices on One Bus 03437-0-038 For users who prefer to use external controllers, the AD5171 can be controlled via an I2C compatible serial bus; the part is connected to this bus as slave device. Referring to Figure 36, Figure 37, and Figure 38, the 2-wire I2C serial bus protocol operates as follows: AD5171 APPLICATIONS DAC It is common to buffer the output of the digital potentiometer as a DAC unless the load is much larger than RWB. The buffer serves the purpose of impedance conversion as well as delivering higher current, which may be needed. LEVEL SHIFTING FOR DIFFERENT VOLTAGE OPERATION 5V AD5171 5V When users need to interface a 2.5 V controller with the AD5171, a proper voltage level shift must be used so that the digital potentiometer can be read from or written to the controller; Figure 43 shows one of the implementations. M1 and M2 should be low threshold N-Ch power MOSFETs, such as FDV301N. A AD1582 GND 2 B U2 AD8601 VO 03437-0-039 W A1 Figure 40. Programmable Voltage Reference (DAC) Rp The digital potentiometers are commonly used in gain controls (Figure 41) or sensor transimpedance amplifier signal conditioning applications. To avoid gain peaking or in worst-case oscillation due to step response, a compensation capacitor is needed. In general, C2 in the range of a few picofarads to no more than a few tenths of a picofarad is adequate for the compensation. SDA2 D SCL2 M2 2.7V-5.5V 2.5V CONTROLLER AD5171 Figure 43. Level Shifting for Different Voltage Operation RESISTANCE SCALING A W The AD5171 offers 5 k, 10 k, 50 k, and 100 k nominal resistances. For users who need to optimize the resolution with an arbitrary full-range resistance, the following techniques can be used. By paralleling a discrete resistor (Figure 44), a proportionately lower voltage appears at terminal A to B, which is applicable to the voltage divider mode only. VO VI 03437-0-040 R1 U1 Rp G S M1 SCL1 4.7pF Figure 41. Typical Noninverting Gain Amplifier PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT For applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (Figure 42). This translates into a finer degree of precision because the step size at terminal W is smaller. The voltage can be found as U3 2N7002 VW (D ) = (RAB || R2) D x x VDD R3 + RAB || R2 64 VOUT VIN A AD5171 CC +V W VDD RBIAS R3 U2 IL AD8601 A B SIGNAL R2 03437-0-041 LD -V R1 B Figure 42. Programmable Booster Voltage Source W 03437-0-043 U1 D S SDA1 R2 100k 47k Rp Rp G C2 B VDD2 = 5V VDD1 = 2.5V GAIN CONTROL COMPENSATION 03437-0-042 1 U1 VIN V OUT 3 ADR03 FET N1. N1 power handling must be adequate to dissipate (VI - VO) x IL power. This circuit can source a maximum of 100 mA with a 5 V supply. For precision applications, a voltage reference such as ADR421, ADR03, or ADR370 can be applied at the A terminal of the digital potentiometer. Figure 44. Lowering the Nominal Resistance In this circuit, the inverting input of the op amp forces the VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-Ch Rev. 0 | Page 17 of 20 (5) AD5171 RDAC CIRCUIT SIMULATION MODEL VW (D ) = (RWB || R2) x VI RWA + RWB || R2 (6) VI The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the digital potentiometers. Configured as a potentiometer divider, the -3 dB bandwidth of the AD5171 (5 k resistor) measures 1.5 MHz at half scale. Figure 14 to Figure 17 provide the large signal BODE plot characteristics of the four available resistor versions: 5 k 10 k, 50 k, and 100 k. A parasitic simulation model is shown in Figure 47. Listing 1 provides a macro model net list for the 10 k device. A A VO R1 W B RDAC 10k CA 25pF R2 B CW 03437-0-044 55pF W CB 25pF 03437-0-046 For log taper adjustment, such as volume control, Figure 45 shows another way of resistance scaling to achieve the log taper function. In this circuit, the smaller the R2 with respect to RAB, the more like the pseudo log taper characteristic it behaves. The wiper voltage is simply Figure 47. Circuit Simulation Model for RDAC = 10 k Figure 45. Resistor Scaling with Log Adjustment Characteristics RESOLUTION ENHANCEMENT Listing 1. Macro Model Net List for RDAC The resolution can be doubled in the potentiometer mode of operation by using three digital potentiometers. Borrowed from ADI's patented RDAC segmentation technique, users can configure three AD5171s (Figure 46) to double the resolution. First, U3 must be parallel with a discrete resistor RP, which is chosen to be equal to a step resistance (RP = RAB/64). One can see that adjusting U1 and U2 together forms the coarse 6-bit adjustment and that adjusting U3 alone forms the finer 6-bit adjustment. As a result, the effective resolution becomes 12-bit. .PARAM D=64, RDAC=10E3 .SUBCKT DPOT (A,W,B) * CA A 0 25E-12 RWA A W {(1-D/64)*RDAC+60} CW W 0 55E-12 RWB W B {D/64*RDAC+60} CB B 0 25E-12 * A1 .ENDS DPOT W1 U1 * A3 B1 RP U3 W3 A2 B3 B2 COARSE FINE ADJUSTMENT ADJUSTMENT 03437-0-045 U2 W2 Figure 46. Doubling the Resolution Rev. 0 | Page 18 of 20 AD5171 AD5171 EVALUATION BOARD JP5 VCC JP3 VDD V+ U4 VDD C4 0.1F ADR03 CP3 VREF -IN1 C5 0.1F -IN1 5 1 TEMP TRIM 2 GND 4 3 VIN VOUT C6 0.1F CP4 CP2 JP1 JP8 CP1 8 2 A W R1 10k J1 8 7 6 5 4 3 2 1 3 VIN U3A CP6 1 2 3 4 R2 10k C2 0.1F SCL U1 W VDD GND SCL 8 A 7 B AD0 6 SDA 5 1 2 3 4 C3 0.1F U2 W VDD GND SCL 8 A 7 B AD0 6 SDA 5 CP7 4 JP4 AGND C8 0.1F AD5171/AD5273 AD5170 OUT1 V- CP5 +IN1 JP2 C1 10F OUT1 1 JP7 B VDD VDD C7 10F C9 10F SDA JP6 7 +IN2 VEE 6 5 OUT2 U3B Figure 48. AD5171 Evaluation Board Schematic The AD5171 evaluation board comes with a dual op amp AD822 and a 2.5 V reference ADR03. Users can configure many building block circuits with minimum components needed. Figure 49 shows one of the examples. There is space available on the board where users can build additional circuits for further evaluations, see Figure 50. CP2 VREF JP3 A A W VO W B U3A V+ 1 JP7 U2 JP2 4 2 3 OUT1 V- 11 AD822 JP4 03437-0-048 JP1 VREF B VDD Figure 50. AD5171 Evaluation Board Figure 49. Programmable Voltage Reference Rev. 0 | Page 19 of 20 03437-0-047 -IN2 AD5171 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 0.65 BSC 1.30 1.15 0.90 1.95 BSC 1.45 MAX 0.15 MAX 0.38 0.22 0.22 0.08 SEATING PLANE 0.60 0.45 0.30 8 4 0 COMPLIANT TO JEDEC STANDARDS MO-178BA Figure 51. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model AD5171BRJ5-R2 AD5171BRJ5-RL7 AD5171BRJZ5-R21 AD5171BRJZ5-R71 AD5171BRJ10-R2 AD5171BRJ10-RL7 AD5171BRJZ10-R21 AD5171BRJZ10-R71 AD5171BRJ50-R2 AD5171BRJ50-RL7 AD5171BRJZ50-R21 AD5171BRJZ50-R71 AD5171BRJ100-R2 AD5171BRJ100-RL7 AD5171BRJZ100-R21 AD5171BRJZ100-R71 AD5171EVAL2 1 2 RAB (k) 5 5 5 5 10 10 10 10 50 50 50 50 100 100 100 100 10 Package Code RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 Package Description SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 SOT-23-8 Evaluation Board Full Container Quantity 250 3000 250 3000 250 3000 250 3000 250 3000 250 3000 250 3000 250 3000 1 Branding D12 D12 D12 D12 D13 D13 D13 D13 D14 D14 D14 D14 D15 D15 D15 D15 Z = Pb-free part. The evaluation board is shipped with three pieces of 10 k parts. Users should order extra samples or different resistance options if needed. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03437-0-1/04(0) Rev. 0 | Page 20 of 20