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ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FSL4110LR 1000 V SenseFET Integrated Power Switch Features Description Built-in Avalanche Rugged 1000 V SenseFET Precise Fixed Operating Frequency: 50 kHz VCC can be supplied from either bias-winding or self- The FSL4110LR is an integrated pulse width modulation (PWM) controller and 1000 V avalanche rugged SenseFET specifically designed for high input voltage offline Switching Mode Power Supplies (SMPS) with minimal external components. VCC can be supplied through integrated high-voltage power regulator without auxiliary bias winding. biasing. Soft Burst-Mode Operation Minimizing Audible Noise Random Frequency Fluctuation for Low EMI Pulse-by-Pulse Current Limit Various Protection Functions: Overload Protection (OLP), Over-Voltage Protection (OVP), Abnormal Over-Current Protection (AOCP), Internal Thermal Shutdown (TSD) with Hysteresis. Under-Voltage Lockout (UVLO) and Line Over-Voltage Protection (LOVP) with Hysteresis. Built-in Internal Startup and Soft-Start Circuit Fixed 1.6 s Restart Time for Safe Auto-Restart Mode of All Protections The integrated PWM controller includes a fixedfrequency oscillator, Under-Voltage Lockout (UVLO), Leading-Edge Blanking (LEB), optimized gate driver, soft-start, temperature-compensated precise current sources for loop-compensation, and variable protection circuitry. Compared with a discrete MOSFET and PWM controller solution, the FSL4110LR reduces total cost, component count, PCB size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. This device provides a basic platform for cost-effective design of a flyback converter. Applications SMPS for Electric Metering Auxiliary Power Supply for 3-Phase Input Industrial Systems Ordering Information Part Number Package FSL4110LRN 7-DIP Operating Junction Temperature -40C ~ 125C FSL4110LRLX (1) Output Power Table Current RDS(ON) (Max.) (2) (2) Limit 45~460 VAC 85~460 VAC 0.52 A 10 4W (3) 9W (3) 7-LSOP Notes: 1. The junction temperature can limit the maximum output power. 2. Maximum practical continuous power in an open-frame design at 50 C ambient temperatures. 3. Bias winding condition. (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 www.fairchildsemi.com FSL4110LR -- 1000 V SenseFET Integrated Power Switch December 2015 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Typical Application Circuit VOUT RSTR (4) VSTR R1 FSL4110LR PWM VIN Drain GND R2 FB RDLY VCC (5) CVCC CFB Figure 1. Typical Application Circuit Notes: 4. RSTR: See the functional description 1. 5. RDLY: See the functional description 3.1. Internal Block Diagram Internal Bias VSTR Drain 2 5 6,7 HVREG VCC Good VSTART / VSTOP VREF Soft Burst VBURH /VBURL VCC VCC Random VREF OSC S Q IFB RDLY FB 3R 3 PWM R Line Comp. CFB SoftStart R Q Gate Driver LEB RSENSE VIN 1.6 s Auto Restart Timing Control 100 ms Delay 4 1 GND VOLP VINH VAOCP VCC TSD VOVP Figure 2. Internal Block Diagram (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 www.fairchildsemi.com 2 7 Drain GND 1 2 FB 3 VIN 4 FSL4110LR VCC 6 Drain 5 VSTR Figure 3. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 GND Ground. The SenseFET source terminal on primary side and the internal PWM control ground. VCC Power Supply Voltage Input. This pin is the positive supply input, which provides the internal operating current for startup and steady-state operation. This voltage is supplied from internal high-voltage regulator via pin 5 (VSTR) during startup (see Figure 2). When the external bias voltage is higher than 10 V, internal high voltage regulator is disable. A ceramic capacitor need to be placed as close as possible between this pin and pin 1 (GND). Recommended distance is less than 3 mm. 3 FB Feedback. This pin is internally connected to the inverting input to the PWM comparator. This pin has a 100 A current source internally. The collector of an opto-coupler is typically tied to this pin. A capacitor should be placed between this pin and GND. A resitor should be connected between this pin and pin 2 (V CC) to generate delay current (IDELAY) for overload protection delay time. The resistance should not be exceed 5 M in self-biasing. 4 VIN Line Over-Voltage Input. This pin is the input of divided line voltage. The voltage is devided by resistors. When this voltage is higher than 2 V, the FSL4110LR is not operationed. If this pin is not used, it should be connected to the ground. 2 5 VSTR Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and charges an external storage capacitor placed between V CC pin and ground. Once VCC reaches 12 V, all internal blocks are activated. The internal high-voltage regulator turns on and off to maintain V CC at 10 V without auxiliary bias winding. 6, 7 Drain Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of 1000 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance. (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 www.fairchildsemi.com 3 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VSTR VSTR Pin Voltage 700 V VDS Drain Pin Voltage 1000 V VCC VCC Pin Voltage 27 V -0.3 12.0 V -0.3 12.0 V 4 A TC=25C 1 A TC=100C 0.6 A 51 mJ 1.5 W 150 C -40 +125 C -55 +150 C VFB Feedback Pin Voltage (6) VIN VIN Pin Voltage IDM Drain Current Pulsed IDS EAS PD (6) Continuous Switching Drain Current Single Pulsed Avalanche Energy (7) (8) Total Power Dissipation (TC=25C) (9) Maximum Junction Temperature TJ TSTG Operating Junction Temperature (10) Storage Temperature Notes: 6. VFB and VIN are clamped by internal clamping diode (11 V, ICLAMP_MAX < 100 A). 7. Repetitive peak switching current when the inductive load is assumed: Limited by maximum duty (DMAX=0.73) and junction temperature (see Figure 4). 8. IAS = 3.2 A, L = 10 mH, starting TJ=25C. 9. Infinite cooling condition (refer to the SEMI G30-88). 10. Although this parameter guarantees IC operation, it does not guarantee all electrical characteristics. IDS DMAX fS Figure 4. Repetitive Peak Switching Current Thermal Impedance Symbol JA Parameter Junction-to-Ambient Thermal Impedance (11) Value Unit 85 C/W Note: 11. JEDEC recommended environment, JESD51-2, and test board, JESD51-3, with minimum land pattern. ESD Capability Symbol ESD Parameter Value Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 5.0 Charged Device Model, JESD22-C101 2.0 (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 Unit KV www.fairchildsemi.com 4 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Absolute Maximum Ratings TJ =-40C to 125C unless otherwise specified. Symbol Parameter Conditions Min. VGS = 0 V, ID = 250 A 1000 Typ. Max. Unit SenseFET Section BVDSS IDSS RDS(ON) CISS COSS td(on) tr td(off) tf Drain-Source Breakdown Voltage Zero-Gate-Voltage Drain Current (12) (12) Drain-Source On-State (12) Resistance Input Capacitance (12)(13) Output Capacitance Turn-On Delay Time Rise Time Fall Time 250 A VGS = 10 V, ID = 1.0 A 10 367 477 pF 37.5 48.8 pF (12) (12) Turn-Off Delay Time VDS = 1000 V, VGS = 0 V VDS = 25 V, VGS = 0 V, f = 1 MHz (12)(13) VDD = 500 V, ID = 1.0 A, VGS = 10 V, Rg = 25 (12) V (12) 13.7 ns 14 ns 33 ns 45 ns Control Section fS fM DMAX IFB VSTART VSTOP tS/S Switching Frequency (12) Frequency Modulation VCC = 14 V, VFB = 4 V 46.5 Maximum Duty Ratio Feedback Source Current 50.0 53.5 1.5 (13) (12) UVLO Threshold Voltage Internal Soft-Start Time kHz kHz VCC = 14 V, VFB = 4 V 61 67 73 % VFB = 0 V 70 100 130 A VFB = 0 V, VCC Sweep 11 12 13 After Turn-on, VFB = 0 V 7 8 9 VSTR = 40 V, VCC Sweep 20 V ms Burst-Mode Section VBURH VBURL Burst-Mode Voltage (12) VCC = 14 V, VFB Sweep 0.45 0.50 0.55 V 0.35 0.40 0.45 V VHYS 100 mV Protection Section ILIM Peak Drain Current Limit (12) VOLP Overload Protection VAOCP Abnormal Over-Current (13) Protection tLEB (12) Leading-Edge Blanking Time di/dt = 240 mA/s 0.45 0.52 0.59 A VCC = 14 V, VFB Sweep 4.0 4.4 4.8 V (13)(14) Current Limit Delay Time VOVP Over-Voltage Protection VCC Sweep 23.0 VINH Line Over-Voltage Protection Threshold Voltage VCC = 14 V, VIN Sweep 1.9 VINHYS Line Over-Voltage Protection (12) Hysteresis VCC = 14 V, VIN Sweep tDELAY Overload Protection Delay Restart Time After Protection (13) Shutdown Temperature Thermal Shutdown Temperature THYS 250 ns 200 ns 24.5 26.0 V 2.0 2.1 V 100 mV 100 ms 1.6 TSD THYS V (13) tCLD tRESTART 1.0 (13) 130 140 Hysteresis (FSL4110LRN) 60 Hysteresis (FSL4110LRLX) 30 s 150 C Continued on the following page... (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 www.fairchildsemi.com 5 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Electrical Characteristics TJ =-40C to 125C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Unit 9 10 11 V High Voltage Regulator Section VHVREG HV Regulator Voltage VFB = 0 V, VSTR = 40 V Total Device Section IOP Operating Supply Current, (12) (Control Part in Burst Mode) VCC = 14 V, VFB = 0 V 0.40 0.50 mA IOPS Operating Switching Current, (12) (Control Part and SenseFET Part) VCC = 14 V, VFB = 2 V 1.00 1.35 mA VCC = 11 V (Before VCC Reaches VSTART) 160 240 A ISTART ICH VSTR Start Current (12) Startup Charging Current (12) Minimum VSTR Supply Voltage VCC = VFB = 0 V, VSTR = 40 V 1.5 CVCC = 0.1 F, VSTR Sweep 2.0 mA 26 V Notes: 12. TJ = 25C. 13. Although these parameters are guaranteed, they are not 100% tested in production. 14. tLEB includes gate turn-on time. (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 www.fairchildsemi.com 6 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Electrical Characteristics (Continued) Characteristic graphs are normalized at TA=25C. Operating Switching Current (IOPS) 1.15 1.1 1.1 1.05 1.05 Normalized Normalized Operating Supply Current (IOP) 1.15 1 0.95 1 0.95 0.9 0.9 0.85 0.85 -40 -25 0 25 50 85 100 125 -40 -25 Temperature () Figure 5. Operating Supply Current (IOP) vs. TA 50 85 100 125 Peak Drain Current Limit (ILIM) 1.15 1.15 1.1 1.1 1.05 1.05 Normalized Normalized 25 Figure 6. Operating Switching Current (IOPS) vs. TA Startup Charging Current (ICH) 1 0.95 0.9 1 0.95 0.9 0.85 0.85 -40 -25 0 25 50 85 100 125 -40 -25 Temperature () 0 25 50 85 100 125 Temperature () Figure 7. Startup Charging Current (ICH) vs. TA Figure 8. Peak Drain Current Limit (ILIM) vs. TA Startup Charging Current (V HVREG ) Feedback Source Current (IFB) 1.15 1.15 1.1 1.1 1.05 1.05 Normalized Normalized 0 Temperature () 1 0.95 1 0.95 0.9 0.9 0.85 0.85 -40 -25 0 25 50 85 100 125 -40 Temperature () 0 25 50 85 100 125 Temperature () Figure 9. Feedback Source Current (IFB) vs. TA (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 -25 Figure 10. HV Regulator Voltage (VHVREG) vs. TA www.fairchildsemi.com 7 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Typical Performance Characteristics Characteristic graphs are normalized at TA=25C. UVLO Threshold Voltage (V START) 1.15 Normalized 1.1 1.05 1 0.95 0.9 0.85 -40 -25 0 25 50 85 100 125 Temperature () Figure 11. UVLO Threshold Voltage (VSTART) vs. TA Figure 12. UVLO Threshold Voltage (VSTOP) vs. TA Over-Voltage Protection (VOVP) 1.15 Normalized 1.1 1.05 1 0.95 0.9 0.85 -40 -25 0 25 50 85 100 125 Temperature () Figure 13. OLP Feedback Voltage (VOLP) vs. TA Figure 14. Over-Voltage Protection (VOVP) vs. TA Switching Frequency (fS) 1.15 Normalized 1.1 1.05 1 0.95 0.9 0.85 -40 -25 0 25 50 85 100 125 Temperature () Figure 15. Switching Frequency (fS) vs. TA (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 Figure 16. Maximum Duty Ratio (DMAX) vs. TA www.fairchildsemi.com 8 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Typical Performance Characteristics (Continued) 1. Startup and High-Voltage Regulator During startup, an internal high-voltage current source (ICH) of the high-voltage regulator (HVREG) supplies the internal bias current (ISTART) and charges the external capacitor (CVCC) connected to VCC pin, as shown in Figure 17. This internal high-voltage current source is enabled until VCC reaches VSTART (12 V). During steadystate operation, this internal high-voltage regulator (HVREG) maintains the VCC with 10 V and provides operating switching current (IOPS) for all internal circuits. Therefore, FSL4110LR needs no external bias circuit. The high-voltage regulator is disabled when V CC supplied by the external bias is higher than 10 V. However in the case of self-biasing, power consumption is increased. Rectified Line Input (VDC) blocked when feedback voltage (VFB) exceeds 2.4 V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current of the SenseFET is limited at: 2.4V Sense Ratio RSENSE VREF IDLY VOUT FOD817 R2 Internal Bias CINL R3 VSTR 5 ICH HVREG VCC Good VSTART VREF / VSTOP Figure 17. Startup and HVREG Block The startup resistor (RSTR) can be calculated by the following equation (1). RSTR VDC _ MIN VSTART I CH (1) where, IOPS < ICH < 2 mA, RSTR + R1 = R2 + R3 2. Feedback Control FSL4110LR employs current-mode control scheme. An opto-coupler (such as FOD817) and shunt regulator (such as KA431) in secondary-side are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across RSENSE resistor makes it possible to control the switching duty cycle. When the input voltage is increased or the output load is decreased, reference input voltage of shunt regulator is increased. If this voltage exceeds internal reference voltage of shunt regulator, opto-diode's current of the opto-coupler increases, pulling down the feedback voltage and reducing drain current. 2.1. Pulse-by-Pulse Current Limit Because current-mode control is employed, the peak current flowing through the SenseFET is limited by the inverting input of PWM comparator, as shown in Figure 18. Assuming that 100 A current source (IFB) flows only through the internal resistors (3R + R = 24 k), the cathode voltage of diode D2 is about 2.4 V. Since D1 is (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 3R D1 CFB OSC IFB FB D2 PWM LEB RSENSE OLP KA431 VOLP Gate Driver R Line Comp. AOCP 1 GND VAOCP RSTR CVCC ISTART or IOPS RDLY 3 CINH 2 Drain 6,7 VCC Figure 18. Pulse Width Modulation Circuit R1 VCC (2) 2.2. Leading Edge Blanking (LEB) At the instant, the internal SenseFET is turned on, a high-current spike usually occurs through the SenseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the RSENSE resistor leads to incorrect feedback operation in the current-mode PWM control. To counter this effect, FSL4110LR employs a leadingedge blanking (LEB) circuit. This circuit inhibits the PWM comparator for tLEB (250 ns) after the SenseFET is turned on. 3. Protection Circuits The protective functions include Overload Protection (OLP), Over-Voltage Protection (OVP), Under-Voltage Lockout (UVLO), Abnormal Over-Current Protection (AOCP), and Thermal Shutdown (TSD). All of the protections operate in auto-restart mode as shown in Figure 19. Since these protection circuits are fully integrated inside the IC without external components, reliability is improved without increasing cost and PCB space. If a fault condition occurs, switching is terminated and the SenseFET remains off. At the same time, internal protection timing control is activated to decrease power consumption and stress on passive and active components during auto-restart. When internal protection timing control is activated, V CC is regulated with 10 V through the internal high-voltage regulator while switching is terminated. This internal protection timing control continues until restart time (1.6 s) duration is finished. After counting to 1.6 s, the internal high-voltage regulator is disabled and V CC is decreased. When VCC reaches the UVLO stop voltage, VSTOP (8 V), the protection is reset and the internal highvoltage current source charges the V CC capacitor via the high voltage startup pin (VSTR) again. When VCC reaches the UVLO start voltage, VSTART (12 V), the FSL4110LR resumes normal operation. In this manner, auto-restart function can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. www.fairchildsemi.com 9 FSL4110LR -- 1000 V SenseFET Integrated Power Switch Functional Description Fault occurs Power on Drain 6,7 Fault removed VCC VREF IDLY OSC IFB RDLY 3R 3 FB CFB D1 D2 PWM R Line Comp. LEB S Q R Q Gate Driver OLP t RSENSE 100 ms Delay VCC OLP 1 GND VOLP VAUX VSTART VHVREG VSTOP Figure 21. OLP Circuit Recommended the RDLY value is less than 5 M in selfbiasing. The delay time (tDLY) can be calculated by equation (3). t Normal operation Fault condition Normal operation Restart time (1.6 s) 2 t DLY RDLY CFB ln 1 V 2 . 4 CC Figure 19. Auto-Restart Protection Waveforms (3) 3.1. Overload Protection (OLP) Example: Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in normal operation, the overload protection circuit can be triggered during load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger only after a specified time to determine whether it is a transient situation or a true overload situation. Because of the pulse-by-pulse current-limit capability, the maximum peak current through the SenseFET is limited. If the output consumes more than this maximum power, the output voltage decreases below the set voltage. This reduces the current through the optodiode, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (V FB). If VFB exceeds 2.4 V, internal diode D1 is blocked and the current (IDLY) by RDLY starts to charge CFB. If feedback voltage reaches 4.4 V, internal fixed delay time (tDELAY) starts counting. If feedback voltage maintains over 4.4 V after tDELAY (100 ms), the switching operation is terminated (see Figure 20). The internal OLP circuit is shown in Figure 21. When, RDLY = 3 M, CFB = 68 nF, VCC = 15 V, VCC tDLY = 35 ms Total delay time for OLP: 135 ms 3.2. Abnormal Over-Current Protection (AOCP) When the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the SenseFET during the minimum turn-on time. Overload protection is not enough to protect the FSL4110LR in that abnormal case (see Figure 22); since severe current stress is imposed on the SenseFET until OLP is triggered. The internal AOCP circuit is shown in Figure 23. When the gate turn-on signal is applied to the power SenseFET, the AOCP block is enabled and monitors the current through the sensing-resistor. The voltage across the resistor is compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the high signal is applied to input of the NOR gate, resulting in the shutdown of the SMPS. VCC VAUX VSTART VHVREG VSTOP VAUX VSTART VHVREG VSTOP tDELAY t VFB tDLY 4.4 V 2.4 V tRESTART t IDS tRESTART t t IDS AOCP Occurrence AOCP Disappear t Figure 22. AOCP Waveforms Overload Occurrence Overload Disappear Figure 20. OLP Waveforms (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 www.fairchildsemi.com 10 FSL4110LR -- 1000 V SenseFET Integrated Power Switch VDS VREF OSC IFB 3R FB 3 D1 D2 PWM R Line Comp. S Q R Q LEB VCC Gate Driver VAUX VSTART VHVREG VSTOP AOCP RSENSE AOCP tRESTART 1 GND VAOCP t IDS Figure 23. AOCP Circuit 3.3. Over-Voltage Protection (OVP) If the secondary-side feedback circuit malfunctions or a solder defect causes an opening in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then VFB climbs in a similar manner to the overload situation, forcing the preset maximum drain current to flow until the overload protection is triggered. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the overload protection is triggered, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an OVP circuit is employed. In general, the VCC is proportional to the output voltage when the bias-winding is used and the FSL4110LR uses VCC instead of directly monitoring the output voltage. If VCC exceeds 24.5 V, an OVP circuit is triggered, resulting in the termination of the switching operation. To avoid undesired activation of OVP during normal operation, VCC should be designed to be below 24.5 V in the normal conditions. The internal OVP circuit is shown in Figure 24. t Figure 25. LOVP Waveforms Rectified Line Input (VDC) D2 PWM R Line Comp. S Q R Q LEB Gate Driver OVP RSENSE VCC 2 OVP 1 GND VOVP 3R FB 3 D1 D2 R1 PWM R Line Comp. VIN LEB 4 LOVP R2 CVIN VINH S Q R Q Gate Driver LOVP RSENSE 1 GND Figure 26. LOVP Circuit Equation (4) calculates the level of input over-voltage to RMS value. OSC 3R D1 OSC IFB R2 IFB FB 3 Drain 6,7 VREF Drain 6,7 VREF LOVP Disappear LOVP Occurrence VINH R1 VDC VINH (4) The resistance of divided resistor can be adjusted as necessary. Small resistance can bring relatively large stand-by power consumption at light-load condition. To avoid this situation, a several M resistor is recommended. For stable operation, a several M resistor should accompany a capacitor (CVIN) with hundreds of pF capacitance between the VIN pin and GND. Figure 24. OVP Circuit 3.4. Thermal Shutdown (TSD) The SenseFET and control IC integrated on the same package makes it easier to detect the temperature of the SenseFET. When the junction temperature exceeds 140C, thermal shutdown is activated. The FSL4110LR is restarted when the temperature decreases by 60C within tRESTART (1.6 s). 3.5. Line Over-Voltage Protection (LOVP) If the line input voltage is increased to an undesirable level, high line input voltage creates high-voltage stress on the entire system. To protect the SMPS from this abnormal condition, LOVP is included. It is comprised of detecting VIN voltage by using divided resistors. When voltage of VIN voltage is higher than 2.0 V, this condition is recognized as an abnormal error and PWM switching shuts down until voltage of VIN voltage decreases to (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 4. Oscillator Block The oscillator frequency is set internally and the FSL4110LR has a random frequency fluctuation function as shown in Figure 27. Fluctuation of the switching frequency can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The range of frequency variation is fixed internally; however, its selection is randomly chosen by the combination of an external feedback voltage and an internal freerunning oscillator. This randomly chosen switching frequency effectively spreads the EMI noise near switching frequency and allows the use of a costeffective inductor instead of an AC input line filter to satisfy world-wide EMI requirements. www.fairchildsemi.com 11 FSL4110LR -- 1000 V SenseFET Integrated Power Switch around 1.9 V within tRESTART (see Figure 25). The internal LOVP circuit is shown in Figure 26. Drain 6,7 mode. Additionally to reduce the audible noise softburst is implemented. several mseconds tS = 1/fS VO tS t Dt fSW t VFB MAX fS + 1/2DfS 0.5V no repetition fS - 1/2DfS several miliseconds 0.4V MAX t IDS t Figure 27. Frequency Fluctuation Waveforms t 5. Soft-Start The internal soft-start circuit slowly increases the SenseFET current after it starts. The typical soft-start time is 20 ms, as shown in Figure 28, where progressive increments of the SenseFET current are allowed during startup. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is gradually increased to smoothly establish the required output voltage. Soft-start also helps to prevent transformer saturation and reduces stress on the secondary diode. 2.5ms ILIM Soft start envelope Drain Current 8-Steps t VDS t Switching disabled Switching disabled Figure 29. Burst Mode Operation 7. Line Compensation All of switching devices have their own inherent propagation delays. This propagation delay will cause a current limit delay defined as tCLD. Because there is a current limit delay, tCLD, there is a difference in the current peak between low and high input voltage. The variance in the current peak is related to the difference between the input voltages, a wider gap in input voltage will result in a greater variance of the current peak. In order to have a constant current peak regardless of the input voltage, line compensation is required. FSL4110LR has line compensation, so the real peak value of high input voltage is similar to that of low input voltage. tCLD effect could be neglected as showed Figure 30. Figure 28. Internal Soft-Start 6. Burst Mode Operation To minimize power dissipation in standby mode, the FSL4110LR enters burst mode. As the load decreases, the feedback voltage decreases. The device automatically enters burst mode when the feedback voltage drops below VBURL (400 mV), as shown in Figure 29. At this point, switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH (500 mV), switching resumes. Feedback voltage then falls and the process repeats. Burst Mode alternately enables and disables switching of the SenseFET, reducing switching loss in standby (c) 2014 Fairchild Semiconductor Corporation FSL4110LR * Rev. 1.3 I DR (85 V A AIN C): 100 iv mA/d IDRAIN(460 VAC): 100 mA/div 500 ns/div Figure 30. ILIMIT Waveforms (85 VAC vs. 460 VAC) www.fairchildsemi.com 12 FSL4110LR -- 1000 V SenseFET Integrated Power Switch IDS 7 10.00 9.10 0.56 0.36 5 A 7.62 2.54 B 6.60 9.90 6.20 9.30 1 0.56 6.70 4 1.09 0.94 0.10 M C B A 1.62 1.47 0.56 0.36 0.10 M C B A 10.70 0.10 MIN LAND PATTERN RECOMMENDATION 7.62 A 3.70 MAX C 0.10 C 2.54 7.62 FRONT VIEW 9 0.25 SEATING PLANE 1.252 1.784 TOP VIEW 3.60 3.20 2.00 3 DETAIL A SCALE 2:1 0.35 0.20 SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A. NO INDUSTRY STANDARD APPLIES TO THIS PACKAGE R0.20 B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, R0.20 MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONS AND TOLERANCES PER GAGE PLANE ASME Y14.5M-2009 8 E. DRAWING FILENAME: MKT-MLSOP07Arev2 0 1.12 0.72 1.60 REF 9.779 9.525 A 7 5 B 6.477 6.223 PIN #1 4 1 (0.787) TOP VIEW 12 2.54 12 3.937 3.683 3.429 3.175 0.508 MIN SEATING PLANE 7.874 7.620 3.556 3.048 1.651 1.397 0.381 0.203 C 7.53 0.508 0.406 0.10 M C FRONT VIEW NOTES: A. REFERENCE JEDEC MS-001, VARIATION BA EXCEPT FOR NUMBER OF LEADS. B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 2009 D. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH AND TIE BAR EXTRUSIONS. E. DRAWING FILENAME: MKT-NA07Drev2 9.398 7.874 SIDE VIEW ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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