P82B96TD,118-CUT TAPE - NXP SEMICONDUCTORS

1. General description

The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface

between the normal I2C-bus and a range of other bus conﬁgurations. It can interface

I2C-bus logic signals to similar buses having different voltage and current levels.

For example, it can interface to the 350 µA SMBus, to 3.3 V logic devices, and to 15 V

levels and/or low-impedance lines to improve noise immunity on longer bus lengths.

It achieves this interface without any restrictions on the normal I2C-bus protocols or clock

speed. The IC adds minimal loading to the I2C-bus node, and loadings of the new bus or

remote I2C-bus nodes are not transmitted or transformed to the local node. Restrictions

on the number of I2C-bus devices in a system, or the physical separation between them,

are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission

lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate

directional Tx and Rx signals are provided. The Tx and Rx signals may be directly

connected, without causing latching, to provide an alternative bidirectional signal line with

I2C-bus properties.

2. Features

nBidirectional data transfer of I2C-bus signals

nIsolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side

nTx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive

buses

n400 kHz operation over at least 20 meters of wire (see

AN10148

)

nSupply voltage range of 2 V to 15 V with I2C-bus logic levels on Sx/Sy side

independent of supply voltage

nSplits I2C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface

with opto-electrical isolators and similar devices that need unidirectional input and

output signal paths.

nLow power supply current

nESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V

SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101

nLatch-up free (bipolar process with no latching structures)

nPackages offered: DIP8, SO8 and TSSOP8

P82B96

Dual bidirectional bus buffer

Rev. 08 — 10 November 2009 Product data sheet

Product data sheet Rev. 08 — 10 November 2009 2 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

3. Applications

nInterface between I2C-buses operating at different logic levels (for example, 5 V and

3 V or 15 V)

nInterface between I2C-bus and SMBus (350 µA) standard

nSimple conversion of I2C-bus SDA or SCL signals to multi-drop differential bus

hardware, for example, via compatible PCA82C250

nInterfaces with opto-couplers to provide opto-isolation between I2C-bus nodes up to

400 kHz

4. Ordering information

4.1 Ordering options

Table 1. Ordering information

Type number Package

Name Description Version

P82B96DP TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm SOT505-1

P82B96PN DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1

P82B96TD SO8 plastic small outline package; 8 leads;

body width 3.9 mm SOT96-1

P82B96TD/S900 SO8 plastic small outline package; 8 leads;

body width 3.9 mm SOT96-1

Table 2. Ordering options

Type number Topside mark Temperature range

P82B96DP 82B96 −40 °C to +85 °C

P82B96PN P82B96PN −40 °C to +85 °C

P82B96TD P82B96T −40 °C to +85 °C

P82B96TD/S900 P82B96T −40 °C to +125 °C

Product data sheet Rev. 08 — 10 November 2009 3 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

5. Block diagram

6. Pinning information

6.1 Pinning

6.2 Pin description

Fig 1. Block diagram of P82B96

P82B96

Sx (SDA)

Rx (RxD, SDA)

Sy (SCL)

Tx (TxD, SDA)

Ty (TxD, SCL)

GND

Ry (RxD, SCL)

002aab976

VCC (2 V to 15 V)

Fig 2. Pin conﬁguration for DIP8 Fig 3. Pin conﬁguration for SO8 Fig 4. Pin conﬁguration for

TSSOP8

P82B96PN

Sx VCC

Rx Sy

Tx Ry

GND Ty

002aab977

P82B96TD

P82B96TD/S900

Sx VCC

Rx Sy

Tx Ry

GND Ty

002aab978

7P82B96DP

Sx VCC

Rx Sy

Tx Ry

GND Ty

002aab979

Table 3. Pin description

Symbol Pin Description

Sx 1 I2C-bus (SDA or SCL)

Rx 2 receive signal

Tx 3 transmit signal

GND 4 negative supply

Ty 5 transmit signal

Ry 6 receive signal

Sy 7 I2C-bus (SDA or SCL)

VCC 8 positive supply voltage

Product data sheet Rev. 08 — 10 November 2009 4 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

7. Functional description

Refer to Figure 1 “Block diagram of P82B96”.

The P82B96 has two identical buffers allowing buffering of both of the I2C-bus (SDA and

SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the

I2C-bus interface pin which drives the buffered bus, and a reverse signal path from the

buffered bus input to drive the I2C-bus interface. Thus these paths are:

•sense the voltage state of the I2C-bus pin Sx (or Sy) and transmit this state to the pin

Tx (Ty respectively), and

•sense the state of the pin Rx (Ry) and pull the I2C-bus pin LOW whenever Rx (Ry) is

LOW.

The rest of this discussion will address only the ‘x’ side of the buffer; the ‘y’ side is

identical.

The I2C-bus pin (Sx) is designed to interface with a normal I2C-bus.

The logic threshold voltage levels on the I2C-bus are independent of the IC supply VCC.

The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is

3 mA.

The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic

LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC (with a typical switching

threshold of half VCC).

Tx is an open-collector output without ESD protection diodes to VCC. It may be connected

via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not

exceeded. It has a larger current sinking capability than a normal I2C-bus device, being

able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down

capability as well.

A logic LOW is only transmitted to Tx when the voltage at the I2C-bus pin (Sx) is below

0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in

accordance with I2C-bus requirements (maximum 1.5 V in 5 V applications) but not low

enough to be looped back to the Tx output and cause the buffer to latch LOW.

The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically

0.8 V.

If the supply voltage VCC fails, then neither the I2C-bus nor the Tx output will be held LOW.

Their open-collector conﬁguration allows them to be pulled up to the rated maximum of

15 V even without VCC present. The input conﬁguration on Sx and Rx also present no

loading of external signals even when VCC is not present.

The effective input capacitance of any signal pin, measured by its effect on bus rise times,

is less than 7 pF for all bus voltages and supply voltages including VCC =0V.

Remark: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design

does not support this conﬁguration. Bidirectional I2C-bus signals do not allow any

direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy

to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the Rx/Ry of a P82B96

will be propagated to Sx/Sy as a ‘buffered LOW’ with a slightly higher voltage level. If this

Product data sheet Rev. 08 — 10 November 2009 5 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will

not recognize it as a ‘regular I2C-bus LOW’ and will not propagate it to its Tx/Ty output.

The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special

logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The

Sx/Sy side is only intended for, and compatible with, the normal I2C-bus logic voltage

levels of I2C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if

required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C-bus logic voltage levels of all

I2C-bus parts. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O

pins to other P82B96s, for example in a star or multipoint conﬁguration with the Tx/Rx and

Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave

devices. For more details see

Application Note AN255

8. Limiting values

[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Voltages with respect to pin GND.

Symbol Parameter Conditions Min Max Unit

VCC supply voltage VCC to GND −0.3 +18 V

VSx voltage on pin Sx I2C-bus SDA or SCL −0.3 +18 V

VTx voltage on pin Tx buffered output [1] −0.3 +18 V

VRx voltage on pin Rx receive input [1] −0.3 +18 V

Incurrent on any pin - 250 mA

Ptot total power dissipation - 300 mW

Tjjunction temperature operating range

P82B96TD/S900 −40 +125 °C

Tstg storage temperature −55 +125 °C

Tamb ambient temperature operating −40 +85 °C

Product data sheet Rev. 08 — 10 November 2009 6 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

9. Characteristics

Table 5. Characteristics

amb

= +25

C; voltages are speciﬁed with respect to GND with V

= 5 V, unless otherwise speciﬁed.

Symbol Parameter Conditions Tamb = +25 °C Tamb = −40 °C to

+125 °C[1] Unit

Min Typ Max Min Max

Power supply

VCC supply voltage operating 2.0 - 15 2.0 15 V

ICC supply current buses HIGH - 0.9 1.8 - 3 mA

VCC =15V;

buses HIGH - 1.1 2.5 - 4 mA

∆ICC additional quiescent

supply current per Tx or Ty LOW - 1.7 3.5 - 3.5 mA

Bus pull-up (load) voltages and currents

VSx, VSy maximum input/output

voltage open-collector;

I2C-busandVRx,VRy =

HIGH

--15-15V

ISx, ISy static output loading on

I2C-bus VSx, VSy = 1.0 V;

VRx,V

Ry =LOW [2] 0.2 - 3 0.2 3 mA

ISx, ISy dynamic output sink

capability on I2C-bus VSx, VSy =2V;

VRx,V

Ry =LOW 718- 7 -mA

ISx, ISy leakage current on

I2C-bus VSx, VSy =5V;

VRx,V

Ry = HIGH --1 -10µA

VSx, VSy =15V;

VRx,V

Ry = HIGH -1- - 10µA

VTx, VTy maximumoutputvoltage

level open-collector - - 15 - 15 V

ITx, ITy static output loading on

buffered bus VTx, VTy = 0.4 V;

VSx,V

Sy = LOW on

I2C-bus = 0.4 V

- - 30 - 30 mA

ITx, ITy dynamic output sink

capability, buffered bus VTx, VTy >1V;

VSx,V

Sy = LOW on

I2C-bus = 0.4 V

60 100 - 60 - mA

ITx, ITy leakage current on

buffered bus VTx, VTy =V

CC =15V;

VSx, VSy = HIGH -1- - 10µA

Input currents

ISx, ISy input current from

I2C-bus bus LOW;

VRx,V

Ry = HIGH -−1- - −10 µA

IRx, IRy input current from

buffered bus bus LOW;

VRx,V

Ry = 0.4 V -−1- - −10 µA

IRx, IRy leakage current on

buffered bus input VRx, VRy =V

CC -1- - 10µA

Output logic LOW level

VSx, VSy output logic level LOW

on normal I2C-bus ISx, ISy =3mA [3] 0.8 0.88 1.0 (see Figure 6)V

ISx, ISy = 0.2 mA [3] 670 730 790 (see Figure 5)mV

dVSx/dT,

dVSy/dT temperature coefﬁcient

of output LOW levels ISx, ISy = 0.2 mA [3] -−1.8 - - - mV/K

Product data sheet Rev. 08 — 10 November 2009 7 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Input logic switching threshold voltages

VSx, VSy input logic voltage LOW on normal I2C-bus [4] - 640 600 (see Figure 7)mV

VSx, VSy input logic level HIGH

threshold on normal I2C-bus [4] 700 650 - (see Figure 8)mV

dVSx/dT,

dVSy/dT temperature coefﬁcient

of input thresholds -−2 - - - mV/K

VRx, VRy input logic HIGH level fraction of applied VCC 0.58VCC - - 0.58VCC -V

VRx, VRy input threshold fraction of applied VCC - 0.5VCC ---V

VRx, VRy input logic LOW level fraction of applied VCC - - 0.42VCC - 0.42VCC V

Logic level threshold difference

VSx, VSy input/output logic level

difference VSx output LOW at

0.2 mA −VSx input

HIGH maximum

[2] 50 85 - 50 - mV

Thermal resistance

Rth(j-pcb) thermal resistance from

junctiontoprinted-circuit

board

SOT96-1 (SO8);

average lead

temperature at board

interface

- 127 - - - K/W

Bus release on VCC failure

VSx, VSy,

VTx, VTy

VCC voltage at which all

buses are guaranteed to

be released

- - 1 (see Figure 9)V

dV/dT temperature coefﬁcient

of guaranteed release

voltage

-−4 - - - mV/K

Buffer response time[5]

Tfall delay

VSx toVTx,

VSy to VTy

buffer time delay on

falling input between

VSx = input switching

threshold, and VTx

output falling 50 %

RTx pull-up = 160 Ω;

no capacitive load;

VCC =5V

-70- - -ns

Trise delay

VSx toVTx,

VSy to VTy

buffer time delay on

rising input between

VSx = input switching

threshold, and VTx

output reaching 50 %

VCC

RTx pull-up = 160 Ω;

no capacitive load;

VCC =5V

-90- - -ns

Table 5. Characteristics

…continued

amb

= +25

C; voltages are speciﬁed with respect to GND with V

= 5 V, unless otherwise speciﬁed.

Symbol Parameter Conditions Tamb = +25 °C Tamb = −40 °C to

+125 °C[1] Unit

Min Typ Max Min Max

Product data sheet Rev. 08 — 10 November 2009 8 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

[1] Limit data for +125 °C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test.

[2] The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for VSx output LOW will always exceed

the minimum VSx input HIGH level to eliminate any possibility of latching. The speciﬁed difference is guaranteed by design within any IC.

While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because

the resulting system would be very susceptible to induced noise and would not support all I2C-bus operating modes.

[3] The output logic LOW depends on the sink current. For scaling, see

Application Note AN255

[4] The input logic threshold is independent of the supply voltage.

[5] The fall time of VTx from 5 V to 2.5 V in the test is approximately 15 ns.

The fall time of VSx from 5 V to 2.5 V in the test is approximately 50 ns.

The rise time of VTx from 0 V to 2.5 V in the test is approximately 20 ns.

The rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70 ns.

Tfall delay

VRx to

VSx, VRy

to VSy

buffer time delay on

falling input between

VRx = input switching

threshold, and VSx

output falling 50 %

RSx pull-up = 1500 Ω;

no capacitive load;

VCC =5V

- 250 - - - ns

Trise delay

VRx to

VSx, VRy

to VSy

buffer time delay on

rising input between

VRx = input switching

threshold, and VSx

output reaching 50 %

VCC

RSx pull-up = 1500 Ω;

no capacitive load;

VCC =5V

- 270 - - - ns

Input capacitance

Ciinput capacitance effective input

capacitance of any

signal pin measured

by incremental bus

rise times

--7 - 7pF

Table 5. Characteristics

…continued

amb

= +25

C; voltages are speciﬁed with respect to GND with V

= 5 V, unless otherwise speciﬁed.

Symbol Parameter Conditions Tamb = +25 °C Tamb = −40 °C to

+125 °C[1] Unit

Min Typ Max Min Max

Product data sheet Rev. 08 — 10 November 2009 9 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

VOL at Sx typical and limits over temperature

(1) Maximum

(2) Typical

(3) Minimum

VOL at Sx typical and limits over temperature

(1) Maximum

(2) Typical

(3) Minimum

Fig 5. VOL as a function of junction temperature

(IOL = 0.2 mA) Fig 6. VOL as a function of junction temperature

(IOL = 3 mA)

VIL(max) at Sx changes over temperature range VIH(min) at Sx changes over temperature range

Fig 7. VIL(max) as a function of junction temperature Fig 8. VIH(min) as a function of junction temperature

Fig 9. VCC(max) that guarantees bus release limit over temperature

600

800

1000

VOL

(mV)

400

Tj (°C)

002aac069

(1)

(3)

−50 1251007550250−25

(2)

1200

VOL

(mV)

400

Tj (°C)

002aac070

(1)

(3)

(2)

1000

800

600

−50 1251007550250−25

1000

VIL(max)

(mV)

200

Tj (°C)

002aac071

800

600

400

−50 1251007550250−25

1000

VIH(min)

(mV)

200

Tj (°C)

002aac072

800

600

400

−50 1251007550250−25

600

1400

VCC(max)

(mV)

400

Tj (°C)

002aac075

−50 1251007550250−25

800

1000

1200

Product data sheet Rev. 08 — 10 November 2009 10 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

10. Application information

Refer to

AN460

and

AN255

for more application detail.

Fig 10. Interfacing an ‘I2C’ type of bus with different logic levels

Fig 11. Galvanic isolation of I2C-bus nodes via opto-couplers

Fig 12. Long distance I2C-bus communications

1/2 P82B96

I2C-bus

SDA

002aab986

+5 V +VCC (2 V to 15 V)

(SDA)

(SDA) 'SDA' (new levels)

1/2 P82B96

I2C-bus

SDA

002aab987

+5 V

+VCC

(SDA)

+VCC1

I2C-bus

SDA

P82B96

SDA

SCL

002aab988

12 V

12 V3.3 V to 5 V

3.3 V to 5 V

long cables

main enclosure

P82B96

SDA

SCL

3.3 V to 5 V

remote control enclosure

12 V

Product data sheet Rev. 08 — 10 November 2009 11 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Figure 13 shows how a master I2C-bus can be protected against short circuits or failures

in applications that involve plug and socket connections and long cables that may become

damaged. A simple circuit is added to monitor the SDA bus, and if its LOW time exceeds

the design value, then the master bus is disconnected. P82B96 will free all its I/Os if its

supply is removed, so one option is to connect its VCC to the output of a logic gate from,

say, the 74LVC family. The SDA and SCL lines could be timed and VCC disabled via the

gate if one or other lines exceeds a design value of ‘LOW’ period as in

Figure 28 of

AN255

. If the supply voltage of logic gates restricts the choice of VCC supply then the

low-cost discrete circuit in Figure 13 can be used. If the SDA line is held LOW, the 100 nF

capacitor will charge and the Ry input will be pulled towards VCC. When it exceeds 0.5VCC

the Ry input will set the Sy input HIGH, which in practice means simply releasing it.

In this example the SCL line is made unidirectional by tying the Rx pin to VCC. The state of

the buffered SCL line cannot affect the master clock line which is allowed when

clock-stretching is not required. It is simple to add an additional transistor or diode to

control the Rx input in the same way as Ry when necessary. The +V cable drive can be

any voltage up to 15 V and the bus may be run at a lower impedance by selecting pull-up

resistors for a static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the

connected devices. Because DDC uses relatively low speeds (< 100 kHz), the cable

length is not restricted to 20 m by the I2C-bus signalling, but it may be limited by the video

signalling.

Fig 13. Extending a DDC bus

P82B96

SCL

002aab989

VCC

I2C-bus/DDC

master

SDA

VCC1

GND

VCC

SCL

SDA

VCC2

GND

I2C-bus/DDC

slave

4.7 kΩ

847B

100 nF 100

kΩ

+V cable drive

470 kΩ

847B

3 m to 20 m

cables

I2C-bus/DDC

video signals

PC/TV receiver/decoder box

P82B96

monitor/flat TV

+V cable drive

Product data sheet Rev. 08 — 10 November 2009 12 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Figure 14 shows that P82B96 can achieve high clock rates over long cables. While

calculating with lumped wiring capacitance yields reasonable approximations to actual

timing, even 25 meters of cable is better treated using transmission line theory. Flat ribbon

cables connected as shown, with the bus signals on the outer edge, will have a

characteristic impedance in the range 100 Ω to 200 Ω. For simplicity they cannot be

terminated in their characteristic impedance but a practical compromise is to use the

minimum pull-up allowed for P82B96 and place half this termination at each end of the

cable. When each pull-up is below 330 Ω, the rising edge waveforms have their ﬁrst

voltage ‘step’ level above the logic threshold at Rx and cable timing calculations can be

based on the fast rise/fall times of resistive loading plus simple one-way propagation

delays. When the pull-up is larger, but below 750 Ω, the threshold at Rx will be crossed

after one signal reﬂection. So at the sending end it is crossed after 2 times the one-way

propagation delay and at the receiving end after 3 times that propagation delay. For ﬂat

cables with partial plastic dielectric insulation (by using outer cores) the one-way

propagation delays will be about 5 ns per meter. The 10 % to 90 % rise and fall times on

the cable will be between 20 ns and 50 ns, so their delay contributions are small. There

will be ringing on falling edges that can be damped, if required, by using Schottky diodes

as shown.

When the Master SCL HIGH and LOW periods can be programmed separately, for

example using control registers I2SCLH and I2SCLL of 89LPC932, the timings can allow

for bus delays. The LOW period should be programmed to achieve the minimum 1300 ns

plus the net delay in the slave's response data signal caused by bus and buffer delays.

The longest data delay is the sum of the delay of the falling edge of SCL from master to

slave and the delay of the rising edge of SDA from slave data to master. Because the

buffer will ‘stretch’ the programmed SCL LOW period, the actual SCL frequency will be

lower than calculated from the programmed clock periods. In the example for 25 meters

the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns and the SDA rising

edge is delayed 570 ns. The required additional LOW period is

(490 ns + 570 ns) = 1060 ns and the I2C-bus speciﬁcations already include an allowance

for a worst case bus rise time 0 % to 70 % of 425 ns. (The bus rise time can be 300 ns

30 % to 70 %, which means it can be 425 ns 0 % to 70 %. The 25 meter cable delay times

as quoted already include all rise and fall times.) Therefore, the microcontroller only needs

to be programmed with an additional (1060 ns −400 ns −425 ns) = 235 ns, making a

total programmed LOW period 1535 ns. The programmed LOW will the be stretched by

400 ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH

period of 600 ns, yields a cycle period of 2535 ns or 394 kHz.

Note that in both the 100 meter and 250 meter examples, the capacitive loading on the

I2C-buses at each end is within the maximum allowed Standard mode loading of 400 pF,

but exceeds the Fast mode limit. This is an example of a ‘hybrid’ mode because it relies on

the response delays of Fast mode parts but uses (allowable) Standard mode bus loadings

with rise times that contribute signiﬁcantly to the system delays. The cables cause large

propagation delays, so these systems need to operate well below the 400 kHz limit, but

illustrate how they can still exceed the 100 kHz limit provided all parts are capable of

Fast mode operation. The fastest example illustrates how the 400 kHz limit can be

exceeded, provided masters and slaves have the required timings, namely smaller than

the maximum allowed for Fast mode. Many NXP slaves have delays shorter than 600 ns

and all Fm+ devices must be < 450 ns.

Product data sheet Rev. 08 — 10 November 2009 13 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Fig 14. Driving ribbon or ﬂat telephone cables

P82B96

SCL

002aab990

VCC

C2C2

I2C-BUS

MASTER SDA

VCC1

GND

R1 R1

BAT54A

cable

propagation

delay ≈ 5 ns/m

BAT54A

R1 R1

P82B96

VCC

SCL

SDA

VCC2

GND

I2C-BUS

SLAVE(S)

C2C2

+V cable drive

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Product data sheet Rev. 08 — 10 November 2009 14 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Table 6. Examples of bus capability

Refer to Figure 14.

+VCC1 +V

cable +VCC2 R1

(Ω)R2

(Ω)C2

(pF) Cable

length Cable

capacitance Cable

delay Set master nominal SCL Effective

bus clock

speed

Maximum slave

response delay

HIGH period LOW period

5 V 12 V 5 V 750 2.2 k 400 250 m n/a

(delay based) 1.25 µs 600 ns 4000 ns 120 kHz Normal spec.

400 kHz parts

5 V 12 V 5 V 750 2.2 k 220 100 m n/a

(delay based) 500 ns 600 ns 2600 ns 185 kHz Normal spec.

400 kHz parts

3.3 V 5 V 3.3 V 330 1 k 220 25 m 1 nF 125 ns 600 ns 1500 ns 390 kHz Normal spec.

400 kHz parts

3.3 V 5 V 3.3 V 330 1 k 100 3 m 120 pF 15 ns 600 ns 1000 ns 500 kHz 600 ns

Product data sheet Rev. 08 — 10 November 2009 15 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

10.1 Calculating system delays and bus clock frequency for a Fast mode

system

Effective delay of SCL at slave: 255 + 17VCCM + (2.5 + 4 ×109 Cb)VCCB + 10VCCS ns.

C = F; V = volts.

Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times

P82B96 P82B96

SCL

local master bus

VCCM

SCL

MASTER

I2C-BUS Cs

slave bus

capacitance

buffered bus

wiring capacitance

master bus

capacitance

GND (0 V)

VCCB

buffered expansion bus

Tx/Rx Tx/Rx Sx

Rb Rs

I2C-BUS

SLAVE

VCCS

remote slave bus

002aab991

Effective delay of SCL at master: 270 + RmCm + 0.7RbCb ns.

C = F; R = Ω.

Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times

P82B96

local master bus

VCCM

SCL

MASTER

I2C-BUS Cb

buffered bus

wiring capacitance

master bus

capacitance

GND (0 V)

VCCB

buffered expansion bus

Tx/Rx Tx/Rx

002aab992

Product data sheet Rev. 08 — 10 November 2009 16 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Figure 15,Figure 16, and Figure 17 show the P82B96 used to drive extended bus wiring,

with relatively large capacitance, linking two Fast mode I2C-bus nodes. It includes

simpliﬁed expressions for making the relevant timing calculations for 3.3 V or 5 V

operation. Because the buffers and the wiring introduce timing delays, it may be

necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the

actual bus frequency will be lower than the nominal Master timing due to bit-wise

stretching of the clock periods.

The delay factors involved in calculation of the allowed bus speed are:

A — The propagation delay of the master signal through the buffers and wiring to the

slave. The important delay is that of the falling edge of SCL because this edge ‘requests’

the data or acknowledge from a slave. See Figure 15.

B — The effective stretching of the nominal LOW period of SCL at the master caused by

the buffer and bus rise times. See Figure 16.

C — The propagation delay of the slave's response signal through the buffers and wiring

back to the master. The important delay is that of a rising edge in the SDA signal. Rising

edges are always slower and are therefore delayed by a longer time than falling edges.

(The rising edges are limited by the passive pull-up while falling edges are actively driven).

See Figure 17.

The timing requirement in any I2C-bus system is that a slave's data response (which is

provided in response to a falling edge of SCL) must be received at the master before the

end of the corresponding LOW period of SCL as appears on the bus wiring at the master.

Since all slaves will, as a minimum, satisfy the worst case timing requirements of a

400 kHz part, they must provide their response within the minimum allowed clock LOW

period of 1300 ns. Therefore in systems that introduce additional delays it is only

necessary to extend that minimum clock LOW period by any ‘effective’ delay of the slave's

response. The effective delay of the slaves response equals the total delays in SCL falling

Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns.

C = F; R = Ω.

Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times

P82B96 P82B96

SDA

local master bus

VCCM

SDA

MASTER

I2C-BUS Cs

slave bus

capacitance

buffered bus

wiring capacitance

master bus

capacitance

GND (0 V)

VCCB

buffered expansion bus

Tx/Rx Tx/Rx Sx

Rb Rs

I2C-BUS

SLAVE

VCCS

remote slave bus

002aab993

Product data sheet Rev. 08 — 10 November 2009 17 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

edge from the master reaching the slave (Figure 15) minus the effective delay (stretch) of

the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on

SDA, reaching the master (Figure 17).

The master microcontroller should be programmed to produce a nominal SCL LOW

period = (1300 + A −B + C) ns, and should be programmed to produce the nominal

minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle

time is not shorter than the minimum 2500 ns. If found necessary, just increase either

clock period.

Due to clock stretching, the SCL cycle time will always be longer than

(600+1300+A+C)ns.

Example:

The master bus has an RmCm product of 100 ns and VCCM =5V.

The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 Ωto 5 V giving

an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns.

The microcontroller LOW period should be programmed to

≥(1300 + 372.5 −482 + 472) ns, that is ≥1662.5 ns.

Its HIGH period may be programmed to the minimum 600 ns.

The nominal microcontroller clock period will be ≥(1662.5 + 600) ns = 2262.5 ns,

equivalent to a frequency of 442 kHz.

The actual bus clock period, including the 482 ns clock stretch effect, will be below

(nominal + stretch) = (2262.5 + 482) ns or ≥2745 ns, equivalent to an allowable

frequency of 364 kHz.

Fig 18. I2C-bus multipoint application

P82B96

SDA Rx

SCL

002aab994

12 V

3.3 V to 5 V

P82B96

Sx Sy

SCL/SDA

P82B96

Sx Sy

SCL/SDA

P82B96

Sx Sy

SCL/SDA

P82B96

Sx SCL

Sy SDA

no limit to the number of connected bus devices

twitsted-pair telephone wires,

USB, or flat ribbon cables;

up to 15 V logic levels,

include VCC and GND

3.3 V 3.3 V

Product data sheet Rev. 08 — 10 November 2009 18 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

10.2 Negative undershoot below absolute minimum value

The reason why the IC pin reverse voltage on pins Tx and Rx in Table 4 “Limiting values”

is speciﬁed at such a low value, −0.3 V, is not that applying larger voltages is likely to

cause damage but that it is expected that, in normal applications, there is no reason why

larger DC voltages will be applied. This ‘absolute maximum’ speciﬁcation is intended to be

a DC or continuous ratings and the nominal DC I2C-bus voltage LOW usually does not

even reach 0 V. Inside P82B96 at every pin there is a large protective diode connected to

the GND pin and that diode will start to conduct when the pin voltage is more than about

−0.55 V with respect to GND at 25 °C ambient.

Figure 21 shows the measured characteristic for one of those diodes inside P82B96. The

plot was made using a curve tracer that applies 50 Hz mains voltage via a series resistor,

so the pulse durations are long duration (several milliseconds) and are reaching peaks of

over 2 A when more than −1.5 V is applied. The IC becomes very hot during this testing

but it was not damaged. Whenever there is current ﬂowing in any of these diodes it is

possible that there can be faulty operation of any IC. For that reason we put a speciﬁcation

on the negative voltage that is allowed to be applied. It is selected so that, at the highest

allowed junction temperature, there will be a big safety factor that guarantees the diode

will not conduct and then we do not need to make any 100 % production tests to

guarantee the published speciﬁcation.

For the P82B96, in speciﬁc applications, there will always be transient overshoot and

ringing on the wiring that can cause these diodes to conduct. Therefore we designed the

IC to withstand those transients and as a part of the qualiﬁcation procedure we made

tests, using DC currents to more than twice the normal bus sink currents, to be sure that

the IC was not affected by those currents. For example, the Tx/Ty and Rx/Ry pins were

tested to at least −80 mA which, from Figure 21, would be more than −0.8 V. The correct

functioning of the P82B96 is not affected even by those large currents. The Absolute

Maximum (DC) ratings are not intended to apply to transients but to steady state

conditions. This explains why you will never see any problems in practice even if, during

transients, more than −0.3 V is applied to the bus interface pins of P82B96.

Frequency = 624 kHz Ch1 frequency = 624 kHz

Fig 19. Propagation Sx to Tx (Sx pull-up to 5 V;

Tx pull-up to VCC =10V) Fig 20. Propagation Rx to Sx (Sx pull-up to 5 V;

Rx pull-up to VCC =10V)

−2

002aab995

0 20001600800 1200400 −2

002aab996

0 20001600800 1200400

Product data sheet Rev. 08 — 10 November 2009 19 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Figure 21 “Diode characteristic curve” also explains how the general Absolute Maximum

DC speciﬁcation was selected. The current at 25 °C is near zero at −0.55 V. The P82B96

is allowed to operate with +125 °C junction and that would cause this diode voltage to

decrease by 100 ×2 mV = 200 mV. So for zero current we need to specify −0.35 V and we

publish −0.3 V just to have some extra margin.

Remark: You should not be concerned about the transients generated on the wiring by a

P82B96 in normal applications and that is input to the Tx/Rx or Ty/Ry pins of another

P82B96. Because not all ICs that may be driven by P82B96 are designed to tolerate

negative transients, in Section 10.2.1 “Example with questions and answers” we show

they can be managed if required.

Fig 21. Diode characteristic curve

002aaf063

voltage (V)

−2.0 0−0.5−1.5 −1.0

−10

−103

−102

−10−1

−1

−104

diode current

(mA)

Product data sheet Rev. 08 — 10 November 2009 20 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

10.2.1 Example with questions and answers

Question: On a falling edge of Tx we measure undershoot at −800 mV at the linked Tx,

Rx pins of the P82B96 that is generating the LOW, but the P82B96 data sheet speciﬁes

minimum −0.3 V. Does this mean that we violate the data sheet absolute value?

Answer: For P82B96 the −0.3 V Absolute Maximum rating is not intended to apply to

transients, it is a DC rating. As shown in Figure 22, there is no theoretical reason for any

undershoot at the IC that is driving the bus LOW and no signiﬁcant undershoot should

be observed when using reasonable care with the ground connection of the ‘scope. It is

more likely that undershoot observed at a driving P82B96 is caused by local stray

inductance and capacitance in the circuit and by the oscilloscope connections. As

shown, undershoot will be generated by PCB traces, wiring, or cables driven by a

P82B96 because the allowed value of the I2C-bus pull-up resistor generally is larger

than that required to correctly terminate the wiring. In this example, with no IC

connected at the end of the wiring, the undershoot is about 2 V.

Fig 22. Transients generated by the bus wiring

002aaf064

time (ns)

voltage

(V)

−2horizontal scale = 62.5 ns/div

send

receive

5 V

P82B96

send

300 Ω

5 V

2 meter

cable

5 V

300 Ω

GND

receive

Product data sheet Rev. 08 — 10 November 2009 21 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Question: We have 2 meters of cable in a bus that joins the Tx/Rx sides of two P82B96

devices. When one Tx drives LOW the other P82B96 Tx/Rx is driven to −0.8 V for over

50 ns. What is the expected value and the theoretically allowed value of undershoot?

Answer: Because the cable joining the two P82B96s is a ‘transmission line’ that will

have a characteristic impedance around 100 Ω and it will be terminated by pull-up

resistors that are larger than that characteristic impedance there will always be negative

undershoot generated. The duration of the undershoot is a function of the cable length

and the input impedance of the connected IC. As shown in Figure 23, the transient

undershoot will be limited, by the diodes inside P82B96, to around −0.8 V and that will

not cause problems for P82B96. Those transients will not be passed inside the IC to the

Sx/Sy side of the IC.

Question: If we input 800 mV undershoot at Tx, Rx pins, what kind of problem is

expected?

Answer: When that undershoot is generated by another P82B96 and is simply the

result of the system wiring, then there will be no problems.

Question: Will we have any functional problem or reliability problem?

Answer: No.

Fig 23. Wiring transients limited by the diodes in P82B96

002aaf065

time (ns)

voltage

(V)

−2horizontal scale = 62.5 ns/div

send receive

5 V

P82B96

send

300 Ω

5 V

2 meter

cable

5 V

300 Ω

GND

receive Sx

5 V

Product data sheet Rev. 08 — 10 November 2009 22 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Question: If we add 100 Ω to 200 Ω at signal line, the overshoot becomes slightly

smaller. Is this a good idea?

Answer: No, it is not necessary to add any resistance. When the logic signal generated

by Tx or Ty of P82B96 drives long traces or wiring with ICs other than P82B96 being

driven, then adding a Schottky diode (BAT54A) as shown in Figure 24 will clamp the

wiring undershoot to a value that will not cause conduction of the IC’s internal diodes.

Fig 24. Wiring transients limited by a Schottky diode

002aaf066

time (ns)

voltage

(V)

−2horizontal scale = 62.5 ns/div

receive

5 V

P82B96

send

300 Ω

5 V

2 meter

cable

5 V

300 Ω

GND

receive Sx

5 V

send

1/2 BAT54A

Product data sheet Rev. 08 — 10 November 2009 23 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

11. Package outline

Fig 25. Package outline SOT97-1 (DIP8)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT97-1 99-12-27

03-02-13

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.14 0.53

0.38 0.36

0.23 9.8

9.2 6.48

6.20 3.60

3.05 0.2542.54 7.62 8.25

7.80 10.0

8.3 1.154.2 0.51 3.2

inches 0.068

0.045 0.021

0.015 0.014

0.009

1.07

0.89

0.042

0.035 0.39

0.36 0.26

0.24 0.14

0.12 0.010.1 0.3 0.32

0.31 0.39

0.33 0.0450.17 0.02 0.13

050G01 MO-001 SC-504-8

(e )

seating plane

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

pin 1 index

DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1

Product data sheet Rev. 08 — 10 November 2009 24 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Fig 26. Package outline SOT96-1 (SO8)

UNIT A

max. A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 5.0

4.8 4.0

3.8 1.27 6.2

5.8 1.05 0.7

0.6 0.7

0.3 8

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.0

0.4

SOT96-1

detail X

vMA

(A )

pin 1 index

076E03 MS-012

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.20

0.19 0.16

0.15 0.05 0.244

0.228 0.028

0.024 0.028

0.012

0.010.010.041 0.004

0.039

0.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-27

03-02-18

Product data sheet Rev. 08 — 10 November 2009 25 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

Fig 27. Package outline SOT505-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Product data sheet Rev. 08 — 10 November 2009 26 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

12. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note

AN10365 “Surface mount reﬂow

soldering description”

12.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

12.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

•Board speciﬁcations, including the board ﬁnish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

12.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

Product data sheet Rev. 08 — 10 November 2009 27 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

12.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 28) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 7 and 8

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 28.

Table 7. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 ≥ 350

< 2.5 235 220

≥ 2.5 220 220

Table 8. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 08 — 10 November 2009 28 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

For further information on temperature proﬁles, refer to Application Note

AN10365

“Surface mount reﬂow soldering description”

13. Soldering of through-hole mount packages

13.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

13.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (Tstg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

13.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

MSL: Moisture Sensitivity Level

Fig 28. Temperature proﬁles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 08 — 10 November 2009 29 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

13.4 Package related soldering information

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

14. Abbreviations

Table 9. Suitability of through-hole mount IC packages for dipping and wave soldering

Package Soldering method

Dipping Wave

CPGA, HCPGA - suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1]

PMFP[2] - not suitable

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

DDC Display Data Channel

ESD ElectroStatic Discharge

HBM Human Body Model

IC Integrated Circuit

I2C-bus Inter IC bus

MM Machine Model

SMBus System Management Bus

Product data sheet Rev. 08 — 10 November 2009 30 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

15. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

P82B96_8 20091110 Product data sheet - P82B96_7

Modiﬁcations: •Table 4 “Limiting values”: added Table note [1].

•Added Section 10.2 “Negative undershoot below absolute minimum value”.

P82B96_7 20090212 Product data sheet - P82B96_6

P82B96_6 20080131 Product data sheet - P82B96_5

P82B96_5 20060127 Product data sheet - P82B96_4

P82B96_4

(9397 750 12932) 20040329 Product data - P82B96_3

P82B96_3

(9397 750 11351) 20030402 Product data 853-2241 29602

of 2003 Feb 28 P82B96_2

P82B96_2

(9397 750 11093) 20030220 Product data 853-2241 29410

of 2003 Jan 22 P82B96_1

P82B96_1

(9397 750 08122) 20010306 Product data 853-2241 25758

of 2001 Mar 06 -

Product data sheet Rev. 08 — 10 November 2009 31 of 32

NXP Semiconductors P82B96

Dual bidirectional bus buffer

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors P82B96

Dual bidirectional bus buffer

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 10 November 2009

Document identifier: P82B96_8

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 4

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

9 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6

10 Application information. . . . . . . . . . . . . . . . . . 10

10.1 Calculating system delays and bus clock

frequency for a Fast mode system . . . . . . . . . 15

10.2 Negative undershoot below absolute minimum

value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.2.1 Example with questions and answers. . . . . . . 20

11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23

12 Soldering of SMD packages . . . . . . . . . . . . . . 26

12.1 Introduction to soldering. . . . . . . . . . . . . . . . . 26

12.2 Wave and reﬂow soldering . . . . . . . . . . . . . . . 26

12.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 26

12.4 Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 27

13 Soldering of through-hole mount packages . 28

13.1 Introduction to soldering through-hole mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13.2 Soldering by dipping or by solder wave . . . . . 28

13.3 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 28

13.4 Package related soldering information . . . . . . 29

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 30

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 31

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

16.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31

17 Contact information. . . . . . . . . . . . . . . . . . . . . 31

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32