UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 2µA (typical) L-version
1µA (typical) LL-version
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8mmx20mm TSOP-1
32-pin 8mmx13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
COLUMN I/O
COLUMN DECODER
ROW
DECODER
I/O
CONTROL
LOGI C
CONTROL
A15
I/O1
V
SS
V
CC
WE
OE
1CE
I/O8
.
.
.
.
.
.
. .
.
A13
A
7
A6
A5
A4
A8
A
11
A
2 A1
A
0
A
10
.
.
.
.
.
.
MEMORY ARRAY
1024 ROWS × 1024 COLUMNS
A
9
A14
A12
A16
A
3
CE2
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
1CE ,CE2 Chip enable 1,2 Inputs
WE Write Enable Input
OE Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
GENERAL DESCRIPTION
The UT621024 is a 1,048,576-bit low power
CMOS static random access memory
organized as 131,072 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
The UT621024 is designed for low power
application. It is particularly well suited for
battery back-up nonvolatile memory
application.
The UT621024 operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT621024
PDIP / SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
1CE
WE
OE
A13
A14
NC
A16
Vcc
A15
29
30
31
32
TSOP-I/STSOP
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4 A3
UT621024
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
1CE
CE2
NC
A15
A16
32
31
30
29
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to Vss VTERM -0.5 to +7.0 V
Operating Temperature TA 0 to +70 ℃
Storage Temperature TSTG -65 to +150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
Soldering Temperature (under 10 sec) Tsolder 260 ℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended
period may affect device reliability.
TRUTH TABLE
MODE 1CE CE2 OE WE I/O OPERATION SUPPLY CURRENT
Standby H X X X High - Z ISB,ISB1
Standby X L X X High -Z ISB,ISB1
Output Disable L H H H High - Z ICC
Read L H L H DOUT ICC
Write L H X L DIN ICC
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS (VCC = 5V±10%, TA = 0℃ to 70℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage VIH 2.2 - VCC+0.5 V
Input Low Voltage VIL - 0.5 - 0.8 V
Input Leakage Current IIL VSS ≦VIN ≦VCC - 1 - 1 µA
Output Leakage Curren
t
IOL VSS ≦VI/O≦VCC
1CE =VIH or CE2 = VIL or
OE = VIH or WE = VIL
- 1 - 1 µA
Output High Voltage VOH IOH = - 1mA 2.4 - - V
Output Low Voltage VOL IOL= 4mA - - 0.4 V
ICC Cycle time=min, 100% duty,
1CE =VIL, CE2 = VIH,
II/O = 0mA
-35
-55
-70
-
-
-
60
50
40
100
85
70
mA
mA
mA
Average Operating
Power Supply Courrent
ICC1 Cycle time=1µs,100% duty,II/O=0mA
.1CE ≦0.2V,CE2≧VCC-0.2V,
other pins at 0.2V or VCC-0.2V,
- - 10 mA
ISB 1CE =VIH or CE2 = VIL
other pins at 0.2V or VCC-0.2V, - - 3 mA
100
- L - 2 40*
µA
50
Standby Power
Supply Current
ISB1 1CE ≧VCC-0.2V or
.CE2≦0.2V
other pins at 0.2V or VCC-0.2V, -
LL - 1 15* µA
*Those parameters are for reference only under 50℃
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance CIN - 8 pF
Input/Output Capacitance CI/O - 10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL=100pF, IOH/IOL=-1mA/4mA
AC ELECTRICAL CHARACTERISTICS (VCC = 5V±10% , TA = 0℃ to 70℃)
(1) READ CYCLE
PARAMETER
SYMBOL UT621024-35 UT621024-55 UT621024-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time tRC 35 - 55 - 70 - ns
Address Access Time tAA - 35 - 55 - 70 ns
Chip Enable Access Time tACE1, tACE2 - 35 - 55 - 70 ns
Output Enable Access Time tOE - 25 - 30 - 35 ns
Chip Enable to Output in Low-Z tCLZ1*, tCLZ2* 10 - 10 - 10 - ns
Output Enable to Output in Low-Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High-Z tCHZ1*, tCHZ2* - 25 - 30 - 35 ns
Output Disable to Output in High-Z tOHZ* - 25 - 30 - 35 ns
Output Hold from Address Change tOH 5 - 5 - 5 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL UT621024-
35 UT621024-55 UT621024-70 UNIT
MIN. MAX. MIN.
MAX. MIN. MAX.
Write Cycle Time tWC 35 - 55 - 70 - ns
Address Valid to End of Write tAW 30 - 50 - 60 - ns
Chip Enable to End of Write tCW1, tCW2 30 - 50 - 60 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 25 - 40 - 45 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 20 - 25 - 30 - ns
Data Hold from End of Write-Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High-Z tWHZ* - 15 - 20 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
DOUT Data Valid
tAA
tOH tOH
READ CYCLE 2 ( 1CE , CE2 and OE Controlled) (1,3,5,6)
Notes :
1. WE is HIGH for read cycle.
2. Device is continuously selected 1
CE =VIL and CE2=VIH.
3. Address must be valid prior to or coincident with 1
CE and CE2 transition; otherwise tAA is the limiting parameter.
4. OE is low.
5. tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.
tRC
tAA
tACE1
tACE2
tOE
tOLZ
t
CLZ1
tCLZ2
High-Z
tCHZ1
tCHZ2 tOHZ
tOH
Data Valid High-Z
A
ddress
1CE
CE2
OE
DOUT
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
WRITE CYCLE 1 ( WE Controlled) (1,2,3,5)
Address
DOUT
High-Z
1CE
WE
Data Valid
DIN
CE2
tCW2
tCW1
tAW
tWC
tWHZ
tWP
tAS
tOW
tDW tDH
tWR
(4) (4)
WRITE CYCLE 2 ( 1
CE and CE2 Controlled) (1,2,5)
Address
DOUT
High-Z
1CE
WE
(4)
Data Valid
DIN
CE2
tWC
tAS tCW1
tAW
tCW2
tWR
tWP
tWHZ
tDW tDH
Notes :
1. WE or 1CE must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low 1CE , a high CE2 and a low WE .
3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the 1CE LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high
impedance state.
6. tOW and tWHZ are specified with CL=5pF. Transition is measured ±500mV from steady state.
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
DATA RETENTION CHARACTERISTICS (TA = 0℃ to 70℃)
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
VDR 1CE ≧ VCC-0.2V or
CE2 ≤ 0.2V
2.0 - - V
40 Data Retention Current IDR Vcc=3V - L - 1 20*
µA
20
1CE ≧ VCC-0.2V or
CE2 ≤ 0.2V
- LL - 0.5 10*
µA
Chip Disable to Data tCDR See Data Retention 0 - - ns
Retention Time Waveforms (below)
Recovery Time
tR tRC* - - ns
tRC* = Read Cycle Time
*Those parameters are for reference only under 50℃
DATA RETENTION WAVEFORM
tCDR tR
4.5V
VCC
1CE
VSS
Date Retention Mode
VDR ≧ 2.0V
1CE ≧ VCC -0.2V
4.5V
VIL VIL
VIH VIH
CE2 ≤ 0.2V
CE2
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
PACKAGE OUTLINE DIMENSION
32 pin 600 mil PDIP Package Outline Dimension
UNIT
SYMBOL INCH(BASE) MM(REF)
A1 0.010 (MIN) 0.254 (MIN)
A2 0.150 ±0.005 3.810
±0.127
B 0.018 ±0.005 0.457
±0.127
B1 0.050 ± 0.005 1.270 ±0.127
c 0.010±0.004 0.254±0.102
D 1.650 ±0.005 41.910
±0.127
E 0.600 ±0.010 15.240
±0.254
E1 0.544 ±0.004 13.818
±0.102
e 0.100(TYP) 2.540(TYP)
eB 0.640 ±0.020 16.256
±0.508
L 0.130 ±0.010 3.302
±0.254
S 0.075 ±0.010 1.905±0.254
Q1 0.070±0.005 1.778±0.127
Note:
1. D/E1/S DIMENSION DO NOT INCLUDE MOLD FLASH.
A
A
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
32 pin 450mil SOP Package Outline Dimension
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.118 (MAX) 2.997 (MAX)
A1 0.004(MIN) 0.102(MIN)
A2 0.111(MAX) 2.82(MAX)
b 0.015(MIN)
0.020(MAX)
0.38(MIN)
0.50(MAX)
c 0.008(TYP) 0.203(TYP)
D 0.817(MAX) 20.75(MAX)
E 0.445 ±0.005 11.303
±0.127
E1 0.555 ±0.005 14.097
±0.127
e 0.050(TYP) 1.270(TYP)
L 0.0347 ±0.008 0.881
±0.203
L1 0.055 ±0.008 1.397
±0.203
S 0.026(MAX) 0.660 (MAX)
y 0.004(MAX) 0.101(MAX)
Θ 0o -10o 0
o -10o
A
C
A
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
32 pin TSOP-I Package Outline Dimension
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1 0.004 ±0.002 0.10
±0.05
A2 0.039 ±0.002 1.00
±0.05
b 0.008 + 0.002
- 0.001
0.20 + 0.05
-0.03
c 0.005 (TYP) 0.127 (TYP)
D 0.724 ±0.004 18.40
±0.10
E 0.315 ±0.004 8.00
±0.10
e 0.020 (TYP) 0.50 (TYP)
HD 0.787 ±0.008 20.00
±0.20
L 0.0197 ±0.004 0.50
±0.10
L1 0.0315 ±0.004 0.08
±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ 0
o〜5o 0
o〜5o
H
C
C
E
B
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
Uni
t
Symbol
MM(REF) INCH(BASE)
A 1.20
(
Max.
)
0.047
(
Max
)
.
A1 0.10±0.05 0.004±0.002
A2 1.00±0.05 0.039±0.002
b 020
(
TYP.
)
0.006
(
TYP.
)
c 0.15
(
TYP.
)
0.006
(
TYP.
)
D 13.40±0.20 0.526±0.006
Db 11.80±0.10 0.465±0.004
E 8.000±0.10 0.315±0.004
e 0.50
(
TYP.
)
0.020
(
TYP.
)
L 0.50±0.10 0.020±0.004
L1 0.80±0.10 0.0315±0.004
y
0.08
(
Max.
)
0.003
(
Max.
)
e 0~5 0
~5
Note：
1.E dinmension is not including end
flash.
2.The total of both sides’ end flash Is
not above 0.3mm.
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
ORDERING INFORMATION
PART NO. ACCESS TIME
(ns)
STANDBY CURRENT
(µA)
PACKAGE
UT621024PC-35L 35 100 32 PIN PDIP
UT621024PC-35LL 35 50 32 PIN PDIP
UT621024SC-35L 35 100 32 PIN SOP
UT621024SC-35LL 35 50 32 PIN SOP
UT621024LC-35L 35 100 32 PIN TSOP-I
UT621024LC-35LL 35 50 32 PIN TSOP-I
UT621024LS-35L 35 100 32 PIN STSOP
UT621024LS-35LL 35 50 32 PIN STSOP
UT621024PC-55L 55 100 32 PIN PDIP
UT621024PC-55LL 55 50 32 PIN PDIP
UT621024SC-55L 55 100 32 PIN SOP
UT621024SC-55LL 55 50 32 PIN SOP
UT621024LC-55L 55 100 32 PIN TSOP-I
UT621024LC-55LL 55 50 32 PIN TSOP-I
UT621024LS-55L 55 100 32 PIN STSOP
UT621024LS-55LL 55 50 32 PIN STSOP
UT621024PC-70L 70 100 32 PIN PDIP
UT621024PC-70LL 70 50 32 PIN PDIP
UT621024SC-70L 70 100 32 PIN SOP
UT621024SC-70LL 70 50 32 PIN SOP
UT621024LC-70L 70 100 32 PIN TSOP-I
UT621024LC-70LL 70 50 32 PIN TSOP-I
UT621024LS-70L 70 100 32 PIN STSOP
UT621024LS-70LL 70 50 32 PIN STSOP
UTRON UT621024
Rev. 1.5 128K X 8 BIT LOW POWER CMOS SRAM
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC. P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
REVISION HISTORY
REVISION DESCRIPTION DATE
REV. 1.0 Original. Apr. 05 2000
REV. 1.1 NA --
REV. 1.2 NA --
REV. 1.3 Add STSOP-I Package Aug. 29.2000
REV. 1.4 Modify the format of power consumption Sep. 01.2000
REV. 1.5 1. Operating : 60/40 -> 60/50/40
2. Standby Current : 10 ->2 (L-version)
3. Add ICC–data as (-55, TYP 50, MAX 85)
4. Revise ISB1 TYP : 10-> 2, MAX : 300/100 ->100/40
5. The symbols CE1# ,OE# & WE# are revised as
1CE ,OE &WE
Jun. 18,2001
