TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 D Push-Pull CMOS Output Drives Capacitive D D Loads Without Pullup Resistor, IO = 8 mA Very Low Power . . . 200 W Typ at 5 V Fast Response Time . . . tPLH = 2.7 s Typ With 5-mV Overdrive Single Supply Operation . . . 3 V to 16 V TLC3704M . . . 4 V to 16 V On-Chip ESD Protection 1OUT 2OUT VDD 2IN - 2IN + 1IN - 1IN + description 2 13 3 12 4 11 5 10 6 9 7 8 3OUT 4OUT GND 4IN + 4IN - 3IN + 3IN - PW PACKAGE (TOP VIEW) 1OUT 2OUT VDD 2IN - 2IN + 1IN - 1IN + 1 2 3 4 5 6 7 14 13 12 11 10 9 8 3OUT 4OUT GND 4IN + 4IN - 3IN + 3IN - FK PACKAGE (TOP VIEW) Texas Instruments LinCMOS process offers superior analog performance to standard CMOS processes. Along with the standard CMOS advantages of low power without sacrificing speed, high input impedance, and low bias currents, the LinCMOS process offers extremely stable input offset voltages with large differential input voltages. This characteristic makes it possible to build reliable CMOS comparators. VDD NC 2IN - NC 2IN + 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 1IN- 1IN+ NC The TLC3704C is characterized for operation over the commercial temperature range of 0C to 70C. The TLC3704I is characterized for operation over the extended industrial temperature range of - 40C to 85C. The TLC3704M is characterized for operation over the full military temperature range of - 55C to 125C. The TLC3704Q is characterized for operation from - 40C to 125C. 14 2OUT 1OUT NC 3OUT 4OUT The TLC3704 consists of four independent micropower voltage comparators designed to operate from a single supply and be compatible with modern HCMOS logic systems. They are functionally similar to the LM339 but use 1/20th the power for similar response times. The push-pull CMOS output stage drives capacitive loads directly without a power-consuming pullup resistor to achieve the stated response time. Eliminating the pullup resistor not only reduces power dissipation, but also saves board space and component cost. The output stage is also fully compatible with TTL requirements. 1 GND NC 4IN + NC 4IN - 3IN- 3IN+ D D D, J, OR N PACKAGE (TOP VIEW) NC - No internal connection symbol (each comparator) IN + OUT IN - Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. LinCMOS is a trademark of Texas Instruments Incorporated. Copyright 2009, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 AVAILABLE OPTIONS PACKAGE TA VIOmax at 25C 0C to 70C 5 mV SMALL OUTLINE (D) CERAMIC (FK) CERAMIC DIP (J) PLASTIC DIP (N) TSSOP (PW) TLC3704CD -- -- TLC3704CN TLC3704CPW -40C to 85C 5 mV TLC3704ID -- -- TLC3704IN TLC3704IPW -55C to 125C 5 mV TLC3704MD TLC3704MFK TLC3704MJ -- -- -40C to 125C 5 mV -- -- TLC3704QJ -- -- The D and PW packages are available taped and reeled. Add R suffix to the device type (e.g., TLC3704CDR). functional block diagram (each comparator) VDD IN+ Differential Input Circuits OUT IN- GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 18 V Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to VDD Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Output current, IO (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Total supply current into VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: TLC3704C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70C TLC3704I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C TLC3704M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to 125C TLC3704Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to network ground. 2. Differential voltages are at IN+ with respect to IN -. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 DISSIPATION RATING TABLE PACKAGE D FK J N PW TA 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING 7.6 mW/C 11.0 mW/C 11.0 mW/C 9.2 mW/C 5.4 mW/C 608 mW 880 mW 880 mW 736 mW 432 mW 494 mW 715 mW 715 mW 598 mW 351 mW N/A 275 mW 275 mW N/A N/A 950 mW 1375 mW 1375 mW 1150 mW 675 mW recommended operating conditions TLC3704C Supply voltage, VDD Common-mode input voltage, VIC MIN NOM 3 5 - 0.2 16 V VDD - 1.5 High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA UNIT MAX 0 V - 20 mA 20 mA 70 C electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise noted) PARAMETER VIO Input offset voltage IIO Input offset current TLC3704C TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, TA MIN 25C See Note 3 1.2 0C to 70C VICR CMRR kSVR Input bias current 70C VIC = 2.5 25V 0.3 25C 0C to 70C 0 to VDD - 1.5 Common-mode Common mode rejection ratio Supply-voltage Supply voltage rejection ratio VIC = VICRmin VDD = 5 V to 10 V VOH High level output voltage High-level V VID = 1 V, IOH = - 4 mA VOL Low level output voltage Low-level VID = -1 1 V, V IOH = 4 mA IDD Supply current (all four comparators) Outputs low low, No load 84 70C 84 0C 84 25C 85 70C 85 0C 85 25C 4.5 4.3 25C nA dB dB 4.7 V 210 70C 25C nA V 25C 70C mV pA 0.6 0 to VDD - 1 UNIT pA 5 70C Common mode input voltage range Common-mode 5 1 25C IIB MAX 6.5 25C VIC = 2.5 25V TYP 300 375 35 0C to 70C 80 100 mV A All characteristics are measured with zero common-mode voltage unless otherwise noted. NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 recommended operating conditions TLC3704I Supply voltage, VDD Common-mode input voltage, VIC MIN NOM 3 5 - 0.2 16 V VDD - 1.5 High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA UNIT MAX - 40 V - 20 mA 20 mA 85 C electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless otherwise noted) TLC3704I PARAMETER VIO Input offset voltage IIO Input offset current TA TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, MIN 25C See Note 3 VICR CMRR kSVR Input bias current Supply-voltage Supply voltage rejection ratio 5 1 85C 25V VIC = 2.5 1 0 to VDD - 1 -40C to 85C 0 to VDD - 1.5 VIC = VICRmin VDD = 5 V to 10 V VOH High level output voltage High-level VID = 1 V, V IOH = - 4 mA VOL Low level output voltage Low-level VID = -1 1 V, V IOH = 4 mA IDD Supply current (all four comparators) Outputs low low, No load 84 85C 84 -40C 83 25C 85 85C 85 -40C 83 25C 4.5 4.3 25C POST OFFICE BOX 655303 210 dB 300 400 35 -40C to 85C * DALLAS, TEXAS 75265 dB V NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V. 4 nA 4.7 85C 25C nA V 25C 85C mV pA 2 25C UNIT pA 5 85C Common mode input voltage range Common-mode Common-mode Common mode rejection ratio 1.2 7 25C IIB MAX -40C to 85C 25C VIC = 2.5 25V TYP 80 125 mV A TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 recommended operating conditions TLC3704M MIN NOM Supply voltage, VDD 4 5 Common-mode input voltage, VIC 0 16 V VDD - 1.5 V - 20 mA 20 mA 125 C High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA UNIT MAX - 55 electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless otherwise noted) TLC3704M PARAMETER VIO Input offset voltage IIO Input offset current TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, TA MIN 25C See Note 3 1.2 -55C to 125C VICR CMRR kSVR Input bias current 125C 25V VIC = 2.5 15 0 to VDD - 1 -55C to 125C 0 to VDD - 1.5 Common-mode Common mode rejection ratio Supply-voltage Supply voltage rejection ratio VIC = VICRmin VDD = 5 V to 10 V VOH High level output voltage High-level VID = 1 V, V IOH = - 4 mA VOL Low level output voltage Low-level VID = -1 1 V, V IOH = 4 mA IDD Supply current (all four comparators) Outputs low low, No load 25C 84 83 -55C 82 25C 85 125C 85 -55C 82 25C 4.5 4.2 25C nA dB dB 4.7 V 210 125C 25C nA V 125C 125C mV pA 30 25C UNIT pA 5 125C Common mode input voltage range Common-mode 5 1 25C IIB MAX 10 25C VIC = 2.5 25V TYP 300 500 35 -55C to 125C 80 175 mV A NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 recommended operating conditions TLC3704Q MIN NOM 3 5 Supply voltage, VDD Common-mode input voltage, VIC 16 -0.2 V VDD - 1.5 High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA UNIT MAX - 40 V - 20 mA 20 mA 125 C electrical characteristics at specified operating free-air temperature, VDD = 5 V, VIC = 0 (unless otherwise noted) TLC3704Q PARAMETER VIO Input offset voltage IIO Input offset current TEST CONDITIONS VDD = 5 V to 10 V, VIC = VICRmin, TA MIN 25C See Note 3 Input bias current VICR Common mode input voltage Common-mode range CMRR Common-mode Common mode rejection ratio kSVR Supply-voltage Supply voltage rejection ratio 1.2 5 7 1 125C 5V VIC = 2 2.5 5 125C VIC = VICRmin VDD = 5 V to 10 V VOH High level output voltage High-level V VID = 1 V, IOH = - 4 mA VOL Low level output voltage Low-level VID = -1 1 V, V IOH = 4 mA IDD Supply current (all four comparators) Outputs low low, No load 25C 0 to VDD - 1 0 to VDD - 1.5 25C 84 83 -40C 83 25C 85 125C 85 -40C 83 25C 4.5 4.2 25C POST OFFICE BOX 655303 210 dB 300 500 35 -40C to 125C * DALLAS, TEXAS 75265 dB V NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V. 6 nA 4.7 125C 25C nA V 125C 125C mV pA 30 -40C to 125C UNIT pA 15 25C IIB MAX -40C to 125C 25C VIC = 2 2.5 5V TYP 80 175 mV A TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 switching characteristics, VDD = 5 V, TA = 25C PARAMETER TEST CONDITIONS TLC3704C, TLC3704I TLC3704M, TLC3704Q MIN tPLH time low-to-high-level low to high level output Propagation delay time, f = 10 kH kHz, CL = 50 pF Overdrive = 2 mV 4.5 Overdrive = 5 mV 2.7 Overdrive = 10 mV 1.9 Overdrive = 20 mV 1.4 Overdrive = 40 mV 1.1 VI = 1.4-V step at IN + tPHL Propagation delay time, time high-to-low-level high to low level output f = 10 kH kHz, CL = 50 pF UNIT MAX ss 1.1 Overdrive = 2 mV 4 Overdrive = 5 mV 2.3 Overdrive = 10 mV 1.5 Overdrive = 20 mV 0.95 Overdrive = 40 mV 0.65 VI = 1.4-V step at IN + TYP ss 0.15 tf Fall time f = 10 kHz, CL = 50 pF Overdrive = 50 mV 50 ns tr Rise time f = 10 kHz, CL = 50 pF Overdrive = 50 mV 125 ns Simultaneous switching of inputs causes degradation in output response. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 PRINCIPLES OF OPERATION LinCMOS process The LinCMOS process is a linear polysilicon-gate CMOS process. Primarily designed for single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance analog functions from operational amplifiers to complex mixed-mode converters. This short guide is intended to answer the most frequently asked questions related to the quality and reliability of LinCMOS products. Direct further questions to the nearest TI field sales office. electrostatic discharge CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to CMOS devices. It can occur when a device is handled without proper consideration for environmental electrostatic charges, e.g., during board assembly. If a circuit in which one amplifier from a dual op amp is being used and the unused pins are left open, high voltages tends to develop. If there is no provision for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail. To prevent voltage buildup, each pin is protected by internal circuitry. Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more transistors break down at voltages higher than the normal operating voltages but lower than the breakdown voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as tens of picoamps. To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in Figure 1. This circuit can withstand several successive 2-kV ESD pulses, while reducing or eliminating leakage currents that may be drawn through the input pins. A more detailed discussion of the operation of the TI ESD-protection circuit is presented on the next page. All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection circuitry that undergoes qualification testing to withstand 2000 V discharged from a 100-pF capacitor through a 1500- resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor (charged device model). These tests simulate both operator and machine handling of devices during normal test and assembly operations. VDD R1 Input To Protected Circuit R2 Q1 Q2 D1 D2 D3 GND Figure 1. LinCMOS ESD-Protection Schematic 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 PRINCIPLES OF OPERATION input protection circuit operation Texas Instruments patented protection circuitry allows for both positive- and negative-going ESD transients. These transients are characterized by extremely fast rise times and usually low energies, and can occur both when the device has all pins open and when it is installed in a circuit. positive ESD transients Initial positive charged energy is shunted through Q1 to VSS. Q1 turns on when the voltage at the input rises above the voltage on the VDD pin by a value equal to the VBE of Q1. The base current increases through R2 with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2 to exceed its threshold level (VT 22 to 26 V) and turn Q2 on. The shunted input current through Q1 to VSS is now shunted through the n-channel enhancement-type MOSFET Q2 to VSS. If the voltage on the input pin continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 to 27 V, which is well below the gateoxide voltage of the circuit to be protected. negative ESD transients The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1 and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is - 0.3 V to -1 V (the forward voltage of D1 and D2). circuit-design considerations LinCMOS products are being used in actual circuit environments that have input voltages that exceed the recommended common-mode input voltage range and activate the input protection circuit. Even under normal operation, these conditions occur during circuit power up or power down, and in many cases, when the device is being used for a signal conditioning function. The input voltages can exceed VICR and not damage the device only if the inputs are current limited. The recommended current limit shown on most product data sheets is 5 mA. Figures 2 and 3 show typical characteristics for input voltage versus input current. Normal operation and correct output state can be expected even when the input voltage exceeds the positive supply voltage. Again, the input current should be externally limited even though internal positive current limiting is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input current. This base current is forced into the VDD pin and into the device IDD or the VDD supply through R2 producing the current limiting effects shown in Figure 2. This internal limiting lasts only as long as the input voltage is below the VT of Q2. When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is required (see Figure 4). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 PRINCIPLES OF OPERATION circuit-design considerations (continued) INPUT CURRENT vs INPUT VOLTAGE INPUT CURRENT vs INPUT VOLTAGE 8 10 TA = 25 C TA = 25 C 9 7 I I - Input Current - mA I I - Input Current - mA 8 6 5 4 3 2 7 6 5 4 3 2 1 1 0 VDD VDD + 4 VDD + 8 VDD + 12 0 VDD - 0.3 VI - Input Voltage - V VDD - 0.5 VDD - 0.7 VDD - 0.9 VI - Input Voltage - V Figure 2 Figure 3 VDD RI VI Positive Voltage Input Current Limit : + 1/2 TLC3704 Vref RI + - V I * V DD * 0.3 V 5 mA Negative Voltage Input Current Limit : * V I * V DD * (* 0.3 V) RI + 5 mA See Note A NOTE A: If the correct input state is required when the negative input exceeds GND, a Schottky clamp is required. Figure 4. Typical Input Current-Limiting Configuration for a LinCMOS Comparator 10 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 PARAMETER MEASUREMENT INFORMATION The TLC3704 contains a digital output stage which, if held in the linear region of the transfer curve, can cause damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo loop which is designed to force the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, we offer the following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc. To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown in Figure 5(a). With the noninverting input positive with respect to the inverting input, the output should be high. With the input polarity reversed, the output should be low. A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can be slewed as shown in Figure 5(b) for the VICR test, rather than changing the input voltages, to provide greater accuracy. 5V 1V + Applied VIO + - Limit Applied VIO VO - Limit VO -4V (a) VIO WITH VIC = 0 V (b) VIO WITH VIC = 4 V Figure 5. Method for Verifying That Input Offset Voltage Is Within Specified Limits A close approximation of the input offset voltage can be obtained by using a binary search method to vary the differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but opposite in polarity, to the input offset voltage, the output changes states. Figure 6 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the comparator in the linear region. The circuit consists of a switching mode servo loop in which IC1a generates a triangular waveform of approximately 20-mV amplitude. IC1b acts as a buffer, with C2 and R4 removing any residual d.c. offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input is driven by the output of the integrator formed by IC1c through the voltage divider formed by R8 and R9. The loop reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input exactly equals the input offset voltage. Voltage divider R8 and R9 provides an increase in the input offset voltage by a factor of 100 to make measurement easier. The values of R5, R7, R8, and R9 can significantly influence the accuracy of the reading; therefore, it is suggested that their tolerance level be one percent or lower. Measuring the extremely low values of input current requires isolation from all other sources of leakage current and compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage can be measured with no device in the socket. Subsequently, this open socket leakage value can be subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the device. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 PARAMETER MEASUREMENT INFORMATION VDD IC1a 1/4 TLC274CN + Buffer C2 1 F R6 1 M - C3 0.68 F R5 1.8 k 1% IC1c 1/4 TLC274CN DUT - R4 47 k - VIO (X100) + + R7 1.8 k 1% R1 240 k Integrator C4 0.1 F IC1b 1/4 TLC274CN - C1 0.1 F + R3 100 Triangle Generator R9 100 1% R8 10 k 1% R2 10 k Figure 6. Circuit for Input Offset Voltage Measurement Response time is defined as the interval between the application of an input step function and the instant when the output reaches 50% of its maximum value. Response time for the low-to-high-level output is measured from the leading edge of the input pulse, while response time for the high-to-low-level output is measured from the trailing edge of the input pulse. Response time measurement at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 7, so that the circuit is just at the transition point. A low signal, for example 105-mV or 5-mV overdrive, causes the output to change state. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 PARAMETER MEASUREMENT INFORMATION VDD Pulse Generator 1 F 50 + 1V DUT 10 10-Turn Potentiometer - 1 k CL (see Note A) 0.1 F -1V TEST CIRCUIT Overdrive Overdrive Input Input 100 mV 100 mV 90% Low-to-High Level Output 90% High-to-Low Level Output 50% 10% 50% 10% tf tr tPLH tPHL VOLTAGE WAVEFORMS NOTE A: CL includes probe and jig capacitance. Figure 7. Response, Rise, and Fall Times Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Input offset voltage Distribution 8 IIB Input bias current vs Free-air temperature 9 CMRR Common-mode rejection ratio vs Free-air temperature 10 kSVR Supply-voltage rejection ratio vs Free-air temperature 11 VOH High level output current High-level vs Free-air Free air temperature vs High-level output current 12 13 VOL Low level output voltage Low-level vs Low-level Low level output current vs Free-air temperature 14 15 tt Output transition time vs Load capacitance 16 Supply current response to an output voltage transition 17 Low-to-high-level output response for various input overdrives 18 High-to-low-level output response for various input overdrives 19 tPLH Low-to-high-level output response time vs Supply voltage 20 tPHL High-to-low-level output response time vs Supply voltage 21 Supply current vs Frequency vs Supply voltage vs Free-air temperature 22 23 24 IDD INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE DISTRIBUTION OF INPUT OFFSET VOLTAGE 180 Number of Units 160 140 120 100 80 60 40 20 0 -5 E E E CC E CC E CC E CC E CC CC E CC CC E CC CC C E E E CCCC C E E C EE E CC CC C E E C EE CEE EE C EEEE CCCC CC CEECCE EEE C 10 VDD = 5 V VIC = 2.5 V TA = 25 C 698 Units Tested From 4 Wafer Lots -4 -3 -2 -1 0 1 2 3 4 VDD = 5 V VIC = 2.5 V IIB - Input Bias Current - nA 200 1 0.1 0.01 0.001 5 25 VIO - Input Offset Voltage - mV 14 75 100 Figure 9 Figure 8 50 TA - Free-Air Temperature - C Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 125 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE REJECTION RATIO vs FREE-AIR TEMPERATURE 88 90 k SVR - Supply Voltage Rejection Ratio - dB CMRR - Common-Mode Rejection Ratio - dB 90 VDD = 5 V 86 84 82 80 78 76 74 72 70 -75 -50 -25 0 25 50 75 100 88 VDD = 5 V to 10 V 86 84 82 80 78 76 74 72 70 -75 125 -50 TA - Free-Air Temperature - C -25 Figure 10 75 100 125 VDD VDD = 5 V IOH = - 4 mA VOH - High-Input Level Output Voltage -V VOH - High-Level Outout Voltage - V 50 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 5 4.9 4.85 4.8 4.75 4.7 4.65 4.6 4.55 4.5 -75 -50 -0.25 VDD = 16 V -0.5 -0.75 10 V -1 5V -1.25 4V -1.5 -1.75 3V TA = 25C -2 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C 0 -2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 IOH - High-Level Output Current - mA Figure 12 25 Figure 11 HIGH-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 4.95 0 TA - Free-Air Temperature - C Figure 13 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 400 TA = 25C 3V VOL - Low-Level Output Voltage - mV VOL - Low-Level Output Voltage - V 1.5 4V 1.25 1 5V 0.75 10 V 0.5 0.25 VDD = 16 V 0 0 2 4 6 8 10 12 14 16 18 VDD = 5 V IOL = 4 mA 350 300 250 200 150 100 50 0 -75 20 -50 -25 50 75 100 Figure 15 Figure 14 OUTPUT TRANSITION TIME vs LOAD CAPACITANCE SUPPLY CURRENT RESPONSE TO AN OUTPUT VOLTAGE TRANSITION 250 VDD = 5 V CL = 50 pF f = 10 kHz VDD = 5 V TA = 25C 10 IDD - Supply Current - mA 200 Rise Time 175 150 125 Fall Time 5 0 100 75 Output Voltage - V tt - Transition Time - ns 25 TA - Free-Air Temperature - C IOL - Low-Level Output Current - mA 225 0 50 25 5 0 0 0 200 400 600 800 1000 t - Time CL - Load Capacitance - pF Figure 17 Figure 16 16 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 125 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS HIGH-TO-LOW-LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES LOW-TO-HIGH-LEVEL OUTPUT RESPONSE FOR VARIOUS INPUT OVERDRIVES 5 5 VO - Output Voltage - V 40 mV 20 mV 10 mV 5 mV 2 mV 0 0 100 100 Differential Input Voltage - mV Differential Input Voltage - mV VO - Output Voltage - V 40 mV 20 mV 10 mV 5 mV 2 mV VDD = 5 V TA = 25 C CL = 50 pF 0 0 1 2 3 4 VDD = 5 V TA = 25 C CL = 50 pF 0 0 5 1 2 3 4 5 tPHL - High-to-Low-Level Output Response Time - s tPLH - Low-to-High-Level Output Response Time - s Figure 19 Figure 18 LOW-TO-HIGH-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE HIGH-TO-LOW-LEVEL OUTPUT RESPONSE TIME vs SUPPLY VOLTAGE 6 6 CL = 50 pF TA = 25C 5 CL = 50 pF TA = 25C 5 t PHL - High-to-Low-Level Output Response - s t PLH - Low-to-High-Level Output Response - s Overdrive = 2 mV 4 5 mV 3 10 mV 2 20 mV 1 Overdrive = 2 mV 4 3 5 mV 2 10 mV 20 mV 1 40 mV 40 mV 0 0 2 4 6 8 10 12 14 16 0 0 2 VDD - Supply Voltage - V 4 6 8 10 12 14 16 VDD - Supply Voltage - V Figure 20 Figure 21 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT (PER COMPARATOR) vs FREQUENCY SUPPLY CURRENT vs SUPPLY VOLTAGE 80 TA = 25C CL = 50 pF TA = - 55C Outputs Low No Loads 70 TA = - 40C VDD = 16 V VDD - Supply Current - A VDD - Average Supply Current - A 10000 1000 10 V 5V 100 4V 60 TA = 25C 50 40 30 TA = 125C 20 TA = 85C 10 3V 10 0.01 0.1 1 10 0 100 0 2 4 6 8 10 12 14 VDD - Supply Voltage - V f - Frequency - kHz Figure 22 Figure 23 SUPPLY CURRENT vs FREE-AIR TEMPERATURE 30 VDD = 5 V No Load IDD - Supply Current -A 25 20 Outputs Low 15 10 Outputs High 5 0 -75 -50 -25 0 25 50 75 100 125 TA - Free-Air Temperature - C Figure 24 18 Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 16 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 APPLICATION INFORMATION The inputs should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic discharge (ESD) protection structure. If either input exceeds this range, the device is not damaged as long as the input is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within the common-mode range. For example, at 25C with VDD = 5 V, both inputs must remain between - 0.2 V and 4 V to ensure proper device operation. To ensure reliable operation, the supply should be decoupled with a capacitor (0.1 F) that is positioned as close to the device as possible. Output and supply current limitations should be watched carefully since the TLC3704 does not provide current protection. For example, each output can source or sink a maximum of 20 mA; however, the total current to ground can only be an absolute maximum of 60 mA. This prohibits sinking 20 mA from each of the four outputs simultaneously since the total current to ground would be 80 mA. The TLC3704 has internal ESD-protection circuits that prevents functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices as exposure to ESD may result in the degradation of the device parametric performance. Table of Applications FIGURE Pulse-width-modulated motor speed controller 25 Enhanced supply supervisor 26 Two-phase nonoverlapping clock generator 27 Micropower switching regulator 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 APPLICATION INFORMATION 12 V 5V EN 1/2 TLC3704 See Note A + 100 k + 10 k 5V SN75603 Half-H Driver DIR - 10 k C1 0.01 F (see Note B) Motor - 1/2 TLC3704 12 V DIR 10 k 5V 10 k Motor Speed Control Potentiometer EN 5V Direction Control S1 SPDT NOTES: A. The recommended minimum capacitance is 10 F to eliminate common ground switching noise. B. Adjust C1 for change in oscillator frequency Figure 25. Pulse-Width-Modulated Motor Speed Controller 20 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN75604 Half-H Driver TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 APPLICATION INFORMATION 5V 12 V 12-V Sense 3.3 k VCC SENSE 10 k 1/2 TLC3704 + RESIN 1 k 5V TL7705A RESET To P Reset - REF CT GND 2.5 V 1 F CT (see Note B) 1/2 TLC3704 + V(UNREG) (see Note A) To P Interrupt Early Power Fail R1 - Monitors 5 VDC Rail Monitors 12 VDC Rail Early Power Fail Warning R2 (R1 +R2) R2 B. The value of CT determines the time delay of reset. NOTES: A. V (UNREG) + 2.5 Figure 26. Enhanced Supply Supervisor POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 APPLICATION INFORMATION 12 V R1 100 k (see Note B) 12 V 12 V - - 1/2 TLC3704 R2 5 k (see Note C) 100 k OUT1 + + - 22 k 100 k C1 0.01 F (see Note A) 100 k 1/2 TLC3704 1/2 TLC3704 OUT2 + R3 100 k (see Note B) 12 V OUT1 OUT2 NOTES: A. Adjust C1 for a change in oscillator frequency where: 1/f = 1.85(100 k)C1 B. Adjust R1 and R3 to change duty cycle C. Adjust R2 to change deadtime Figure 27. Two-Phase Nonoverlapping Clock Generator 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC3704, TLC3704M QUAD MICROPOWER LinCMOS VOLTAGE COMPARATORS SLCS117C - NOVEMBER 1986 - REVISED NOVEMBER 2009 APPLICATION INFORMATION V + 6 V to 16 V I I + 0.01 mA to 0.25 mA L (R1 ) R2) V + 2.5 O R2 1/2 TLC3704 + 100 k VI - 100 k VI SK9504 (see Note C) G S VI 1/2 TLC3704 + - 100 k D + C1 180 F (see Note A) 47 F Tantalum IN5818 100 k R1 R=6 L = 1 mH (see Note D) VO 100 k TLC271 (see Note B) VI 470 F RL + R2 100 k - C2 100 pF 100 k 270 k VI LM385 2.5 V NOTES: A. Adjust C1 for a change in oscillator frequency B. TLC271 - Tie pin 8 to pin 7 for low bias operation C. SK9504 - VDS = 40 V IDS = 1 Awill D. To achieve microampere current drive, the inductance of the circuit must be increased. Figure 28. Micropower Switching Regulator POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) 5962-9096901M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629096901M2A TLC3704 MFKB 5962-9096901MCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9096901MC A TLC3704MJB TLC3704CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3704C TLC3704CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3704C TLC3704CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3704C TLC3704CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3704C TLC3704CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLC3704CN TLC3704CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLC3704CN TLC3704CNSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3704 TLC3704CNSRG4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLC3704 TLC3704CPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 P3704 TLC3704CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 P3704 TLC3704CPWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI 0 to 70 TLC3704CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 P3704 TLC3704CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 P3704 TLC3704ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 Addendum-Page 1 TLC3704I Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Orderable Device Status (1) (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) TLC3704IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLC3704I TLC3704IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLC3704I TLC3704IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLC3704I TLC3704IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLC3704IN TLC3704INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLC3704IN TLC3704IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 P3704I TLC3704IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 P3704I TLC3704IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 P3704I TLC3704IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 P3704I TLC3704MD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 TLC3704MD TLC3704MDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 PJ3704M TLC3704MDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 TLC3704MD TLC3704MDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 PJ3704M TLC3704MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 59629096901M2A TLC3704 MFKB TLC3704MJ ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 TLC3704MJ TLC3704MJB ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-9096901MC A TLC3704MJB The marketing status values are defined as follows: Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC3704, TLC3704M : * Catalog: TLC3704 * Automotive: TLC3704-Q1, TLC3704-Q1 * Military: TLC3704M NOTE: Qualified Version Definitions: Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Military - QML certified for Military and Defense Applications Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLC3704CDR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC3704CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 TLC3704CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLC3704IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC3704IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLC3704MDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLC3704MDRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLC3704CDR SOIC D 14 2500 367.0 367.0 38.0 TLC3704CNSR SO NS 14 2000 367.0 367.0 38.0 TLC3704CPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLC3704IDR SOIC D 14 2500 367.0 367.0 38.0 TLC3704IPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLC3704MDR SOIC D 14 2500 367.0 367.0 38.0 TLC3704MDRG4 SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as "components") are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI's terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers' products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers' products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI's goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or "enhanced plastic" are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP(R) Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright (c) 2013, Texas Instruments Incorporated