©2004 Fairchild Semiconductor Corporation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
HUF75344G3, HUF75344P3, HUF75344S3S
75A, 55V, 0.008 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Channel power MOSFETs
are manufactured using the
inno vat ive UltraFET ® process . This
advanced process technology
achieves the lowest possible on-resistance per silicon area,
resulting in outstandi ng p erformance. This device is c apa ble
of withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficie nc y is important, such as s wi tch in g regul ators,
switching converters, motor drivers, relay drivers, low-
voltage bus switches, and power management in portabl e
and battery-operated products.
Formerly developmental type TA75344.
Features
• 75A, 55V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Models
- Thermal Impedance PSPICE and SABER Models
Available on the web at: www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
Product r e liability informa tion can be found at http: //www.fairchilds e m i.com/products/discr e te/reliability /index .html
For severe environments, see our Automotive HUFA series.
All Fairchi ld semiconductor pr oduct s are manufactured, assembled and tested under IS O9000 and QS9000 quality systems certifi cation.
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75344G3 TO-247 75344G
HUF75344P3 TO-220AB 75344P
HUF75344S3S TO-263AB 75344S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB variant in tape and reel, e.g., HUF75344S3ST.
D
G
S
JEDEC STYLE T O-247 JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(TAB)
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data Sheet December 2004
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . VDSS 55 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR 55 V
Gate to Sou rc e Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Dr a i n Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 75
Figure 4 A
Pulsed Avalan che Ra tin g. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figure 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
1.90 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC
Maximum Tem perature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . .TL
P ackage Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: St resses above those l isted in “A bsolute Maximu m Rating s” may cause per manent d amage to t he device. This is a stress on ly rating and operation o f the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V
Zero Gate Voltage Drain Current IDSS VDS = 50V, VGS = 0V - - 1 µA
VDS = 45V, VGS = 0V, TC = 150oC--250µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
ON STAT E SPECIFICAT ION S
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (F igure 10) 2 - 4 V
Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figure 9) - 6.5 8.0 mΩ
THERMAL SP EC I FICAT I ONS
Thermal Resistance Junction to Case RθJC (Figure 3) - - 0.52 oC/W
Thermal Resistance Junction to Ambient RθJA TO-247 - - 30 oC/W
TO-220, TO-263 - - 62 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 30V, ID ≅ 75A,
RL = 0.4Ω, VGS = 10V,
RGS = 3.0Ω
--187ns
Turn-On Delay Time td(ON) -13- ns
Rise Time tr- 125 - ns
Turn-Off Delay Time td(OFF) -46- ns
Fall Ti me tf-57- ns
Turn-Off Time tOFF --147ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 20V VDD = 30V,
ID ≅ 75A,
RL = 0.4Ω
Ig(REF) = 1. 0mA
(Figure 13)
- 175 210 nC
Gate Charge at 10V Qg(10) VGS = 0V to 10V - 90 108 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 5.9 7. 0 nC
Gate to Source Gate Charge Qgs -14-nC
Reverse Transfer Capacitance Qgd -39-nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1M H z
(Figure 12)
- 3200 - pF
Output Capacitance COSS - 1170 - pF
Reverse Transfer Capacitance CRSS - 310 - pF
HUF753 44 G3, H UF753 44P3, HUF75344S3S
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
Sour ce to Drain Diode Specificatio ns
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNI TS
Source to Drain Diode Voltage VSD ISD = 75A - - 1.25 V
Reverse Recovery Time trr ISD = 75A, dISD/ dt = 100A/µs - - 105 ns
Reverse Recovered Charge QRR ISD = 75A, dISD/dt = 100A/µs - - 210 nC
Typical Performance Curves
FIGURE 1. NORMALIZED PO WER DISSIPA TI ON vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 175
I
D
, DRAIN CURRENT (A)
T
C
, CASE TEMPERAT URE (
o
C)
20
40
60
80
50 75 100 125 150 175
025
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
10-4 10-3 10-2 10-1 100101
10-5
0.1
1
2
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
HUF753 44 G3, H UF753 44P3, HUF75344S3S
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Fa irchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS
Typical Performance Curves (Continued)
10
1
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
50
100
2000 T
C
= 25
o
C
I = I
25
175 - T
C
150
FOR TEMPERATURES
ABO VE 25
o
C DERATE PEAK
CURRENT AS FOLLOW S:
V
GS
= 10V
I
DM
, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1000
V
GS
= 20V
10
100
1000
10 100
11200
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
T
C
= 25
o
C
100
µ
s
10ms
1ms
V
DSS(MAX)
= 55V
LIMITED BY r
DS(ON)
AREA MAY BE
OPERATION IN THIS
tAV = (L)( IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
1100.01
1000
10
IAS, AVALANCHE CURRENT (A)
tAV, TIME IN AVALANCHE (ms)
0.1
100
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
30
60
90
120
150
01234
VGS = 10V
PULSE DURATION = 80µs
TC = 25oC
VGS = 5V
VGS = 6V
VGS = 20V
VGS = 7V
DUTY CYCLE = 0.5% MAX
0 3 4.5 6 7.51.5
0
30
60
90
120
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
150
175
o
C
-55oC
25oC
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
VDD = 15V
HUF753 44 G3, H UF753 44P3, HUF75344S3S
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
FIGURE 9. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GATE THRESHOLD VOLTA GE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN T O SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. CAPA CITANCE vs DRAIN T O SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves (Continued)
0.5
1.0
1.5
2.0
2.5
-80 -40 040 80 120 160
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
200
PULSE DURATION = 80µs
VGS = 10V, ID = 75A
DUTY CYCLE = 0.5% MAX VGS = VDS, ID = 250µA
-80 -40 0 40 80 120 160
0.4
0.6
0.8
1.0
1.2
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
200
ID = 250µA
1.2
1.1
0.9-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
200
1.0
3000
00 20304050
C, CAPACITANCE (pF)
4500
VDS, DRAIN T O SOURCE VOLTAGE (V)
1500
6010
CISS
CRSS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
0
2
4
6
8
10
0 255075100
VDD = 30V
ID = 75A
ID = 55A
ID = 35A
ID = 20A
WAVEFORMS IN
DESCENDING ORDER:
HUF753 44 G3, H UF753 44P3, HUF75344S3S
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF753 44 G3, H UF753 44P3, HUF75344S3S
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
PSPICE Electrical Model
.SUBCKT HUF75337 2 1 3 ; rev 3 Feb 1999
CA 12 8 4.9e-9
CB 15 14 4.75e-9
CIN 6 8 2.85e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 59.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEM P 20 6 18 22 1
IT 8 17 1
LDRA IN 2 5 1e - 9
LGATE 1 9 2.6e-9
LSOURCE 3 7 1.1e-9
KGATE LSOURCE LGATE 0.008 5
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.94e-3
RGATE 9 20 0.36
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AM OD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VA LUE={(V(5 ,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*400),3))}
.MODEL DBODYMOD D (IS = 2.95e-12 RS = 2.6e-3 TRS1 = 1.05e -3 TRS2 = 5.0e-7 CJO = 5.19e-9 TT = 5.9e-8 M = 0.55)
.MODEL DBREAKMOD D (RS = 1.65e-1 IKF = 30 TRS1 = 1.15e-4 TRS2 = 2.27e-6)
.MODEL DPLCAPMOD D (CJO = 5.40e-9 IS = 1e-30 N=1 M = 0. 88 )
.MODEL MMEDMOD NMOS (VTO = 3.29 KP = 5.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.36)
.MODEL MSTROMOD NMOS (VTO = 3.83 KP = 123 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.90 KP =0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL RBREAKMOD RE S (TC1 = 1.1 5e-3 TC2 = 2.0e-7)
.MODEL RDRAINMOD RES (TC1 = 1. 37e-2 TC2 = 3.85e-5)
.MODEL RSLCMOD RES (TC1 = 1.45e- 4 T C 2 = 2.11e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -3.7e-3 TC2 = -1.6e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.4e-3 TC2 = 7e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.9 VOFF= -3.9)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.9 VOFF= -6.9)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.99 VOFF= 2.39)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.39 VOFF= -2.99)
.ENDS
NOTE: For fur th er discussion of the PSPICE m odel, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Gl oba l
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF753 44 G3, H UF753 44P3, HUF75344S3S
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
SABER Electrical Model
REV 3 February 1999
template huf75344 n2 , n1, n3
electrical n2, n1, n3
{
var i iscl
d..model dbodymod = (is = 2.95e-12, cjo = 5.19e-9, tt = 5.90e-8, m = 0.55)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 5.4 0e-9, is = 1e-30, n = 1, m = 0. 88)
m..model mmedmod = (t ype=_n, vto = 3.29, kp = 5.5, is = 1e-30, tox = 1)
m..model mstr ongmod = (type=_n, vto = 3.83, kp = 123, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.90, kp = 0.04, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.9, voff = -3.9)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.9, voff = -6.9)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.99, voff = 2.39)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.39, voff = -2.99)
c.ca n12 n8 = 4.9e -9
c.cb n15 n14 = 4.75e-9
c.ci n n6 n8 = 2.85e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplc ap n10 n5 = model=dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.6e-9
l.lsou rce n3 n7 = 1.1e-9
k.kl i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.00 85
m.mmed n16 n6 n8 n8 = mod el=mmedmod, l = 1u, w = 1u
m.mstr ong n16 n6 n8 n8 = model=ms trongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model=mweak mod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = 2e-7
res.rdbody n71 n5 = 2.6e -3, tc1 = 1.05e-3, tc2 = 5e-7
res.rdbreak n72 n5 = 1.65e-1, tc1 = 1.15e-4, tc2 = 2.27e-6
res.rdrain n50 n16 = 1.94e- 3, tc1 = 1.37e-2, tc 2 = 3.85e-5
res.rgate n9 n20 = 0.36
res.rldrain n2 n5 = 10
res.r l gate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 1.45e-4, tc2 = 2. 11e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.5e -3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -2.4e- 3, tc2 = 7e-7
res.rvthres n22 n8 = 1, tc 1 = -3.7e-3, tc2 = -1.6e-5
spe.e b reak n11 n7 n17 n18 = 59.7
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc = 1
equa tions {
i (n51- >n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e- 9+abs(v (n5,n51))))*((abs(v (n5,n51)*1e6/400))** 3))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF753 44 G3, H UF753 44P3, HUF75344S3S
©2004 Fairchild Semiconductor Corpor ation HUF75344G3, HUF75344P3, HUF75344S3S Rev. B2
SPICE Thermal Model
REV 5 February 1999
HUF75344
CTHERM1 th 6 5.0e-3
CTHERM2 6 5 1.0e-2
CTHERM3 5 4 1.3e-2
CTHERM4 4 3 1.5e-2
CTHERM5 3 2 2.2e-2
CTHERM6 2 tl 8.5e-2
RTHERM1 th 6 6.0e-4
RTHERM2 6 5 3.5e-3
RTHERM3 5 4 2.5e-2
RTHERM4 4 3 4.8e-2
RTHERM5 3 2 1.6e-1
RTHERM6 2 tl 1.8e-1
SABER Thermal Model
SABER thermal mode l HUF75344
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-3
ctherm.ctherm2 6 5 = 1.0e-2
ctherm.ctherm3 5 4 = 1.3e-2
ctherm.ctherm4 4 3 = 1.5e-2
ctherm.ctherm5 3 2 = 2.2e-2
ctherm.ctherm 6 2 tl = 5.5e-2
rtherm.rtherm1 th 6 = 6.0e-4
rtherm.rtherm2 6 5 = 3.5e-3
rtherm.rtherm3 5 4 = 2.5e-2
rtherm.rtherm4 4 3 = 4.8e-2
rtherm.rtherm5 3 2 = 1.6e-1
rtherm.rtherm6 2 tl = 1.8e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF753 44 G3, H UF753 44P3, HUF75344S3S
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