ANALOG DEVICES Low Cost, Laser Trimmed, Precision IC Op Amp ADS17 FEATURES Low Input Bias Current: 1nA max (AD517L) Low Input Offset Current: 0.25nA max (AD517L) Low Vos: 50uV max (AD517L), 150V max (AD517J) Low Vos Drift: 1.3uV/C (AD517L) Internal Compensation MiL-Standard Parts Available 8-Pin TO-99 Hermetic Metal Can Available in Chip Form PRODUCT DESCRIPTION The AD517 is a high accuracy monolithic op amp featuring ex- tremely low offset voltages and input currents. Analog Devices thermally-balanced layout and superior IC processing combine to produce a truly precision device at low cost. The AD517 is laser trimmed at the wafer level (LWT) to pro- duce offset voltages less than 50uV and offset voltage drifts less than 1.3#V/ C unnulled. Superbeta input transistors pro- vide extremely low input bias currents of nA max and offset currents as low as 0.25nA max. While these figures are com- parable to presently available BIFET amplifiers at room tem- perature, the AD517 input currents decrease, rather than increase, at elevated temperatures. Open-loop gain in many IC amplifiers is degraded under loaded conditions due to thermal gradients on the chip. However, the AD517 layout is balanced along a thermal axis, maintaining open-loop gain in excess of 1,000,000 for a wide range of load resistances. The input stage of the AD517 is fully protected, allowing dif- ferential input voltages of up to +Vg without degradation of gain or bias current due to reverse breakdown. The output stage is short-circuit protected and is capable of driving a load capacitance up to 1000pF. The AD517 is well suited to applications requiring high pre- cision and excellent long-term stability at low cost, such as stable references, followers, bridge instruments and analog computation circuits. REV. A PIN CONFIGURATION OFFSET NULL 8 1 7 +Vs5 -IN 2 6 OUTPUT +IN 3 5 NC 4 a Vs TOP VIEW The circuit is packaged in a hermetically sealed TO-99 metal can, and is available in three performance versions (J, K, and L) specified over the commercial 0 to +70C range; and one version (AD517S) specified over the extended temperature range, -55C to +125C. PRODUCT HIGHLIGHTS 1. Offset voltage is 100% tested and guaranteed on all models. 2. The AD517 exhibits extremely low input bias currents without sacrificing CMRR (over 100dB) or offset voltage stability. 3. The AD517 inputs are protected (to tVg), preventing offset voltage and bias current degradation due to reverse break- down of the input transistors. 4. Internal compensation is provided, eliminating the need for additional components (often required by high accuracy IC op amps). 5. The AD517 can directly replace 725, 108, and AD510 am- plifiers. In addition, it can replace 741-type amplifiers if the offset-nulling potentiometer is removed. 6. Thermally-balanced layout insures high open-loop gain inde- pendent of thermal gradients induced by output loading, offset nulling, and power supply variations. 7. Chips are available. OPERATIONAL AMPLIFIERS 2-51AD517 SPECIFICATIONS (a +2 anv, = = 15V de) ADS17J AD517K ADSI7L ADS517S Model . Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units OPEN LOOP GAIN Vo = *10V,R, = 2k0 10 10* 10 10 vA Tenia t0 Trax, Re = 2k. 500,000 500,000 500,000 250,000 VN OUTPUT CHARACTERISTICS Voltage @ Rr = 2k2, Trin to Tux +10 +10 +10 +10 v Load Capacitance 1000 1000 1000 1000 pF Output Current 10 10 10 10 mA Short Circuit Current 25 2s 25 2s mA FREQUENCY RESPONSE Unity Gain Small Signal 250 250 250 250 kHz Full Power Response 1.5 1.5 15 1.5 kHz Slew Rate, Unity Gain 0.10 0.10 0.10 0.10 Vips INPUT OFFSET VOLTAGE Initial Offset 150 75 50 vi) pv Input Offset vs. Temp. 3.0 18 13 18 aVPC Input Offset vs. Supply 25 10 10 10 py Train t0 Tmax 40 15 15 20 pvv INPUT BIAS CURRENT Initial 5 2 1.0 2.0 nA Train ( Tmax 8 3.5 LS 10 nA vs. Temp, Trin (0 Tmax +20 +10 #4 +10 parc INPUT OFFSET CURRENT a Initial 1.0 0.75 0.25 2.0 pA Tin tO Tmax 1.5 1.25 0.4 10 nA INPUT IMPEDANCE Differential 15|1.5 2041.5 2041.5 2041.5 MQ \pF Common Mode 2.0x 10" 2.0 x 10" 2.0 x 10" 2.0x 10" a INPUT VOLTAGE RANGE Differential +Vs *Vs +Vs =Vs Vv Common Mode Rejection 110 10 110 4B Common Mode Rejection Tinin tO Tmax . 110 100 100 dB INPUT NOISE Voltage, 0.1Hz to 1OHz 2 2 2 2 pVpp f=10Hz 35 35 35 35 aV/VHz f= 100H2 25 25 25 25 aV/VHz f= kHz 20 20 20 20 aV/VHz Current, f= 10kHz 0.05 0.05 0.05 0.05 pA/VHz f=100Hz 0.03 0.03 0.03 0.03 pAVHz f=1kHz 0.03 0.03 0.03 0.03 pA/VHz POWER SUPPLY Rated Performance +15 +15 +15 +15 v Operating *5 +18 +5 +18 +5 +18 +5 +18 Vv Quiescent Current 4 3 3 3 mA TEMPERATURE RANGE Operating, Rated Performance 0 +70 0 +70 0 +70 ~55 +125 C Storage -65 +150 65 +150 -65 +150 -65 +150 cc PACKAGE OPTION! TO-99 Style (H-08B) ADS17JH ADS17KH ADSI7LH ADSI7SH Jand S Grade Chips Also Available NOTES "For outline information see Package Information section. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. Al! min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. 2-52 OPERATIONAL AMPLIFIERS REV. AADS17 CHIP DIMENSIONS AND BONDING DIAGRAM Contact factory for latest dimensions. Dimensions shown in inches and (mm). 0.093 (2.362) __> NULL NULL THE AD517 IS AVAILABLE IN LASER-TRIMMED CHIP FORM. REV. A OPERATIONAL AMPLIFIERS 2-53AD517Typical Performance Curves 10M 100 2 So GAIN 2 3 1 w Qo > E z 9 q = Zz < o 01 1 10 100 Ik 10k 100k 1M tk 10k 100k FREQUENCY Hz LOAD RESISTANCE ohms Smalt-Signal Gain vs. Frequency Open-Loop Gain vs. Load Resistance ty nA p+ +4 NV IW | | OFFSET VOLTAGE uV /F \ 0 25 70 125 TEMPERATURE ~ C 7B -60 -2s 25 50 % 100 128 TEMPERATURE C Input Bias Current vs. Temperature Untrimmed Offset Voltage vs. Temperature CMRR - dB PSRR dB 0.1 1 10 100 Tk 10k FREQUENCY Hz FREQUENCY Hz CMRAR vs. Frequency PSRR vs. Frequency 2-54 OPERATIONAL AMPLIFIERS REV. AADS17 W GUTPUT VOLTAGE Volts rms =~ Nw ea aon @ Oo 2 3 FREQUENCY kHz Maximum Undistorted Output vs. Frequency (Distortion < 1%) NON-INVERTING INPUT CURRENT mA 1000 5 0 4% +100 415 +200 +28, DIFFERENTIAL INPUT VOLTAGE Input Current vs. Differential Input Voltage nvi/Hz 10 100 k 10k FREQUENCY Hz Total Input Noise Voltage vs. Frequency REV. A yw - IN3HHND LNdNI ONILY3ANI OUTPUT SWING Volts NEGATIVE SWING POSITIVE SWING 0.1 1 10 LOAD RESISTOR TO GROUND k&t Output Voltage vs. Load Resistance Vos. HV TIME AFTER POWER SUPPLY TURN-ON Minutes Warm-Up Offset Voltage Drift VOLTAGE NOISE 0.1 10Hz E, = 500nV/DIV RTt Low Frequency Voltage Noise (0.1 to 10Hz)} OPERATIONAL AMPLIFIERS 2-55AD517 Applications NULLING THE AD517 The internally-trimmed offset voltage of the AD517 will be low enough for most circuits without further nulling. However, in high precision applications, the AD517 may be nulled using either of the following methods: Figure 1A shows a simple circuit using a 10k{2, ten-turn poten- tiometer. This circuit allows nulling to within several microvolts. The circuit of Figure 1B is recommended in applications where nulling to within 1V is desired. This circuit has the advantage that potentiometer instability effects are reduced by a factor of ten. Values of Ry and R2 are calculated as follows: 1. Null the offset to zero using a standard 10k pot, as shown in Figure 1A. 2. Measure pot halves R, and R. 3. Calculate: _ Ryx 50kQ, 1. -soKa=R, 2 = Rz x 50k2 R 4 ' 50k2R, 4. Replace the pot with R; and Rg using the closest value 1% metal film resistors. 5. Use a 100k, ten-turn pot for R, to complete the nulling. @) ~@ (8) 10k 10 TURNS A. Simple 7 RV R2 R, B. High Precision Figure 1. Nulling Circuits 2-56 OPERATIONAL AMPLIFIERS AN INSTRUMENT INPUT AMPLIFIER USING THE ADS517L The circuit shown in Figure 2 represents a typical input stage for laboratory instruments and panel meters. The amplifier is non-inverting and offers selectable gains from 1 to 1000 in decade steps. Input impedance of this amplifier is 10 megohms, determined by resistor R,. The offset nulling network comprised of R3, Rg, and Rg is the same one described earlier. If a less precise adjustment can be tolerated, a single 10k potentiometer can be substituted for R3, Ry and Rs. +15V SR3 | RAZ R2 7 j Wk 1% 3 wn INPUT + 1 R5 RI 10M. 8 1% AD517 5 9 2 - R6 10k 1% R7 2 R10 ~1V 1k 1% $ 90k 0.02% RB t R11 oa. 9,09k 1% ; 9k 0.02% RO R12 \ 10k 1% 2 9002 0.02% > $ R13 uu 0.02% Figure 2. Stable Instrument Input Amplifier Gain switching is accomplished in the feedback network. The divider consisting of Ryg, Ryz, Ry and Ry3 determines the gain by dividing the output and returning it to the inverting input of the amplifier. The ratio tolerances of these resistors uniquely determine the gain of the amplifier. The impedance seen by the inverting input is held constant at 10k ohms by Rg, Rz Rg or Rg depending on the gain selected. Since input bias currents flow through equal resistances, the offset voltages produced will cancel each other. The input offset currents will produce an insignificant offset voltage on the order of 1 micro- volt. If this offset is nulled out at the highest gain selected, it will be nulled on all ranges. The AD517 offers excellent temperature stability in this cir- cuit. Once the offset has been zeroed, the error produced by offset current drift will remain quite low due to the extremely low offset current drift of the AD517. A FET-input op amp would not work well in this application, since the input offset currents would double for each 10C increase in temperature, soon exceeding the input offset currents of the AD517. REV. A