®
Integrated Circuits Group
LH28F320BFN-PTTLZJ
Flash Memory
32M (2M × 16)
(Model No.: LHF32FDH)
Spec No.: FM024004
Issue Date: April 1, 2002
PRELIMINARY PRODUCT SPECIFICATIONS
LHF32FDH
• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,
full or in part, of this material is prohibited without the express written permission of the company.
• When using the products covered herein, please observe the conditions written herein and the precautions outlined in
the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly
adhere to these conditions and precautions.
(1) The products covered herein are designed and manufactured for the following application areas. When using the
products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure
to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph
(3).
• Office electronics
• Instrumentation and measuring equipment
• Machine tools
• Audiovisual equipment
• Home appliance
• Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment which demands high
reliability, should first contact a sales representative of the company and then accept responsibility for
incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring
reliability and safety of the equipment and the overall system.
• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment
• Mainframe computers
• Traffic control systems
• Gas leak detectors and automatic cutoff devices
• Rescue and security equipment
• Other safety devices and safety equipment, etc.
(3) Do not use the products covered herein for the following equipment which demands extremely high performance
in terms of functionality, reliability, or accuracy.
• Aerospace equipment
• Communications equipment for trunk lines
• Control equipment for the nuclear power industry
• Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales
representative of the company.
• Please direct all queries regarding the products covered herein to a sales representative of the company.
Rev. 2.41
sharp
LHF32FDH 1
PAGE
44-Lead SOP Pinout ................................................... 3
Pin Descriptions.......................................................... 4
Memory Map .............................................................. 5
Identifier Codes and OTP Address
for Read Operation ............................................. 6
OTP Block Address Map for OTP Program............... 7
Bus Operation............................................................. 8
Command Definitions ................................................ 9
Functions of Block Lock and Block Lock-Down...... 11
Block Locking State Transitions upon
Command Write................................................. 11
Status Register Definition......................................... 12
Extended Status Register Definition ........................ 13
PAGE
1 Electrical Specifications......................................... 14
1.1 Absolute Maximum Ratings ........................... 14
1.2 Operating Conditions ...................................... 14
1.2.1 Capacitance .............................................. 15
1.2.2 AC Input/Output Test Conditions ............ 15
1.2.3 DC Characteristics ................................... 16
1.2.4 AC Characteristics
- Read-Only Operations......................... 17
1.2.5 AC Characteristics
- Write Operations ................................. 20
1.2.6 Reset Operations ...................................... 22
1.2.7 Block Erase, Full Chip Erase,
(Page Buffer) Program and
OTP Program Performance.................... 23
2 Related Document Information.............................. 24
CONTENTS
Rev. 2.41
sharp
LHF32FDH 2
LH28F320BFN-PTTLZJ
32Mbit (2Mbit×16)
Page Mode Flash MEMORY
32M density with 16Bit I/O Interface
High Performance Reads
• 70/25ns 8-Word Page Mode
Low Power Operation
• 2.7V Read and Write Operations
• Automatic Power Savings Mode Reduces ICCR
in Static Mode
Enhanced Code + Data Storage
• 5µs Typical Erase/Program Suspends
OTP (One Time Program) Block
• 4-Word Factory-Programmed Area
• 4-Word User-Programmable Area
High Performance Program with Page Buffer
• 16-Word Page Buffer
Operating Temperature 0°C to +70°C
Flexible Blocking Architecture
• Eight 4K-word Parameter Blocks
• Sixty-three 32K-word Main Blocks
• Top Parameter Location
CMOS Process (P-type silicon substrate)
Enhanced Data Protection Features
• Individual Block Lock and Block Lock-Down with
Zero-Latency
• All blocks are locked at power-up or device reset.
• Block Erase, Full Chip Erase, (Page Buffer) Word
Program Lockout during Power Transitions
Automated Erase/Program Algorithms
• 3.0V Low-Power 11µs/Word (Typ.)
Programming
Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
44-Lead SOP
ETOXTM* Flash Technology
Not designed or rated as radiation hardened
The product, which is Page Mode Flash memory, is a low power, high density, low cost, nonvolatile read/write storage
solution for a wide range of applications. The product can operate at VCC=2.7V-3.6V. Its low voltage operation capability
greatly extends battery life for portable applications.
The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus
eliminating time consuming wait states.
The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.
* ETOX is a trademark of Intel Corporation.
Rev. 2.41
sharp
LHF32FDH 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44-LEAD SOP
STANDARD PINOUT
13.2mm x 28.2mm
TOP VIEW
A
19
A
18
A
17
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE#
GND
OE#
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
RST#
WE#
A
20
NC
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
DQ
15
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
Figure 1. 44-Lead SOP Pinout
Rev. 2.41
sharp
LHF32FDH 4
Table 1. Pin Descriptions
Symbol Type Name and Function
A0-A20 INPUT ADDRESS INPUTS: Inputs for addresses. 32M: A0-A20
DQ0-DQ15 INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User
Interface) write cycles, outputs data during memory array, status register, query code and
identifier code reads. Data pins float to high-impedance (High Z) when the chip or
outputs are deselected. Data is internally latched during an erase or program cycle.
CE# INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense
amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to
standby levels.
RST# INPUT
RESET: When low (VIL), RST# resets internal automation and inhibits write operations
which provides data protection. RST#-high (VIH) enables normal operation. After
power-up or reset mode, the device is automatically set to read array mode. RST# must
be low during power-up/down.
OE# INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of CE# or WE# (whichever goes high first).
VCC SUPPLY
DEVICE POWER SUPPLY (2.7V-3.6V): With VCC≤VLKO, all write attempts to the
flash memory are inhibited. Device operations at invalid VCC voltage (see DC
Characteristics) produce spurious results and should not be attempted.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated.
Rev. 2.41
sharp
LHF32FDH 5
54
53
52
51
50
49
48
55
56
57
58
59
60
61
63
64
65
66
67
68
62
69
70 4K-WORD 1FF000H - 1FFFFFH
4K-WORD 1FE000H - 1FEFFFH
4K-WORD 1FD000H - 1FDFFFH
4K-WORD 1FC000H - 1FCFFFH
4K-WORD 1FB000H - 1FBFFFH
4K-WORD 1FA000H - 1FAFFFH
4K-WORD 1F9000H - 1F9FFFH
4K-WORD 1F8000H - 1F8FFFH
32K-WORD 1F0000H - 1F7FFFH
32K-WORD 1E8000H - 1EFFFFH
32K-WORD 1E0000H - 1E7FFFH
32K-WORD 1D8000H - 1DFFFFH
32K-WORD 1D0000H - 1D7FFFH
32K-WORD 1C8000H - 1CFFFFH
32K-WORD 1C0000H - 1C7FFFH
32K-WORD 1B8000H - 1BFFFFH
32K-WORD 1B0000H - 1B7FFFH
32K-WORD 1A8000H - 1AFFFFH
32K-WORD 1A0000H - 1A7FFFH
32K-WORD 198000H - 19FFFFH
32K-WORD 190000H - 197FFFH
32K-WORD 188000H - 18FFFFH
32K-WORD 180000H - 187FFFH
32
33
34
35
36
37
38
40
41
42
43
44
45
39
46
47 32K-WORD 178000H - 17FFFFH
32K-WORD 170000H - 177FFFH
32K-WORD 168000H - 16FFFFH
32K-WORD 160000H - 167FFFH
32K-WORD 158000H - 15FFFFH
32K-WORD 150000H - 157FFFH
32K-WORD 148000H - 14FFFFH
32K-WORD 140000H - 147FFFH
32K-WORD 138000H - 13FFFFH
32K-WORD 130000H - 137FFFH
32K-WORD 128000H - 12FFFFH
32K-WORD 120000H - 127FFFH
32K-WORD 118000H - 11FFFFH
32K-WORD 110000H - 117FFFH
32K-WORD 108000H - 10FFFFH
32K-WORD 100000H - 107FFFH 0
1
2
3
4
5
6
8
9
10
11
12
13
7
14
15 32K-WORD 078000H - 07FFFFH
32K-WORD 070000H - 077FFFH
32K-WORD 068000H - 06FFFFH
32K-WORD 060000H - 067FFFH
32K-WORD 058000H - 05FFFFH
32K-WORD 050000H - 057FFFH
32K-WORD 048000H - 04FFFFH
32K-WORD 040000H - 047FFFH
32K-WORD 038000H - 03FFFFH
32K-WORD 030000H - 037FFFH
32K-WORD 028000H - 02FFFFH
32K-WORD 020000H - 027FFFH
32K-WORD 018000H - 01FFFFH
32K-WORD 010000H - 017FFFH
32K-WORD 008000H - 00FFFFH
32K-WORD 000000H - 007FFFH
16
17
18
19
20
21
22
24
25
26
27
28
29
23
30
31 32K-WORD 0F8000H - 0FFFFFH
32K-WORD 0F0000H - 0F7FFFH
32K-WORD 0E8000H - 0EFFFFH
32K-WORD 0E0000H - 0E7FFFH
32K-WORD 0D8000H - 0DFFFFH
32K-WORD 0D0000H - 0D7FFFH
32K-WORD 0C8000H - 0CFFFFH
32K-WORD 0C0000H - 0C7FFFH
32K-WORD 0B8000H - 0BFFFFH
32K-WORD 0B0000H - 0B7FFFH
32K-WORD 0A8000H - 0AFFFFH
32K-WORD 0A0000H - 0A7FFFH
32K-WORD 098000H - 09FFFFH
32K-WORD 090000H - 097FFFH
32K-WORD 088000H - 08FFFFH
32K-WORD 080000H - 087FFFH
BLOCK NUMBER ADDRESS RANGE
BLOCK NUMBER ADDRESS RANGE
Rev. 2.41
Figure 2. Memory Map (Top Parameter)
sharp
LHF32FDH 6
NOTES:
1. Top parameter device has its parameter blocks at the highest address.
2. DQ15-DQ2 are reserved for future implementation.
3. OTP-LK=OTP Block Lock configuration.
4. OTP=OTP Block data.
Table 2. Identifier Codes and OTP Address for Read Operation
Code Address
[A20-A0]
Data
[DQ15-DQ0]Notes
Manufacturer Code Manufacturer Code 000000H 00B0H
Device Code Top Parameter Device Code 000001H 00B4H 1
Block Lock Configuration
Code
Block is Unlocked Block
Address
+ 2
DQ0 = 0 2
Block is Locked DQ0 = 1 2
Block is not Locked-Down Block
Address
+ 2
DQ1 = 0 2
Block is Locked-Down DQ1 = 1 2
OTP OTP Lock 000080H OTP-LK 3
OTP 000081-
000088H OTP 4
Rev. 2.41
sharp
LHF32FDH 7
Rev. 2.41
Customer Programmable Area Lock Bit (DQ
1
)
Factory Programmed Area Lock Bit (DQ
0
)
Customer Programmable Area
Factory Programmed Area
Reserved for Future Implementation
000080H
000081H
000084H
000085H
000088H
[A
20
-A
0
]
(DQ
15
-DQ
2)
Figure 3. OTP Block Address Map for OTP Program
(The area outside 80H~88H cannot be used.)
sharp
LHF32FDH 8
Rev. 2.41
NOTES:
1. See DC Characteristics for VIL or VIH voltages.
2. X can be VIL or VIH for control pins and addresses.
3. RST# at GND±0.2V ensures the lowest power consumption.
4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably
executed when VCC=2.7V-3.6V.
5. Refer to Table 4 for valid DIN during a write operation.
6. Never hold OE# low and WE# low at the same timing.
7. Refer to Appendix of LH28F320BF series for more information about query code.
Table 3. Bus Operation(1, 2)
Mode Notes RST# CE# OE# WE# Address DQ0-15
Read Array 6 VIH VIL VIL VIH XD
OUT
Output Disable VIH VIL VIH VIH XHigh Z
Standby VIH VIH XX XHigh Z
Reset 3 VIL XXX XHigh Z
Read Identifier
Codes/OTP 6VIH VIL VIL VIH See
Table 2
See
Table 2
Read Query 6,7 VIH VIL VIL VIH See
Appendix
See
Appendix
Write 4,5,6 VIH VIL VIH VIL XD
IN
sharp
LHF32FDH 9
NOTES:
1. Bus operations are defined in Table 3.
2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus
cycle.
X=Any valid address within the device.
IA=Identifier codes address (See Table 2).
QA=Query codes address. Refer to Appendix of LH28F320BF series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
3. ID=Data read from identifier codes. (See Table 2).
QD=Data read from query database. Refer to Appendix of LH28F320BF series for details.
SRD=Data read from status register. See Table 7 and Table 8 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes
high first).
OD=Data to be programmed at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes
high first).
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, and the data within OTP block (See Table 2).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
block can be erased or programmed when RST# is VIH.
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any
valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of
LH28F320BF series for details.
8. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted
Table 4. Command Definitions(10)
Command
Bus
Cycles
Req’d
Notes
First Bus Cycle Second Bus Cycle
Oper(1) Addr(2) Data(3) Oper(1) Addr(2) Data(3)
Read Array 1 2 Write X FFH
Read Identifier Codes/OTP ≥ 2 2,3,4 Write X 90H Read IA or OA ID or OD
Read Query ≥ 2 2,3,4 Write X 98H Read QA QD
Read Status Register 2
2,3,11
Write BA or WA 70H Read BA or WA SRD
Clear Status Register 1 2 Write X 50H
Block Erase 2 2,3,5 Write BA 20H Write BA D0H
Full Chip Erase 2 2,5,8 Write X 30H Write X D0H
Program 2 2,3,5,6 Write WA 40H or
10H Write WA WD
Page Buffer Program ≥ 4 2,3,5,7 Write WA E8H Write WA N-1
Block Erase and (Page Buffer)
Program Suspend 12,8WriteBA or WAB0H
Block Erase and (Page Buffer)
Program Resume 1 2,8 Write BA or WA D0H
Set Block Lock Bit 2 2 Write BA 60H Write BA 01H
Clear Block Lock Bit 2 2,9 Write BA 60H Write BA D0H
Set Block Lock-down Bit 2 2 Write BA 60H Write BA 2FH
OTP Program 2 2,3,8 Write OA C0H Write OA OD
Rev. 2.41
sharp
LHF32FDH 10
while the block erase operation is being suspended.
9. Following the Clear Block Lock Bit command, the selected block is unlocked regardless of lock-down configuration.
10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be
used.
11. When the status register data is read, input the address to which the erase or program operation is executed.
Rev. 2.41
sharp
LHF32FDH 11
NOTES:
1. DQ0=1: a block is locked; DQ0=0: a block is unlocked.
DQ1=1: a block is locked-down; DQ1=0: a block is not locked-down.
2. Erase and program are general terms, respectively, to express: block erase, full chip erase and
(page buffer) program operations.
3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,
[01] regardless of the states before power-off or reset operation.
4. OTP (One Time Program) block has the lock function which is different from those described
above.
NOTES:
1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit
command and "Set Lock-down" means Set Block Lock-Down Bit command.
2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the
corresponding block is locked-down and automatically locked at the same time.
3. "No Change" means that the state remains unchanged after the command written.
Table 5. Functions of Block Lock(4) and Block Lock-Down
Current State
Erase/Program Allowed (2)
State DQ1(1) DQ0(1) State Name
[00] 0 0 Unlocked Yes
[01](3) 0 1 Locked No
[10] 1 0 Unlocked Yes
[11] 1 1 Locked No
Table 6. Block Locking State Transitions upon Command Write
Current State Result after Lock Command Written (Next State)
State DQ1DQ0Set Lock(1) Clear Lock(1) Set Lock-down(1)
[00] 0 0 [01] No Change(3) [11](2)
[01] 0 1 No Change [00] [11]
[10] 1 0 [11] No Change [11](2)
[11] 1 1 No Change [10] No Change
Rev. 2.41
sharp
LHF32FDH 12
Table 7. Status Register Definition
RRRRRRRR
15 14 13 12 11 10 9 8
WSMS BESS BEFCES PBPOPS R PBPSS DPS R
76543210
SR.15 - SR.8 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
STATUS (BEFCES)
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
SR.4 = (PAGE BUFFER) PROGRAM AND
OTP PROGRAM STATUS (PBPOPS)
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
SR.3 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
STATUS (PBPSS)
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Erase or Program Attempted on a
Locked Block, Operation Abort
0 = Unlocked
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
Check SR.7 to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, page buffer program, set/clear block lock bit, set block
lock-down bit, attempt, an improper command sequence was
entered.
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.15 - SR.8, SR.3 and SR.0 are reserved for future use and
should be masked out when polling the status register.
Rev. 2.41
sharp
LHF32FDH 13
Rev. 2.41
Table 8. Extended Status Register Definition
RRRRRRRR
15 14 13 12 11 10 9 8
SMSRRRRRRR
76543210
XSR.15-8 =
RESERVED FOR FUTURE
ENHANCEMENTS (R)
XSR.7 = STATE MACHINE STATUS (SMS)
1 = Page Buffer Program available
0 = Page Buffer Program not available
XSR.6-0 =
RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTES:
After issue a Page Buffer Program command (E8H),
XSR.7="1" indicates that the entered command is accepted.
If XSR.7 is "0", the command is not accepted and a next Page
Buffer Program command (E8H) should be issued again to
check if page buffer is available or not.
XSR.15-8 and XSR.6-0 are reserved for future use and
should be masked out when polling the extended status
register.
sharp
LHF32FDH 14
1 Electrical Specifications
1.1 Absolute Maximum Ratings*
Operating Temperature
During Read, Erase and Program ...... 0°C to +70°C(1)
Storage Temperature
During under Bias............................... -10°C to +80°C
During non Bias................................ -65°C to +125°C
Vo l t a g e O n A ny P i n
(except VCC)............................ -0.5V to VCC+0.5V (2)
VCC Supply Voltage ........................... -0.2V to +3.9V (2)
Output Short Circuit Current ...........................100mA (3)
*WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent
damage. These are stress ratings only. Operation
beyond the "Operating Conditions" is not
recommended and extended exposure beyond
the "Operating Conditions" may affect device
reliability.
NOTES:
1. Operating temperature is for commercial temperature
product defined by this specification.
2. All specified voltages are with respect to GND.
Minimum DC voltage is -0.5V on input/output pins
and -0.2V on VCC pins. During transitions, this level
may undershoot to -2.0V for periods <20ns. Maximum
DC voltage on input/output pins and VCC is VCC+0.5V
which, during transitions, may overshoot to VCC
+2.0V for periods <20ns.
3. Output shorted for no more than one second. No more
than one output shorted at a time.
Rev. 2.41
1.2 Operating Conditions
NOTES:
1. See DC Characteristics tables for voltage range-specific specification.
Parameter Symbol Min. Typ. Max. Unit Notes
Operating Temperature TA0+25+70°C
VCC Supply Voltage VCC 2.7 3.0 3.6 V 1
Main Block Erase Cycling 100,000 Cycles
Parameter Block Erase Cycling 100,000 Cycles
sharp
LHF32FDH 15
TEST POINTSVCC/2 VCC/2INPUT
VCC
0.0
OUTPUT
AC test inputs are driven at VCC(min) for a Logic "1" and 0.0V for a Logic "0".
Input timing begins, and output timing ends at VCC/2. Input rise and fall times (10% to 90%) < 5ns.
Worst case speed conditions are when VCC=VCC(min).
DEVICE
UNDER
TEST
RL=3.3k
CL
VCC(min)/2
OUT
CL Includes Jig
Capacitances.
1N914
Figure 5. Transient Equivalent Testing Load Circuit
Rev. 2.41
Table 9. Configuration Capacitance Loading Value
Test Configuration CL (pF)
VCC=2.7V-3.6V 50
1.2.2 AC Input/Output Test Conditions
1.2.1 Capacitance(1) (TA=+25°C, f=1MHz)
NOTE:
1. Sampled, not 100% tested.
Parameter Symbol Condition Min. Typ. Max. Unit
Input Capacitance CIN VIN=0.0V 47pF
RST# Input Capacitance CIN VIN=0.0V 20 28 pF
Output Capacitance COUT VOUT=0.0V 610pF
Figure 4. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V
sharp
LHF32FDH 16
Rev. 2.41
1.2.3 DC Characteristics
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V and TA=+25°C
unless VCC is specified.
2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend
mode, the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW
, respectively.
3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when VCC≤VLKO, and not guaranteed
outside the specified voltage.
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
completion. Standard address access timings (tAVQV) provide new data when addresses are changed.
5. Sampled, not 100% tested.
VCC=2.7V-3.6V
Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions
ILI Input Load Current 1 -1.0 +1.0 µAVCC=VCCMax.,
VIN/VOUT=VCC or
GND
ILO Output Leakage Current 1 -1.0 +1.0 µA
ICCS VCC Standby Current 1625µA
VCC=VCCMax.,
CE#=RST#=
VCC±0.2V
ICCAS VCC Automatic Power Savings Current 1,4 4 20 µAVCC=VCCMax.,
CE#=GND±0.2V
ICCD VCC Reset Power-Down Current 1420µA RST#=GND±0.2V
ICCR
Average VCC Read
Current
Normal Mode
11525mA
VCC=VCCMax.,
CE#=VIL,
OE#=VIH,
f=5MHz
Average VCC Read
Current
Page Mode
8 Word Read 1 5 10 mA
ICCW VCC (Page Buffer) Program Current 1,5 20 60 mA
ICCE
VCC Block Erase, Full Chip
Erase Current 1,5 10 30 mA
ICCWS
ICCES
VCC (Page Buffer) Program or
Block Erase Suspend Current 1,2 15 210 µACE#=VIH
VIL Input Low Voltage 5 -0.4 0.4 V
VIH Input High Voltage 5 VCC
-0.4
VCC
+ 0.4 V
VOL Output Low Voltage 5 0.2 V VCC=VCCMin.,
IOL=100µA
VOH Output High Voltage 5 VCC
-0.2 VVCC=VCCMin.,
IOH=-100µA
VLKO VCC Lockout Voltage 31.5 V
sharp
LHF32FDH 17
1.2.4 AC Characteristics - Read-Only Operations(1)
NOTES:
1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.
2. Sampled, not 100% tested.
3. OE# may be delayed up to tELQV tGLQV after the falling edge of CE# without impact to tELQV
.
VCC=2.7V-3.6V, TA=0°C to +70°C
Symbol Parameter
Notes
Min. Max. Unit
tAVAV Read Cycle Time 70 ns
tAVQV Address to Output Delay 70 ns
tELQV CE# to Output Delay 3 70 ns
tAPA Page Address Access Time 25 ns
tGLQV OE# to Output Delay 3 20 ns
tPHQV RST# High to Output Delay 150 ns
tEHQZ, tGHQZ CE# or OE# to Output in High Z, Whichever Occurs First 2 20 ns
tELQX CE# to Output in Low Z 2 0 ns
tGLQX OE# to Output in Low Z 2 0 ns
tOH Output Hold from First Occurring Address, CE# or OE# change 2 0 ns
Rev. 2.41
sharp
LHF32FDH 18
tAVQV
tEHQZ
tGHQZ
tELQV
tPHQV
tGLQV
tOH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
(P)
(D/Q)
(W)
(G)
(E)
(A)A20-0
DQ15-0
CE#
OE#
WE#
RST#
High Z
tELQX
VALID
OUTPUT
VALID
ADDRESS
tGLQX
Figure 6. AC Waveform for Single Asynchronous Read Operations
from Status Register, Identifier Codes, OTP Block or Query Code
Rev. 2.41
sharp
LHF32FDH 19
tAVQV
tELQV tEHQZ
tGHQZ
tOH
tAPA
tGLQV
tPHQV
High Z
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
(P)
(W)
(G)
(E)
(A)A20-3
VIH
VIL
(A)A2-0
VOH
VOL
(D/Q)
DQ15-0
CE#
OE#
WE#
RST#
tGLQX
tELQX
VALID
ADDRESS
VALID
ADDRESS VALID
ADDRESS VALID
ADDRESS
VALID
OUTPUT VALID
OUTPUT VALID
OUTPUT VALID
OUTPUT
VALID
ADDRESS
Figure 7. AC Waveform for Asynchronous Page Mode Read Operations
from Main Blocks or Parameter Blocks
Rev. 2.41
sharp
LHF32FDH 20
Rev. 2.41
1.2.5 AC Characteristics - Write Operations(1), (2)
NOTES:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and
OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH.
5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
edge of CE# or WE# (whichever goes low last). Hence, tWPH=tWHWL=tEHEL=tWHEL=tEHWL.
6. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns.
7. Refer to Table 4 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
configuration.
VCC=2.7V-3.6V, TA=0°C to +70°C
Symbol Parameter Notes Min. Max. Unit
tAVAV Write Cycle Time 70 ns
tPHWL (tPHEL)
RST# High Recovery to WE# (CE#) Going Low
3150 ns
tELWL (tWLEL)CE# (WE#) Setup to WE# (CE#) Going Low 4 0 ns
tWLWH (tELEH)WE# (CE#) Pulse Width 4 50 ns
tDVWH (tDVEH)Data Setup to WE# (CE#) Going High 7 40 ns
tAV W H (tAV E H )Address Setup to WE# (CE#) Going High 7 50 ns
tWHEH (tEHWH)CE# (WE#) Hold from WE# (CE#) High 0 ns
tWHDX (tEHDX)Data Hold from WE# (CE#) High 0 ns
tWHAX (tEHAX)Address Hold from WE# (CE#) High 0 ns
tWHWL (tEHEL)WE# (CE#) Pulse Width High 5 20 ns
tWHGL (tEHGL)Write Recovery before Read 30 ns
tWHR0 (tEHR0)WE# (CE#) High to SR.7 Going "0" 3, 6 tAVQV+
40 ns
sharp
LHF32FDH 21
tAVAV tAVWH (tAVEH)
tWHAX
(tEHAX)
tELWL (tWLEL)
tPHWL (tPHEL)
tWLWH
tWHWL (tEHEL)
tWHDX (tEHDX)tDVWH (tDVEH)
tWHQV1,2,3 (tEHQV1,2,3)
tWHEH (tEHWH)t
WHGL (tEHGL)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
(D/Q)
(W)
(G)
(E)
(A)
NOTES 5, 6
A20-0
DQ15-0
VIH
VIL
(P)
RST#
CE#
OE#
WE#
(tELEH )
NOTE 1 NOTE 2 NOTE 3 NOTE 4 NOTE 5
VALID
ADDRESS VALID
ADDRESS VALID
ADDRESS
DATA IN DATA IN VALID
SRD
"1"
"0"
(R)SR.7
tWHR0 (tEHR0)
NOTES 5, 6
NOTES:
1. VCC power-up and standby.
2. Write each first cycle command.
3. Write each second cycle command or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operation, OE# and CE# must be driven active, and WE# de-asserted.
Figure 8. AC Waveform for Write Operations
Rev. 2.41
sharp
LHF32FDH 22
ABORT
COMPLETE
tPLPH
tPLPH
t2VPH
tPLRH tPHQV
tPHQV
(A) Reset during Read Array Mode
(B) Reset during Erase or Program Mode
(C) RST# rising timing
RST#
RST#
VIL
VIH
VIL
VIH
VCC GND
VCC(min)
RST# VIL
VIH
SR.7="1"
VOH
VOL
(D/Q)
DQ15-0 VALID
OUTPUT
High Z
(P)
(P)
(P)
VOH
VOL
(D/Q)
DQ15-0 VALID
OUTPUT
High Z
VOH
VOL
(D/Q)
DQ15-0 VALID
OUTPUT
High Z
tPHQV
tVHQV
NOTES:
1. A reset time, tPHQV
, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC
Characteristics - Read-Only Operations for tPHQV
.
2. tPLPH is <100ns the device may still reset but this is not guaranteed.
3. Sampled, not 100% tested.
4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,
the reset will complete within 100ns.
5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and
also has been in stable there.
Reset AC Specifications (VCC=2.7V-3.6V, TA=0°C to +70°C)
Symbol Parameter Notes Min. Max. Unit
tPLPH RST# Low to Reset during Read
(RST# should be low during power-up.) 1, 2, 3 100 ns
tPLRH RST# Low to Reset during Erase or Program 1, 3, 4 22 µs
t2VPH VCC 2.7V to RST# High 1, 3, 5 100 ns
tVHQV VCC 2.7V to Output Delay 31ms
Figure 9. AC Waveform for Reset Operations
Rev. 2.41
1.2.6 Reset Operations
sharp
LHF32FDH 23
Rev. 2.41
1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3)
NOTES:
1. Typical values measured at VCC=3.0V and TA=+25°C. Assumes corresponding lock bits
are not set. Subject to change based on device characterization.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".
5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter
than tERES and its sequence is repeated, the block erase operation may not be finished.
VCC=2.7V-3.6V, TA=0°C to +70°C
Symbol Parameter Notes
Page Buffer
Command is
Used or not
Used
Min. Typ.(1)
Max.
(2)
Unit
tWPB 4K-Word Parameter Block
Program Time
2 Not Used 0.05 0.3 s
2 Used 0.03 0.12 s
tWMB 32K-Word Main Block
Program Time
2 Not Used 0.38 2.4 s
2 Used 0.24 1.0 s
tWHQV1/
tEHQV1
Word Program Time 2 Not Used 11 200 µs
2 Used 7 100 µs
tWHOV1/
tEHOV1
OTP Program Time 2 Not Used 36 400 µs
tWHQV2/
tEHQV2
4K-Word Parameter Block
Erase Time 2- 0.34s
tWHQV3/
tEHQV3
32K-Word Main Block
Erase Time 2- 0.65s
Full Chip Erase Time 2 40 350 s
tWHRH1/
tEHRH1
(Page Buffer) Program Suspend
Latency Time to Read 4- 510µs
tWHRH2/
tEHRH2
Block Erase Suspend
Latency Time to Read 4- 520µs
tERES
Latency Time from Block Erase
Resume Command to Block
Erase Suspend Command
5 - 500 µs
sharp
LHF32FDH 24
Rev. 2.41
2 Related Document Information(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales offices.
Document No. Document Name
FUM00701 LH28F320BF series Appendix
sharp
Rev. 1.10
i
A-1 RECOMMENDED OPERATING CONDITIONS
A-1.1 At Device Power-Up
AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
Figure A-1. AC Timing at Device Power-Up
For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“
described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in
the next page.
t2VPH
VCC
GND
VCC(min)
RP#
VIL
VIH
(P)
tPHQV
CE#
VIL
VIH
(E)
WE#
VIL
VIH
(W)
OE#
VIL
VIH
(G)
VOH
VOL
(D/Q)
DATA High Z Valid
Output
tVR
tFtELQV
tFtGLQV
(A)ADDRESS Valid
(RST#)
tRor tF
Address
VIL
VIH
tAVQV tRor tF
tR
tR
sharp
Rev. 1.10
ii
A-1.1.1 Rise and Fall Time
NOTES:
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
Symbol Parameter Notes Min. Max. Unit
tVR VCC Rise Time 1 0.5 30000 µs/V
tRInput Signal Rise Time 1, 2 1 µs/V
tFInput Signal Fall Time 1, 2 1 µs/V
sharp
Rev. 1.10
iii
A-1.2 Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals,
as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a).
Figure A-2. Waveform for Glitch Noises
See the “DC CHARACTERISTICS“ described in specifications for VIH (Min.) and VIL (Max.).
(a) Acceptable Glitch Noises
Input Signal
VIH (Min.)
Input Signal
VIH (Min.)
Input Signal
VIL (Max.)
Input Signal
VIL (Max.)
(b)
NOT
Acceptable Glitch Noises
sharp
Rev. 1.10
iv
A-2 RELATED DOCUMENT INFORMATION(1)
NOTE:
1. International customers should contact their local SHARP or distribution sales office.
Document No. Document Name
AP-001-SD-E Flash Memory Family Software Drivers
AP-006-PT-E Data Protection Method of SHARP Flash Memory
AP-007-SW-E RP#, VPP Electric Potential Switching Circuit
sharp
SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited
Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.
ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND
FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,
for any incidental or consequential economic or property damage.
NORTH AMERICA EUROPE JAPAN
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Phone: (1) 360-834-2500
Fax: (1) 360-834-8903
Fast Info: (1) 800-833-9437
www.sharpsma.com
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Division of Sharp Electronics (Europe) GmbH
Sonninstrasse 3
20097 Hamburg, Germany
Phone: (49) 40-2376-2286
Fax: (49) 40-2376-2232
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Electronic Components & Devices
22-22 Nagaike-cho, Abeno-Ku
Osaka 545-8522, Japan
Phone: (81) 6-6621-1221
Fax: (81) 6117-725300/6117-725301
www.sharp-world.com
TAIWAN SINGAPORE KOREA
SHARP Electronic Components
(Taiwan) Corporation
8F-A, No. 16, Sec. 4, Nanking E. Rd.
Taipei, Taiwan, Republic of China
Phone: (886) 2-2577-7341
Fax: (886) 2-2577-7326/2-2577-7328
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438A, Alexandra Road, #05-01/02
Alexandra Technopark,
Singapore 119967
Phone: (65) 271-3566
Fax: (65) 271-3855
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(Korea) Corporation
RM 501 Geosung B/D, 541
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Seoul 121-701, Korea
Phone: (82) 2-711-5813 ~ 8
Fax: (82) 2-711-5819
CHINA HONG KONG
SHARP Microelectronics of China
(Shanghai) Co., Ltd.
28 Xin Jin Qiao Road King Tower 16F
Pudong Shanghai, 201206 P.R. China
Phone: (86) 21-5854-7710/21-5834-6056
Fax: (86) 21-5854-4340/21-5834-6057
Head Office:
No. 360, Bashen Road,
Xin Development Bldg. 22
Waigaoqiao Free Trade Zone Shanghai
200131 P.R. China
Email: smc@china.global.sharp.co.jp
SHARP-ROXY (Hong Kong) Ltd.
3rd Business Division,
17/F, Admiralty Centre, Tower 1
18 Harcourt Road, Hong Kong
Phone: (852) 28229311
Fax: (852) 28660779
www.sharp.com.hk
Shenzhen Representative Office:
Room 13B1, Tower C,
Electronics Science & Technology Building
Shen Nan Zhong Road
Shenzhen, P.R. China
Phone: (86) 755-3273731
Fax: (86) 755-3273735
