PIC16F628A-I/SSG - Microchip Technology

 2004 Microchip Technology Inc. Preliminary DS40044B

PIC16F627A/628A/648A

Data Sheet

Flash-Based 8-Bit CMOS

Microcontrollers with nanoWatt Technology

DS40044B-page ii Preliminary  2004 Microchip Technology Inc.

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The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, MPLAB, PIC, PI Cmicro, PIC START,

PRO MATE, PowerSm art and rfPIC are registered

trademarks of Microchip Technology Incorporat ed in the

U.S.A. and other countries.

AmpLab, FilterLab, microID, MXDEV, M XL AB, PICMASTE R ,

SEEVAL, SmartShunt and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDE M. net,

dsPICwo rks, ECAN, ECONOMONITOR, Fan Sen s e ,

FlexROM, fuzzyLAB , In-C ircuit Serial Programm ing, ICSP,

ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK,

MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal,

PowerInfo, PowerMate , PowerTool, rfLAB, Select Mode,

SmartSensor , SmartTel and Total Endurance are trademarks

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countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

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Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously impro ving the cod e protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Mic ro chi p re cei v e d IS O/T S - 16 949 : 20 02 qu ality syste m c er t if i cat i on f or

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and T empe, Arizona and Mountain View, California in October

2003. The Company’s quality system processes and procedur es are for

its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 1

PIC16F627A/628A/648A

High Performance RISC CPU:

• Operati ng spe eds from DC - 20 MHz

• Interrupt capability

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

• 35 single word ins truc t i ons

- All instructions single cycle except branches

Special Microcontroller Features:

• Internal and external os cil la tor opti ons

- Precision Internal 4 MHz oscillator factory

calibrated to ±1%

- Low Power Inte rnal 37 kHz oscillator

- External Oscillator support for crystals and

resonators.

• Power saving Sleep mode

• Programm abl e we ak pul l-u p s on PORTB

• Multipl ex ed Ma ste r Clear/In put-pin

• Watchdog Timer with independent oscillator for

reliable operation

• Low voltage programming

• In-Circuit Serial Programming™ (via two pins)

• Programmable code protection

• Brown-out Reset

• Power-on Reset

• Power-up Timer and Oscillat or Start-up Timer

• Wide operating voltage range. (2.0 - 5.5V)

• Industrial and extended temperature range

• High Endurance Flash/EEPROM Cell

- 100,000 write Flash end urance

- 1,000,000 write EEPROM endurance

- 100 year data retention

Low Power Features:

• Standby Current:

- 100 nA @ 2.0V, typical

• Operating Current:

-12µA @ 32 kHz, 2.0V, typical

-120µA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current

-1µA @ 2.0V, typical

• Timer1 oscillator current:

-1.2µA @ 32 kHz, 2.0V, typical

• Dual Speed Internal Oscillator:

- Run-time selec t able between 4 MHz and

37 kHz

-4µs wake-up from Sleep, 3.0V, typical

Peripheral Feat ures:

• 16 I/O pins with indiv idual direction control

• High current sink/source for direct LED drive

• Analog comparator module with:

- Two analog compar ators

- Programmable on-chip voltage reference

(VREF) module

- Selectable internal or external reference

- Comparator outputs are externally accessible

• Timer0: 8-bit timer/counter with 8-bit

progra mmab le pres caler

• Timer1: 16-bit timer/counter with external crystal/

clock capability

• Timer2: 8-bit timer/counter with 8-bit period

• Capture , Comp a re, PWM module

- 16-bit Capture/Compare

-10-bit PWM

• Addressable Universal Synchronous/Asynchronous

Receiv er/Trans mitter U SAR T/SCI

Device

Program

Memory Data Memor y I/O CCP

(PWM) USART Comparators Timers

8/16-bit

Flash

(words) SRAM

(bytes) EEPROM

(bytes)

PIC16F627A 1024 224 128 16 1 Y 2 2/1

PIC16F628A 2048 224 128 16 1 Y 2 2/1

PIC16F648A 4096 256 256 16 1 Y 2 2/1

18-pin Flash-Based 8-Bit CMOS Microcontrollers

with nanoWatt Techno logy

PIC16F627A/628A/648A

DS40044B-page 2 Preliminary  2004 Microchip Technology Inc.

Pin Diagrams

PDIP, SOIC

SSOP

PIC16F627A/628A/648A

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VSS

VSS VDD

VDD

RA1/AN1

RA0/AN0

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

RB1/RX/DT

RB2/TX/CK

RB3/CCP1 RB4/PGM

RB5

RA3/AN3/CMP1

RA4/TOCKI/CMP2

RA5/MCLR/VPP

RB0/INT

RA2/AN2/VREF

VSS

RB1/RX/DT

RB2/TX/CK

RB3/CCP1

RA3/AN3/CMP1

RA4/TOCKI/CMP2

RA5/MCLR/VPP

RB0/INT

RA2/AN2/VREF

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VDD

RA1/AN1

RA0/AN0

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

RB4/PGM

RB5

PIC16F627A/628A/648A

RA2/AN2/VREF

RA3/AN3/CMP1

RA4/T0CKI/CMP2

RA5/MCLR/VPP

VSS

RB0/INT

RB1/RX/DT

RB2/TX/CK

RB3/CCP1

RA1/AN1

RA0/AN0

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

RB7/T1OSI/PGD

RB6/T1OSO/T1CKI/PG

RB5

VDD

RB4/PGM

VSS

NC VDD

PIC16F627A/628A

PIC16F648A

28-Pin

QFN

118

PIC16F627A/628A/648A

 2004 Microchip Technology Inc. Preliminary DS40044B-page 3

PIC16F627A/628A/648A

Table of Contents

1.0 General Description............... ....... .. .... .. .... .. ....... .... .. .... .. ....... .... .. .... .. .. ......... .. .... .. .. .... ................................................................... 5

2.0 PIC16F627A/628A/648A Devic e Varieties..................... .......................................... .................................................................... 7

3.0 Arc hitectural Overview ................................................................................................................................................................. 9

4.0 Memory Organization....................................................... . ......................................................................................................... 15

5.0 I /O Po r ts.................... ................... ........................... ................... ................... ............................................................................. 31

6.0 Timer0 Module ........................................ ................................................................................................................................... 45

7.0 Timer1 Module ........................................ ................................................................................................................................... 48

8.0 Timer2 Module ........................................ ................................................................................................................................... 52

9.0 Capture/Compare/PWM (CCP) Module.................. ........ ............... ................. ...... ................. ...... .............................................. 55

10.0 Comparator Module...................... .... .. .... .. ......... .. .... .. .... .. ......... .. .... .. .... ....... .... .. .... .. ......... .......................................................... 61

11.0 Voltage Reference Module.................................. .. .. .... .. .. ..... .... .. .. .. .. .... ..... .. .... .. .. .. .. ....... .. .. .. ...................................................... 67

12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module........................................................................ 69

13.0 Data EEPROM Mem o ry................. ................... ................... ................... .................. ................................................................. 89

14.0 Specia l Features of the CPU...................... ................... ................... ................... ................. ...................................................... 93

15.0 Instruction Set Summary.......................................................................................................................................................... 111

16.0 Development Support................................ ............................................................................................................................... 125

17.0 Electrical Specifications ............................................................................................................................................................ 131

18.0 DC and AC Characteristics Graphs and Tables................................... ......... .... .... .. ......... .... .... .... .. .......................................... 147

19.0 Packagin g In fo rmation........................ ................... ................... ................... ............................................................................. 149

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Customer Noti fic atio n Syst em

PIC16F627A/628A/648A

DS40044B-page 4 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 5

PIC16F627A/628A/648A

1.0 GENERAL DESCRIPTION

The PIC16F627A/628A/648A are 18-Pin Flash-based

members of the versatile PIC16CXX family of low cost,

high performance, CMOS, fully-static, 8-bit

microcontrollers.

All PICmicro® microcontrollers employ an advanced

RISC architecture. The PIC16F627A/628A/648A have

enhanced core features, eight-level deep stack, and

multiple internal and external interrupt sources. The

separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two-stage instruction

pipeline allows all instructions to execute in a single-

cycl e, except for program branc hes (which require two

cycles). A total of 35 instructions (reduced instruction

set) are available, complemented by a large register

set.

PIC16F627A/628A/648A microcontrollers typically

achieve a 2:1 code compression and a 4:1 speed

improvement over other 8-bit microcontrollers in their

class.

PIC16F627A/628A/648A devices have integrated

featur es to reduce extern al com ponent s, th us redu cing

system c ost, enhancing s ystem rel ia bil ity an d reducing

power consumptio n.

The PIC16F627A/628A/648A has 8 oscillator configu-

rations. The single-pin RC oscillator provides a low cost

solution. The LP oscillator minimizes power consump-

tion, XT is a standard crystal, and INTOSC is a self-

contained precision two-speed internal oscillator. The

HS is for High-Speed crystals. The EC mode is for an

external clock source.

The Sleep (Power-down) mode offers power savings.

Users can wake-up the chip from Sleep through

several external interrupts, internal interrupts and

Resets.

A highly reliable Watchdog Timer with its own on-chip

RC osci llator provid es protection against softwa re lock-

up.

Table 1-1 shows the features of the PIC16F627A/

628A/648A mid-range m ic r o c o n tr o l l e r f a m ilies.

A simplified block diagram of the PIC16F627A/628A/

648A is shown in Figure 3-1.

The PIC16F 627 A/62 8A/6 48A se rie s fit s in app lic ati on s

ranging from battery chargers to low power remote

sensors. The Flash technology makes customizing

application programs (detection levels, pulse genera-

tion, timers, etc.) extremely fast and convenient. The

small footprint packages makes this microcontroller

series ideal for all applications with space limitations.

Low cost, low power, high performance, ease of use

and I/O flexibility make the PIC16F627A/628A/648A

very versatile.

1.1 Development Support

The PIC16F627A/628A/648A family is supported by a

full-feat ured mac ro assem bler , a softwar e simulato r , a n

in-circuit emulator, a low cos t i n-c irc ui t d ebu gge r, a low

cost development programmer and a full-featured

programmer. A Third Party “C” compiler support tool is

also available.

TABLE 1-1: PIC16F627A/628A/648A FAMILY OF DEVICES

PIC16F627A PIC16F628A PIC16F648A PIC16LF627A PIC16LF628A PIC16LF648A

Clock Maximum Frequency

of Operati on (MHz ) 20 20 20 4 4 4

Flash Program Mem-

ory (words) 1024 2048 4096 1024 2048 4096

Memory RAM Data Memory

(bytes) 224 224 256 224 224 256

EEPROM Data Mem-

ory (bytes) 128 128 256 128 128 256

Timer mo dule (s) TMR0, TMR1,

TMR2 TMR0, TMR1,

TMR2

Comparator(s) 222222

Peripherals Capture/Compare/

PWM modules 111111

Serial Communications USART USART USART USART USART USART

Internal Voltage

Reference Yes Yes Yes Yes Yes Yes

Interrupt Sources 10 10 10 10 10 10

I/O Pins 16 16 16 16 16 16

Features Voltage Range (Volts) 3.0-5.5 3.0-5.5 3.0-5.5 2.0-5.5 2.0-5.5 2.0-5.5

Brown-out Reset Yes Yes Yes Yes Yes Yes

Packages 18-pin DIP,

SOIC, 20-pin

SSOP,

28- p in QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

18-pin DIP,

SOIC, 20-pin

SSOP,

28-pin QFN

All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability.

All PIC16F627A/628A/648A Family devices use serial programming with clock pin RB6 and data pin RB7.

PIC16F627A/628A/648A

DS40044B-page 6 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 7

PIC16F627A/628A/648A

2.0 PIC16F627A/628A/648A

DEVICE VARIETIES

A variety of frequency ranges and packaging options

are avail able. Depending on application an d production

requirem ents, the p roper device o ption can be s elected

using the information in the PIC16F627A/628A/648A

Product Identification System, at the end of this data

sheet. When placing orders, please use this page of

the data sheet to specify the correct part number.

2.1 Flash Devices

Flash devices can be erased and re-programmed

electric al ly. This allows the same devi ce to be used for

proto type deve lopment, pilot prog rams and productio n.

A further adv antag e of the elec trically eras able Flas h is

that it can be erased and re programmed in-circuit, or by

device programmers, such as Microchip's

PICSTART® Plus, or PRO MATE® II programmers.

2.2 Quick-Turnaround-Production

(QTP) Devices

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who chose not to program a medium

to high quantity of un its and whos e c ode patterns hav e

stabilized. The devices are standard Flash devices but

with all program locations and configuration options

already programmed by the factory. Certain code and

prototype verification procedures apply before

production shipments are available. Please contact

your Microchip Technology sales office for more

details.

2.3 Serialized Quick-Turnaround-

Production (SQTPSM) Devi ces

Microchip offers a unique programming service where

a few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Serial programming allows each device to have a

unique number, which can serve as an entry-code,

password or ID number.

PIC16F627A/628A/648A

DS40044B-page 8 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 9

PIC16F627A/628A/648A

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16F627A/628A/648A

family can be attributed to a number of architectural

featur es comm only fo und in RISC mic roproc essor s. To

begin with, the PIC16F627A/628A/648A uses a

Harvard architecture, in which program and data are

accessed from separate memories using separate

busses. This improves bandwidth over traditional Von

Neumann architecture where program and data are

fetched from the same memory. Separating program

and dat a memor y further allows instructions to be sized

differently than 8-bit wide data word. Instruction

opco de s a re 14-bits wide making it pos si ble to have al l

single word instructions. A 14-bit wide program mem-

ory access bus fetches a 14-bit instruction in a single

cycle. A two-stage pipeline overlaps fetch and execu-

tion of instructions. Consequently, all instructions (35)

execute in a single-cycle (200 ns @ 20 MHz) except for

progra m bran ch es.

Table 3-1 lists device memory sizes (Flash, Data and

EEPROM).

TABLE 3-1: DEVICE MEMORY LIST

The PIC16F627A/628A/648A can directly or indirectly

address its register files or data memory. All Special

Function Registers (SFR), including the program

counter, are mapped in the data memory. The

PIC16F6 27A/628A/648A ha ve an orthogon al (symmet-

rical) instruction set that makes it possible to carry out

any operation, on any register, using any Addressing

mode. This symmetrical nature and lack of ‘special

optimal situations’ make programming with the

PIC16F627A/628A/648A simple yet efficient. In

addition, the learning curve is reduced significantly.

The PIC16F627A/628A/648A devices contain an 8-bit

ALU and working register. The ALU is a general

purpose arithmetic unit. It performs arithmetic and

Boolean fu nctions b etween da ta in the work ing regis ter

and any register file.

The ALU is 8-bit wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the working register

(W register). The other operand is a file register or an

immedi ate con st ant. In si ngle op eran d instru ction s, the

operand is either the W register or a file register.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affe ct the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the Status Register. The C and DC bits

operate as a Borrow and Digit Borrow out bit,

respectively, bit in subtraction. See the SUBLW and

SUBWF instructions for examples.

A simplified block diagram is shown in Figure 3-1, and

a description of the device pins in Table 3-2.

Two types of data memory are provided on the

PIC16F627A/628A/648A devices. Nonvolatile

EEPROM data memory is provided for long term stor-

age of data such as calibration values, look up table

data, and any other data which may require periodic

updating in the field. These data are not lost when

power is removed. The other data memory provided is

regular R AM data memory. Regular R AM data memory

is provid ed for temporary storage of da ta during norma l

operation. Data are lost when power is removed.

Device

Memory

Flash

Program RAM

Data EEPROM

Data

PIC16F627A 1024 x 14 224 x 8 128 x 8

PIC16F628A 2048 x 14 224 x 8 128 x 8

PIC16F648A 4096 x 14 256 x 8 256 x 8

PIC16LF627A 1024 x 14 224 x 8 128 x 8

PIC16LF628A 2048 x 14 224 x 8 128 x 8

PIC16LF648A 4096 x 14 256 x 8 256 x 8

PIC16F627A/628A/648A

DS40044B-page 10 Preliminary  2004 Microchip Technology Inc.

FIGURE 3-1: BLOCK DIAGRAM

Note: Higher order bits are from the Status Register.

Flash

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8-Level Stack

(13-bit)

RAM

File

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR reg

Stat us Re g

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start- up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

PORTA

PORTB

RA4/T0CK1/CMP2

RA5/MCLR/VPP

RB0/INT

Brown-out

Detect

USART

CCP1

Timer0 Timer1 Timer2

RA3/AN3/CMP1

RA2/AN2/VREF

RA1/AN1

RA0/AN0

RB1/RX/DT

RB2/TX/CK

RB3/CCP1

RB4/PGM

RB5

RB6/T1OSO/T1CKI/PGC

RB7/T1OSI/PGD

Low-Voltage

Programming

RA6/OSC2/CLKOUT

RA7/OSC1/CLKIN

VREF

Comparator

Data EEPROM

 2004 Microchip Technology Inc. Preliminary DS40044B-page 11

PIC16F627A/628A/648A

TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION

Name Function Input Type Output Type Description

RA0/AN0 RA0 ST CMOS Bidirectional I/O port

AN0 AN — Analog comparator input

RA1/AN1 RA1 ST CMOS Bidirectional I/O port

AN1 AN — Analog comparator input

RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port

AN2 AN — Analog comparator input

VREF —ANVREF output

RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port

AN3 AN — Analog comparator input

CMP1 — CMO S Comparator 1 output

RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port

T0CKI ST — Timer0 clock input

CMP2 — OD Comparator 2 output

RA5/MCLR/VPP RA5 ST — Input port

MCLR ST — Master cl ear. Wh en co nfigure d as MC LR, t his

pin is an active low Reset to the device.

Voltage on MCLR/VPP must not exceed VDD

during normal devi ce ope rati on.

VPP — — Programming voltage input.

RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectional I/O port

OSC2 — XTAL Oscillator crystal output. Connects to crystal

or resonator in Crystal Oscillator mode.

CLKOUT — CMOS In RC/INTOSC mode, OSC2 pin can output

CLKOUT, which has 1/4 the frequency of

OSC1

RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port

OSC1 XTAL — Oscillator crystal input

CLKIN ST — External clock source input. RC biasing pin.

RB0/INT RB0 TTL CMOS Bidirectional I/O po rt. Can be software

programmed for internal weak pull-up.

INT ST — External interrupt.

RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software

programmed for internal weak pull-up.

RX ST — USART receive pin

DT ST CMOS Sync hronous data I/O.

RB2/TX/CK RB2 TTL CMOS Bidirectional I/O po rt. Can be software

programmed for internal weak pull-up.

TX — CMOS USART transmit pin

CK ST CMOS Synchronous clock I/O.

RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software

programmed for internal weak pull-up.

CCP1 ST CMOS Capture/Compare/PWM I/O

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

PIC16F627A/628A/648A

DS40044B-page 12 Preliminary  2004 Microchip Technology Inc.

RB4/PGM RB4 TTL CMOS Bidirectional I/ O port. Interrupt -on-pin change.

Can be software programmed for internal

weak pull-up.

PGM ST — Low voltage programming input pin. When

low voltage programming is enabled, the

interrupt-on-pin change and weak pull-up

resistor are disabled.

RB5 RB5 TTL CMOS Bidirectional I/ O port. Interrupt-on-pin change.

Can be software programmed for internal

weak pull-up.

RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change.

Can be software programmed for internal

weak pull-up.

T1OSO — XTAL Tim er1 osc illa tor outp ut.

T1CKI ST — Timer1 clock input.

PGC ST — ICSP Programming Clock.

RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. I nterrupt-on-pin change.

Can be software programmed for internal

weak pull-up.

T1OSI XTAL — Timer1 osc il la tor inpu t.

PGD ST CMOS ICSP Data I/O

VSS VSS Powe r — Ground reference for logic and I/O pins

VDD VDD Power — Positive supply for logic and I/O pins

TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION

Name Function Input Type Output Type Description

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

 2004 Microchip Technology Inc. Preliminary DS40044B-page 13

PIC16F627A/628A/648A

3.1 Clocking Scheme/Instruction

Cycle

The clock input (OSC1/CLKIN/RA7 pin) is internally

divided by four to generate four non-overlapping

quadrature clocks namely Q1, Q2, Q3 and Q4. Inter-

nally, the program counter (PC) is incremented every

Q1, the instruction is fetched from the program memory

and latched into the instruction register in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

exe cution flow is shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then tw o cycles are req uired to com plete the ins truction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the ex ecution cycle , the fetched instruction i s latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal

phase

clock

All instru ctions are sing le cycle, except fo r any progra m branches. These ta ke two cycles sinc e the fetch instructio n

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF PORTA, 3 Fetch 4 Flush

Fetch SUB_1 Execute SUB_1

PIC16F627A/628A/648A

DS40044B-page 14 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 15

PIC16F627A/628A/648A

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16F627A/628A/648A has a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. Only the first 1K x 14 (0000h - 03FFh)

for the PIC16F627A, 2K x 14 (0000h - 07FFh) for the

PIC16F628A and 4K x 14 (0000h - 0FFFh) for the

PIC16F648A are physically implemented. Accessing a

location above these boundaries will cause a wrap-

around within the first 1K x 14 space (PIC16F627A), 2K

x 14 space (PIC16F628A) or 4K x 14 space

(PIC16F648A). The Reset vector is at 0000h and the

interrupt vector is at 0004h (Figure 4-1).

FIGURE 4-1: PROGRAM MEMORY MAP

AND STACK

4.2 Data Memory Organiza tion

The data memory (Figure 4-2 and Figure 4-3) is

partitioned into four banks, which contain the General

Purpose Registers (GPR’s) and the Special Function

Registers (SFR). The SFR’s are located in the first 32

locations of each Bank. There are General Purpose

Registers implemented as static RAM in each Bank.

Table 4-1 lists the General Purpose Register available

in each of the four banks.

TABLE 4-1: GENERAL PURPOSE STATIC

RAM REGISTERS

Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are

implemented as common RAM and mapped back to

addresses 70h-7Fh.

Tabl e 4-2 list s how to access the four banks o f register s

via the Status Register bits RP1 and RP0.

TABLE 4-2: ACCESS TO BANKS OF

REGISTERS

4.2. 1 GENERAL PURPOSE REGISTER

FILE

The register file is organized as 224 x 8 in the

PIC16F627A/628A and 256 x 8 in the PIC16F648A.

Each is accessed either directly or indirectly through

the File Select Register (FSR), See Section 4.4 "Indi-

rect Addressing, INDF and FSR Regi sters".

PC<12:0>

000h

0004

0005

03FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interr upt Vector

On-chip Program

Memory

CALL, RETURN

RETFIE, RETLW

Stack Level 2

07FFh

PIC16F627A,

PIC16F628A and

PIC16F648A

On-chip Program

Memory

PIC16F628A and

PIC16F648A

On-chip Program

Memory

PIC16F648A o nly

0FFFh

PIC16F627A/628A PIC16F648A

Bank0 20-7Fh 20-7Fh

Bank1 A0h-FF A0h-FF

Bank2 120h-14Fh, 170h-17Fh 120h-17Fh

Bank3 1F0h-1FFh 1F0h-1FFh

RP1 RP0

Bank0 00

Bank1 01

Bank2 10

Bank3 11

PIC16F627A/628A/648A

DS40044B-page 16 Preliminary  2004 Microchip Technology Inc.

FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A

Indirect addr.(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PIE1

PCON

PR2

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

File

Address

Indirect addr . (1) Indirect addr.(1)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

17Fh 1FFh

Bank 2 Bank 3

Indirect addr.(1)

TMR0 OPTION

RCSTA

TXREG

RCREG

CMCON

TXSTA

SPBRG

VRCON

General

Purpose

1EFh

1F0h

accesses

70h - 7Fh

EFh

F0h

accesses

70h-7Fh

16Fh

170h

accesses

70h-7Fh

80 Bytes

EEDATA

EEADR

EECON1

EECON2(1)

General

Purpose

80 Bytes

General

Purpose

48 Bytes

11Fh

120h

14Fh

150h

6Fh

70h

16 Bytes

PORTB TRISB

1Ch

1Dh

1Eh

 2004 Microchip Technology Inc. Preliminary DS40044B-page 17

PIC16F627A/628A/648A

FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F648A

Indirect addr.(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR

TRISA

TRISB

PCLATH

INTCON

PIE1

PCON

PR2

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

File

Address

Indirect addr . (1) Indirect addr.(1)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

17Fh 1FFh

Bank 2 Bank 3

Indirect addr.(1)

TMR0 OPTION

RCSTA

TXREG

RCREG

CMCON

TXSTA

SPBRG

VRCON

General

Purpose

1EFh

1F0h

accesses

70h - 7Fh

EFh

F0h

accesses

70h-7Fh

16Fh

170h

accesses

70h-7Fh

80 Bytes

EEDATA

EEADR

EECON1

EECON2(1)

General

Purpose

80 Bytes

11Fh

120h

6Fh

70h

16 Bytes

PORTB TRISB

1Ch

1Dh

1Eh

General

Purpose

80 Bytes

PIC16F627A/628A/648A

DS40044B-page 18 Preliminary  2004 Microchip Technology Inc.

4.2.2 SPECIAL FUNCTION REGISTERS

The SFRs are registers used by the CPU and Periph-

eral functions for controlling the desired operation of

the devic e (Table 4-3). These regis ters are st at ic RAM.

The special registers can be classified into two sets

(core and peripheral). The SFRs associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

described in the section of that peripheral feature.

TABLE 4-3: SPECIAL REGISTERS SUMMARY BANK0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Reset(1)

Details

Page

Bank 0

00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28

01h TMR0 Timer0 module’s Register xxxx xxxx 45

02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28

03h STATUS IRP RP1 RP0 TO PD ZDCC

0001 1xxx 22

04h FSR Indirect data memory address pointer xxxx xxxx 28

05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 31

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 36

07h —Unimplemented — —

08h —Unimplemented — —

09h —Unimplemented — —

0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 28

0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24

0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 26

0Dh —Unimplemented — —

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 48

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 48

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 48

11h TMR2 TMR2 module’s register 0000 0000 52

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52

13h —Unimplemented — —

14h —Unimplemented — —

15h CCPR1L Capture/Compare/PWM register (LSB) xxxx xxxx 55

16h CCPR1H Capture/Compare/PWM register (MSB) xxxx xxxx 55

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 55

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 69

19h TXREG USART Transmit data register 0000 0000 76

1Ah RCREG USART Receive data register 0000 0000 79

1Bh —Unimplemented — —

1Ch —Unimplemented — —

1Dh —Unimplemented — —

1Eh —Unimplemented — —

1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 61

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 19
PIC16F627A/628A/648A
TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 Bit 0 Value on 
POR 
Reset(1)
Details 
on 
Page
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical 
register) xxxx xxxx 28
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28
83h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22
84h FSR Indirect data memory address pointer xxxx xxxx 28
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 31
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 36
87h —Unimplemented — —
88h —Unimplemented — —
89h —Unimplemented — —
8Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 28
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IETMR2IETMR1IE0000 -000 25
8Dh —Unimplemented — —
8Eh PCON — — — — OSCF —PORBOR ---- 1-0x 27
8Fh —Unimplemented — —
90h —Unimplemented — —
91h —Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 52
93h —Unimplemented — —
94h —Unimplemented — —
95h —Unimplemented — —
96h —Unimplemented — —
97h —Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 71
99h SPBRG Baud Rate Generator Register 0000 0000 71
9Ah EEDATA EEPROM data register xxxx xxxx 89
9Bh EEADR EEPROM address register xxxx xxxx 90
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 90
9Dh EE CON2 EEPROM control register 2 (not a physical register) ---- ---- 90
9Eh —Unimplemented — —
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 67
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unim-
plemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.

PIC16F627A/628A/648A

DS40044B-page 20 Preliminary  2004 Microchip Technology Inc.

TABLE 4-5: SPECIAL FUNCTION REGISTERS SUMMARY BANK2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Reset(1)

Details

Page

Bank 2

100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28

101h TMR0 Timer0 module’s Register xxxx xxxx 45

102h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28

103h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22

104h FSR Indirect data memory address pointer xxxx xxxx 28

105h —Unimplemented — —

106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 36

107h —Unimplemented — —

108h —Unimplemented — —

109h —Unimplemented — —

10Ah PCLATH — — — Write buffer for upper 5 bits of pr ogram counter ---0 0000 28

10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24

10Ch —Unimplemented — —

10Dh —Unimplemented — —

10Eh —Unimplemented — —

10Fh —Unimplemented — —

110h —Unimplemented — —

111h —Unimplemented — —

112h —Unimplemented — —

113h —Unimplemented — —

114h —Unimplemented — —

115h —Unimplemented — —

116h —Unimplemented — —

117h —Unimplemented — —

118h —Unimplemented — —

119h —Unimplemented — —

11Ah —Unimplemented — —

11Bh —Unimplemented — —

11Ch —Unimplemented — —

11Dh —Unimplemented — —

11Eh —Unimplemented — —

11Fh —Unimplemented — —

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on c ondition, shaded =

unimplemented.

Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 21
PIC16F627A/628A/648A
TABLE 4-6: SPECIAL FUNCTION REGISTERS SUMMARY BANK3
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2  Bit 1 Bit 0 Value on 
POR 
Reset(1)
Details 
on 
Page
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 28
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 23
182h PCL Program Counter's (PC) Least Significant Byte 0000 0000 28
183h STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 22
184h FSR Indirect data memory address pointer xxxx xxxx 28
185h —Unimplemented — —
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 36
187h —Unimplemented — —
188h —Unimplemented — —
189h —Unimplemented — —
18Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 28
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 24
18Ch —Unimplemented — —
18Dh —Unimplemented — —
18Eh —Unimplemented — —
18Fh —Unimplemented — —
190h —Unimplemented — —
191h —Unimplemented — —
192h —Unimplemented — —
193h —Unimplemented — —
194h —Unimplemented — —
195h —Unimplemented — —
196h —Unimplemented — —
197h —Unimplemented — —
198h —Unimplemented — —
199h —Unimplemented — —
19Ah —Unimplemented — —
19Bh —Unimplemented — —
19Ch —Unimplemented — —
19Dh —Unimplemented — —
19Eh —Unimplemented — —
19Fh —Unimplemented — —
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = 
unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.

PIC16F627A/628A/648A

DS40044B-page 22 Preliminary  2004 Microchip Technology Inc.

4.2.2.1 Status Register

The Status Register, shown in Register 4-1, contains

the arithmetic status of the ALU; the Reset status and

the bank select bits for data memory (SRAM).

The Status Register can be the destination for any

instruc tion, like an y other regi ster . If the S t atus Regis ter

is the destination for an instruction that affects the Z,

DC or C bits, then the write to these three bits is dis-

abled. These bits are set or cleared according to the

device logic. Further more, the T O and PD bit s are non-

writable. Therefore, the result of an instruction wi th the

Status Register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper-three

bits and set the Z bit. This leaves the Status Register

as “000uu1uu” (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

S tat usRegiste r because t hese instru ctions do not affec t

any Status bit. For other instructions, not affecting any

Status bits, see the “Instruction Set Summary”.

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)

00 = Bank 0 (00h - 7Fh)

01 = Bank 1 (80h - FFh)

10 = Bank 2 (100h - 17Fh)

11 = Bank 3 (180h - 1FFh)

bit 4 TO: Time out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instruc tions) (for borrow the polarity

is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the Most Significan t bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded wi th either the high or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS40044B-page 23

PIC16F627A/628A/648A

4.2.2.2 OPTION Register

The OPTION register is a readable and writable

the TMR0/WDT prescaler, the external RB0/INT

interrupt, TMR0 and the weak pull-ups on PORTB.

Note: To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT

(PSA = 1). See Section 6.3.1 "Switching

Prescaler Assignment".

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disa bled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Presca ler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F627A/628A/648A

DS40044B-page 24 Preliminary  2004 Microchip Technology Inc.

4.2.2.3 INTCON Register

The INTCON register is a readable and writable

for all i nter rupt so urces excep t the c omp arator modul e.

See Section 4.2.2.4 "PIE1 Register" and

Section 4.2.2.5 "PIR1 Register" for a description of

the comparator enable and flag bits.

Note: Interru pt flag bit s ge t set when an i nterrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all un-maske d interrupts

0 = Disables all inte rrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-maske d peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 reg i ster did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external int errupt o c curred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Chan ge Interrupt Flag bit

1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS40044B-page 25

PIC16F627A/628A/648A

4.2.2.4 PI E1 Regi st er

This register contains interrupt enable bits.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 EEIE: EE Write Complete Interrupt Enable Bit

1 = Enables the EE write complete interrupt

0 = Disables the EE write complete interrupt

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt

0 = Disables the comparator interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit 3 Unimplemented: Re ad as ‘0’

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: T MR1 Ov erfl ow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

DS40044B-page 26 Preliminary  2004 Microchip Technology Inc.

4.2.2.5 PIR1 Register

This register contains interrupt flag bits.

Note: Interru pt fla g bit s get set when an in terru pt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bit s are clear prio r to enab ling

an interrupt.

R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0

EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation has not completed or has not been started

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator output has changed

0 = Comparator output has not changed

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full

0 = The USART receive buffer is empty

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty

0 = The USART transmit buffer is full

bit 3 Unimplemented: Re ad as ‘0’

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occu rred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 reg i ster did not overflow

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS40044B-page 27

PIC16F627A/628A/648A

4.2.2.6 PCON Regi st er

The PCON register contains flag bits to differentiate

between a Power-on Reset, an external MCLR Res et,

WDT Reset or a Brown-out Reset.

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent Resets to see if BOR is

cleared, indicating a brown-out has

occurred. The BOR Status bit is a “don't

care” and is not necessarily predictable if

the brown-out circuit is disabled (by

clearing the BOREN bit in the

Configuration word).

U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-0 R/W-x

— — — — OSCF —PORBOR

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3 OSCF: INTOSC oscillator frequency

1 = 4 MHz typical

0 = 37 kHz typical

bit 2 Unimplemented: Read as ‘0 ’

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (mus t be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-ou t Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

DS40044B-page 28 Preliminary  2004 Microchip Technology Inc.

4.3 PCL and PCLATH

The progra m counter (PC) is 13-bits wide. Th e low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not

directly rea dab le or w ri table and come s fro m PCLATH.

On any Re se t, th e PC is cleared . Fi gure 4-4 shows th e

two situations for loading the PC. The upper example

in Figure 4-4 shows how the PC is lo aded on a write to

PCL (PCLATH<4:0> → PCH). The lower example in

Figure 4-4 shows how the PC is loaded during a CALL

or GOTO instruction (P CLATH<4:3> → PCH).

FIGURE 4-4: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A comput ed GOTO is a ccom pli shed by adding a n offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be ex ercise d if th e t able loca tion c rosse s a PCL

memory boundary (each 256-byte block). Refer to the

application note “Implementing a Table Read” (AN556).

4.3.2 STACK

The PIC16F627A/628A/648A family has an 8-level

deep x 13-bit wide hardware stack (Figure 4-1). The

stac k s p a ce i s no t p art o f eith er pro gram or da t a space

and the stack pointer is not readable or writable. The

PC is PUSHed onto the stack when a CALL instruct ion

is executed or an interrupt cause s a branch. The stack

is POPed in the event of a RETURN, RETLW or a

RETFIE ins truct ion exec ution . PCL ATH is not affec ted

by a PUSH or POP operation.

The st ack operates as a circular buffer . This means that

after the stack has been PUSHed eight times, the ninth

push ov erwrite s the va lue tha t was store d from th e first

push. The tenth push ov erwr i tes the se co nd push (and

so on).

4.4 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physical reg ister . Addr essing

the INDF register will cause indi rect addressing.

Indirect addressing is possible by using the INDF

actually accesses data pointed to by the file select

produce 00h. Writing to the INDF register indirectly

results in a no-operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit

(STATUS<7>), as shown in Figure 4-5.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-1.

EXAMPL E 4-1: Indire ct Addre ssin g

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode < 10:0 >

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions, or the vectoring to an

interr upt add ress.

MOVLW 0x20 ;initialize pointer

MOVWF FSR ;to RAM

NEXT CLRF INDF ;clear INDF register

INCF FSR ;inc pointer

BTFSS FSR,4 ;all done?

GOTO NEXT ;no clear next

;yes continue

 2004 Microchip Technology Inc. Preliminary DS40044B-page 29

PIC16F627A/628A/648A

FIGURE 4-5: DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A

Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.

RAM

Indirect AddressingDirect Addressing

bank select location select

RP1 RP0 6 0

from opcode IRP FSR Register

bank select location select

00 01 10 11 180h

1FFh

00h

7Fh Bank 0 Bank 1 Bank 2 Bank 3

File

Registers

S tatus

PIC16F627A/628A/648A

DS40044B-page 30 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 31

PIC16F627A/628A/648A

5.0 I/O PORTS

The PIC16F627A/628A/648A have two ports, PORTA

and PORTB. Some pins for these I/O ports are

multiplexed with alternate functions for the peripheral

featur es on the devic e. In general , when a periphe ral is

enabled, that pin may not be used as a general

purpose I/O pin.

5.1 IPORTA and TRISA Registers

PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger

input an d an open drai n output. Port R A4 is multipl exed

with the T0C KI clock input. RA5(1) is a Schmitt Trigger

input only and has no output drivers. All other RA port

pins have Schmitt Trigger input levels and full CMOS

output drivers. All pins have data direction bits (TRIS

registers) which can configure these pins as input or

output.

A ‘1’ in the TRISA register puts the corresponding

output driver in a High-impedance mode. A '0' in the

TRISA regi ster puts the contents of the output latch on

the selected pin(s).

Reading the PORTA register reads the status of the

pins whereas writing to it will write to the port latch. All

write op erations are re ad-modify-write op erations. So a

write to a port implies that the port pins are first read,

then this value is modified and written to the port data

latch.

The PORTA pins are multiplexed with comparator and

voltage reference functions. The operation of these

pins are selected by control bits in the CMCON

(comparator control register) register and the VRCON

(voltage reference control register) register. When

selected as a comparator input, these pins will read

as ‘0’s.

TRISA controls the direction of the RA pins, even when

they are being used as comparator inputs. The user

must make sure to keep the pins configured as inputs

when us ing them as comparator inputs.

The RA2 pin will also function as the output for the

voltage reference. When in this mode, the VREF pin is a

very high-impedance output. The user must configure

TRISA<2> bit as an input and use high-impedance

loads.

In one of the Comparator modes defined by the

CMCON register, pins RA3 and RA4 become outputs

of the comparators. The TRISA<4:3> bits must be

cleared to enable outputs to use this function.

EXAMPLE 5- 1: Initializing PORTA

FIGURE 5-1: BLOCK DIAGRAM OF

RA0/AN0:RA1/AN1 PINS

Note 1: RA5 shares function with VPP. When VPP

voltage levels are applied to RA5, the

device wi ll enter Programming mode.

2: On Reset, the TRISA register is set to all

inputs. The digital inputs (RA<3:0>) are

disabled and the comparator inputs are

forced to ground to reduce current

consumption.

3: TRISA<6:7> is overridden by oscillator

configuration. When PORTA<6:7> is

overridden, the data reads ‘0’ and the

TRIS A<6 :7> bits are ignored.

CLRF PORTA ;Initialize PORTA by

;setting

;output data latches

MOVLW 0x07 ;Turn comparators off and

MOVWF CMCON ;enable pins for I/O

;functions

BCF STATUS, RP1

BSF STATUS, RP0;Select Bank1

MOVLW 0x1F ;Value used to initialize

;data direction

MOVWF TRISA ;Set RA<4:0> as inputs

;TRISA<5> always

;read as ‘1’.

;TRISA<7:6>

;depend on oscillator

;mode

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latc h

RD PORTA

Analog

I/O Pi

Input Mode

To Comparator

Schmitt Trigger

Input Buffer

VDD

VSS

TRISA

(CMCON Reg.)

PIC16F627A/628A/648A

DS40044B-page 32 Preliminary  2004 Microchip Technology Inc.

FIGURE 5-2: BLOCK DIAGRAM OF

RA2/VREF PIN

FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3 PIN

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latch

RD PORTA

Analog

RA2 Pi

CK Input Mode

To Comparator

Schmitt Trigger

Input Buffer

VROE

VREF

VDD

VSS

TRISA

(CMCON Reg.)

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latch

RD PORTA

Analog

RA3 Pin

To Comparator

Schmitt Trigger

Input Buffer

Input Mode

Comparator Output

Comparator Mode = 110 VDD

VSS

TRISA

(CMCON R eg. )

(CMCON Reg.)

 2004 Microchip Technology Inc. Preliminary DS40044B-page 33

PIC16F627A/628A/648A

FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI PIN

FIGURE 5-5: BLOCK DIAGRAM OF THE

RA5/MCLR/VPP PIN FIGURE 5-6: BLOCK DIAGRAM OF

RA6/OSC2/CLKOUT PIN

Data

Bus QD

PORTA

TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

Vss

RA4 Pin

TMR0 Clock Input

Schmitt Trigger

Input Buffer

Comparator Output

Comparator Mode = 110

Vss

(CMCON Reg.)

HV Detect

MCLR Filter

RA5/MCLR/VPP

MCLR

Program

MCLRE

VSS

Data

Bus

VSS

PORTA

circuit

mode Schmitt Trigger

Input Buffer

TRISA

(Configu ration Bit)

WR D

PORTA

TRISA

VDD

VSS

CLKOUT(FOSC/4)

(FOSC =

101, 111) (2)

RD PORTA

FOSC =

011, 100, 110 (1)

TRISA

From OSC1 OSC

Circuit

Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.

2: INTOSC with RA6 = CLKOUT or RC with RA6 =

CLKOUT.

Schmitt

Trigger

Input Buffer

Data Latch

TRIS Latch

PIC16F627A/628A/648A

DS40044B-page 34 Preliminary  2004 Microchip Technology Inc.

FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN

Data Bus QD

WR PORTA

WR TRISA

Data Latch

TRIS Latch

RD TRISA

RD PORTA

RA7/OSC1/CLKIN Pin

To Clock Circuits

FOSC = 100, 101(1)

VDD

VSS

Note 1: INTOSC with CLKOUT, and INTOSC with I/O.

Schmitt Trigger

Input Buffer

 2004 Microchip Technology Inc. Preliminary DS40044B-page 35

PIC16F627A/628A/648A

TABLE 5-1: PORTA FUNCTIONS

Name Function Input

Type Output

Type Description

RA0/AN0 RA0 ST CMOS Bidirectional I/O port

AN0 AN — Analog comparator input

RA1/AN1 RA1 ST CMOS Bidirectional I/O port

AN1 AN — Analog comparator input

RA2/AN2/VREF RA2 ST CMOS Bidirectional I/O port

AN2 AN — Analog comparator input

VREF —ANVREF output

RA3/AN3/CMP1 RA3 ST CMOS Bidirectional I/O port

AN3 AN — Analog comparator input

CMP1 — CMOS Comparator 1 output

RA4/T0CKI/CMP2 RA4 ST OD Bidirectional I/O port. Output is open drain type.

T0CKI ST — External clock input for TMR0 or comparator output

CMP2 — OD Comparator 2 output

RA5/MCLR/VPP RA5 ST — Input port

MCLR ST — Master clear. When configured as MCLR, this pin is an

active low Res et to the de vice . Vol tage on MCLR /VPP must

not exceed VDD during normal device operation.

VPP HV — Programming voltage input.

RA6/OSC2/CLKOUT RA6 ST CMOS Bidirectio nal I/O port

OSC2 — XTAL Oscillator crystal output. Connects to crystal reso nator in

Crystal Oscill ator mode.

CLKOUT — CMOS In RC or INTOSC mode. OSC2 pin can output CLKOUT,

which has 1/4 the frequency of OSC1

RA7/OSC1/CLKIN RA7 ST CMOS Bidirectional I/O port

OSC1 XTAL — Oscillator crystal inp ut. Connects to crystal resonator in

Crystal Oscill ator mode.

CLKIN ST — External clock source input. RC biasing pin.

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

PIC16F627A/628A/648A

DS40044B-page 36 Preliminary  2004 Microchip Technology Inc.

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA(1)

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bidirectional port. The

correspo nding da ta direction r egister is TR ISB. A ‘1’ in

the TRISB register puts the corresponding output driver

in a High-impedance mode. A '0' in the TRISB register

puts the contents of the output latch on the selected

pin(s).

PORTB is multiplexed with the external interrupt,

USAR T , CCP module and the TMR1 clock input/output.

The standard port functions and the alternate port

functions are shown in Table 5-3. Alternate port

func tions may overri de TR IS setti ng when enabled.

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operatio ns are read-mo dify-write operat ions. So a wri te

to a port implies that the port pins are first read, then

this val ue i s mo di fied and written to the port da t a l atc h.

Each of the PORTB pins has a weak internal pull-up

(≈200 µA typica l). A singl e control bit can tu rn on all th e

pull-ups. This is done by clearing the RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is configured as an output.

The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB<7:4>, have an interrupt-on-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB<7:4> pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed togeth er to gen erate th e RBIF interrup t (flag

latched in INTCON<0>).

This interrupt can wake the device from Sleep. The

user, in the interrupt service routine, can clear the

inter rupt in the following manne r:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software configurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression. (See AN552)

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

Resets

05h PORTA RA7 RA6 RA5(2) RA4 RA3 RA2 RA1 RA0 xxxx 0000 qqqu 0000

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

9Fh VRCON VREN VROE VRR —VR3 VR2 VR1 VR0 000- 0000 000- 0000

Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unim pl eme nte d

Note 1: Shaded bits are not used by PORTA.

2: MCLRE Configuration Bit sets RA5 functionality.

Note: If a change on the I/O pin should occur

when a read operation is being executed

(start of the Q2 cycle), then the RBIF

interrupt flag may not get set.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 37

PIC16F627A/628A/648A

FIGURE 5-8: BLOCK DIAGRAM OF

RB0/INT PIN FIGURE 5-9: BLOCK DIAGRAM OF

RB1/RX/DT PIN

Data Bus

WR PORTB

WR TRISB

RD PORTB

Data Latch

TRIS Latch

RB0/INT

INT

RD TRISB

RBPU P

VDD

VSS

CK Q

Weak Pull-up

Schmitt

TTL

Input

Buffer

Trigger

Data Latch

TRIS Latch

RD TRISB

WR PORTB

WR TRISB

Schmitt

Trigger

Peripheral OE(1)

Data Bus

SPEN

USART Data Output

USART Receive Input

RBPU VDD

VDD

VSS

Note 1: Peripheral OE (output enable) is only active if

peripheral select is active.

RD PORTB

RX/DT

RB1/

TTL

Input

Buffer

Weak

Pull-up

PIC16F627A/628A/648A

DS40044B-page 38 Preliminary  2004 Microchip Technology Inc.

FIGURE 5-10: BLOCK DIAGRAM OF

RB2/TX/CK PIN FIGURE 5-11: BLOCK DIAGRAM OF

RB3/CCP1 PIN

Data Latch

TRIS Latch

RD TRISB

WR PORTB

WR TRISB

Schmitt

Trigger

Peripheral OE(1)

Data Bus

SPEN

USART TX/CK Output

USART Slave Clock In

RBPU VDD

VDD

VSS

Note 1: Periphe ral OE (output enable) is only active if

peripheral select is active.

RD PORTB

TTL

Input

Buffer

RB2/

TX/CK

Weak

Pull-up

Data Latch

TRIS Latch

RD TRISB

WR PORTB

WR TRISB

Schmitt

Trigger

Peripheral OE(2)

Data Bus

CCP1CON

CCP output

CCP In

RBPU VDD

VDD

VSS

Note 1: Periphe ral OE (output enable) is only active if

peripheral select is active.

RD PORTB

TTL

Input

Buffer

RB3/

CCP1

Weak

Pull-up

 2004 Microchip Technology Inc. Preliminary DS40044B-page 39

PIC16F627A/628A/648A

FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN

Data Latch

TRIS Latch

RD TRISB

RD PORTB

WR PORTB

WR TRISB

Schmitt

Trigger

PGM input

LVP

Data Bus

RB4/PGM

VDD

weak pull-up

From other QD

Set RBIF

RB<7:4> pins

TTL

input

buffer

VDD

VSS

Note: The low voltage program ming disables the interrupt-on-change and the weak pull-ups on RB4.

RBPU

(Configuration Bit)

PIC16F627A/628A/648A

DS40044B-page 40 Preliminary  2004 Microchip Technology Inc.

FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN

Data Bus

WR PORTB

WR TRISB

RD PORTB

Data Latch

TRIS Latch

RB5 pin

TTL

input

buffer

RD TRISB

RBPU P

VDD

weak

pull-up

From other QD

Set RBIF

RB<7:4> pins

VDD

VSS

 2004 Microchip Technology Inc. Preliminary DS40044B-page 41

PIC16F627A/628A/648A

FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN

Data Latch

TRIS Latch

RD TRISB

RD PORTB

WR PORTB

WR TRISB

Schmitt

Trigger

T1OSCEN

Data Bus

RB6/

TMR1 Clock

RBPU VDD

weak pull-up

From RB7

T1OSO

T1CKI

From other QD

Set RBIF

RB<7:4> pins

Serial programming clock

TTL

input

buffer

TMR1 oscillator

VDD

VSS

PIC16F627A/628A/648A

DS40044B-page 42 Preliminary  2004 Microchip Technology Inc.

FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN

Data Latch

TRIS Latch

RD TRISB

RD PORTB

WR PORTB

WR TRISB

T10SCEN

Data Bus

RB7/T1OS

To RB6

RBPU VDD

weak pull-up

TTL

input

buffer

From other QD

Set RBIF

RB<7:4> pins

Serial programming input

Schmitt

Trigger

TMR1 oscillator

VDD

VSS

 2004 Microchip Technology Inc. Preliminary DS40044B-page 43

PIC16F627A/628A/648A

TABLE 5-3: PORTB FUNCTIONS

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB(1)

Name Function Input Type Output

Type Description

RB0/INT RB0 TTL CMOS Bidirectional I/O port. Can be software programmed for

intern al we ak pull-up.

INT ST — External interrupt.

RB1/RX/DT RB1 TTL CMOS Bidirectional I/O port. Can be software programmed for

intern al we ak pull-up.

RX ST — USART Receive Pin

DT ST CMOS Synchrono us data I/O

RB2/TX/CK RB2 TTL CMOS Bidirectional I/O port

TX — CMOS USART Transmit Pin

CK ST CMOS Synchronous Clock I/O. Can be software programmed

for internal weak pull-up.

RB3/CCP1 RB3 TTL CMOS Bidirectional I/O port. Can be software programmed for

intern al we ak pull-up.

CCP1 ST CMOS Capture/Compare/PWM/I/O

RB4/PGM RB4 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change . Can be

software programmed for internal weak pull-up.

PGM ST — Low voltage programming input pin. When low voltage

programmi ng is ena ble d, the int errup t -on -pin chan ge

and weak pull-up resistor are disabled.

RB5 RB5 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be

software programmed for internal weak pull-up.

RB6/T1OSO/T1CKI/

PGC RB6 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be

software programmed for internal weak pull-up.

T1OSO — XTAL Timer1 Oscillator Output

T1CKI ST — Timer1 Clock Input

PGC ST — ICSP Programming Clock

RB7/T1OSI/PGD RB7 TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. Can be

software programmed for internal weak pull-up.

T1OSI XTAL — Timer1 Oscillator Input

PGD ST CMOS ICSP Data I/O

Legend: O = Output CMOS = CMOS Output P = Power

— = Not used I = Input ST = Schmitt Trigger Input

TTL = TTL Input OD = Open Drain Output AN = Analog

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

Resets

06h, 106h PORTB RB7 RB6 RB5 RB4(2) RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRI SB 3 TRISB2 TRISB1 TRISB 0 1111 1111 1111 1111

81h, 181h OPT IO N RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: u = unchanged, x = unknown

Note 1: Shaded bits are not used by PORTB.

2: LVP Configuration Bit sets RB4 functionality.

PIC16F627A/628A/648A

DS40044B-page 44 Preliminary  2004 Microchip Technology Inc.

5.3 I/O Programming Considerations

5.3.1 BIDIREC TION AL I/O PORTS

Any instruction that writes, operates internally as a read

followed by a write operation. The BCF and BSF instru c-

tions, for example, read the register into the CPU,

execute the bit operation and write the result back to

the regist er. Caut ion mus t be used when these ins truc-

tions are applied to a port with both inputs and outputs

defined. For example, a BSF operation on bit5 of

PORTB will cause all eight bits of PORTB to be read

into the CPU. Then the BSF operation takes place on

bit5 and PORTB is written to the output latches. If

another bit of PORTB is used as a bidirectional I/O pin

(e.g., bit 0) and is defined as an input at this time, the

input si gnal present on the pi n it s el f wo uld be rea d in to

the CPU and rewri tten to the dat a latch of this p articular

pin, ov erwriting the previous conte nt. As long as the pin

stays in the Input mode, no problem occurs. However,

if bit 0 is switched into Output mode later on, the con-

tent of t he data latch may now be unknow n.

Reading a port register reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(ex. BCF, BSF , etc .) on a port, the v alue of the po rt pins

is read, the des ired o peratio n is do ne to th is va lue, and

this value is then written to the port latch.

Example 5-2 shows the effect of two sequential read-

modify-write instructions (ex., BCF, BSF, etc.) on an

I/O port.

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to chang e the level o n this pin (“wired -or”, “wired-an d”).

The resulting high output currents may damage the

chip.

EXAMPLE 5-2: RE AD-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

5.3.2 SUCCESSIVE OPERATIONS ON I/O

PORTS

The actu al write to an I/O port happe ns at the e nd of an

instruction cycle, whereas for reading, the data must be

valid a t the beg innin g of the ins tructio n cycle (Figure 5-

16). Therefore, care must be exercised if a write

follow ed by a read operat ion is carried out on the same

I/O port. The sequence of instructions should be such

to allow the pin voltage to stabilize (load dependent)

before the nex t ins truc ti on, w hi ch caus es that fil e to be

read into the CPU, is executed. Otherwise, the

previous state of that pin may be read into the CPU

rather than the new st a te. Whe n in doubt, it is bet ter to

separate these instructions with a NOP or another

instruction not accessing this I/O port.

FIGURE 5-16: SUCCESSIVE I/O OPERATION

;Initial PORT settings:PORTB<7:4> Inputs

; PORTB<3:0> Outputs

;PORTB<7:6> have external pull-up and are

;not connected to other circuitry

;

; PORT latchPORT Pins

---------- ----------

BCF STATUS, RP0 ;

BCF PORTB, 7 ;01pp pppp 11pp pppp

BSF STATUS, RP0 ;

BCF TRISB, 7 ;10pp pppp 11pp pppp

BCF TRISB, 6 ;10pp pppp 10pp pppp

;

;Note that the user may have expected the

;pin values to be 00pp pppp. The 2nd BCF

;caused RB7 to be latched as the pin value

;(High).

Q1 Q2 Q3 Q4

Instruction

fetched

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC + 1

PC PC + 2 PC + 3

MOVWF PORTB

Write to PORTB MOVF PORTB, W

Read to PORTB NOP NOP

TPD

Execute

MOVWF

PORTB

Execute

MOVF

PORTB, W

Port pin

sampled here

Execute

NOP

Note 1: This example shows write to PORTB followed by a read from PORTB.

2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 45

PIC16F627A/628A/648A

6.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Read/Write capabilities

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 6-1 is a simplified block diagram of the Timer0

module. Addition al information is a v ailable in the

PICmicro® Mid - Rang e M C U Fam il y R ef eren ce Ma nual

(DS33023).

Timer mode is selected by clearing the T0CS bit

(OPT ION<5>). In T imer mode, the TMR0 register v alue

will increment every instruction cycle (without

prescaler). If the TMR0 register is written to, the

increment is inhibited for the following two cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

Counter mode is selected by setting the T0CS bit. In

this mod e the TMR0 regist er value wil l increment either

on every rising or falling edge of pin RA4/T0CKI. The

incrementing edge is determined by the source edge

(T0SE) con trol bit (OP TION<4>). Clearing th e T0SE bit

selects the rising edge. Restrictions on the external

clock input are discussed in detail in Section 6.2

"Using Timer0 with External Clock".

The prescaler is shared between the Timer0 module

and the Watchdog Timer. The prescaler assignment is

controlled in software by the control bit PSA

(OPTION<3>). Clearing the PSA bit will assign the

prescaler to Timer0. The prescaler is not readable or

writ ab le. Wh en the prescal er is ass ign ed to th e Timer0

module, prescale value of 1:2, 1:4,..., 1:256 are

selectable. Section 6.3 "Timer0 Prescaler" details

the operation of the pres caler.

6.1 Timer0 Interrupt

Timer0 interrupt is generated when the TMR0 register

timer/c ounter ov erflows from FFh to 00 h. This overfl ow

sets the T0IF bit. Th e interrupt can be masked by c lear-

ing the T0IE bit (INTCON<5>). The T0IF bit

(INTCON<2>) must be cleared in software by the

Timer0 module interrupt service routine before re-

enabling this interrupt. The Timer0 interrupt cannot

wake the processor from Sleep since the timer is shut

off during Sleep.

6.2 Using Timer0 with External Clock

When an external cl ock input i s used for T ime r0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1 EXTE RNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the pre sc ale r outp ut. The synch r on iza tio n

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-1). Therefore, it is ne ce ss ary for T0CKI t o be

high for a t least 2TOSC (and a s ma ll RC d el ay of 2 0 ns )

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical specification of the

desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple-counter must be taken into

accoun t. Therefo re, it is necessary for T0CKI to h ave a

period of at least 4TOSC (and a small RC delay of 4 0 ns)

divided by the prescaler value. The only requirement

on T0C KI hig h and lo w time is that th ey do no t viol ate

the minimum pulse width requirement of 10 ns. Refer to

param ete rs 40, 41 and 42 in the electrical s pec ification

of the desired device. See Table 17-8.

PIC16F627A/628A/648A

DS40044B-page 46 Preliminary  2004 Microchip Technology Inc.

6.3 Timer0 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. A prescaler assignment for the Timer0 module

means that there is no postscaler for the Watchdog

Timer, and vice-versa.

The PSA and PS2:PS0 bit s (OP TION<3:0>) de termine

the prescaler as signment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1,

MOVWF 1, BSF 1, x....etc.) will clear the

prescaler. When assigned to WDT, a CLRWDT in struc-

tion will clear the prescaler along with the Watchdog

Timer. The prescaler is not readable or writable.

FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT

T0CKI

T0SE

FOSC/4

SYNC

CYCLES TMR0 REG

8-TO-1MUX

WATCHDOG

TIMER

PSA

WDT

TIME OUT

PS0 - PS2

PSA

WDT EN ABLE BIT

DATA BUS

SET FL AG BIT T0 IF

ON OVERFLOW

PSA

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option Register.

T0CS

WDT POSTSCALER/

TMR0 PRESCALER

TMR1 Clock Source

 2004 Microchip Technology Inc. Preliminary DS40044B-page 47

PIC16F627A/628A/648A

6.3.1 SWITCHING PRESCALE R

ASSIGNMENT

The prescaler assignment is fully under software

control (i.e., it can be changed “on the fly” during

program execution). Use the instruction sequences

shown in Example 6-1 when changing the prescaler

assignment from Timer0 to WDT, to avoid an

unintended device Reset.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

To change prescaler from the WDT to the Timer0

module, use the se quence shown in Exa mple 6-2. This

preca ution mus t be tak en even if the WDT is dis abled.

EXAMPLE 6-2: CHANGIN G PRESCA LER

(WDT→TIMER0)

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

BCF STATUS, RP0 ;Skip if already in

;Bank 0

CLRWDT ;Clear WDT

CLRF TMR0 ;Clear TMR0 and

;Prescaler

BSF STATUS, RP0 ;Bank 1

MOVLW '00101111’b ;These 3 lines

;(5, 6, 7)

MOVWF OPTION_REG ;are required only

;if desired PS<2:0>

;are

CLRWDT ;000 or 001

MOVLW '00101xxx’b ;Set Postscaler to

MOVWF OPTION_REG ;desired WDT rate

BCF STATUS, RP0 ;Return to Bank 0

CLRWDT ;Clear WDT and

;prescaler

BSF STATUS, RP0

MOVLW b'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source

MOVWF OPTION_REG

BCF STATUS, RP0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

Resets

01h, 101h TMR0 Timer0 module register xxxx xxxx uuuu uuuu

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

81h, 181h OPTION(2) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown

Note 1: Shaded bits are not used by Timer0 module.

2: Option is referred by OPTION_REG in MPLAB®.

PIC16F627A/628A/648A

DS40044B-page 48 Preliminary  2004 Microchip Technology Inc.

7.0 TIMER1 MODULE

The Timer1 module is a 16-bi t timer/c ou nter c ons isting

of two 8-bit registers (TMR1H and TMR1L) which are

readable and writable. The TMR1 register pair

(TMR1H:TMR1L) increments from 0000h to FFFFh

and rolls over to 0000h. The Timer1 Interrupt, if

enabled , is generated on overfl ow of the TMR1 register

pair which latches the interrupt flag bit TMR1IF

(PIR1<0>). This interrupt can be enabled/disabled by

setting /clearing the T imer1 in terrupt enabl e bit TMR1IE

(PIE1<0>).

Timer1 can operate in one of two modes:

•As a timer

•As a counter

The Operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

In Timer mode, the TMR1 register pair value

increments every instruction cycle. In Counter mode, it

increments on every rising edge of the external clock

input.

Timer1 can be enabled/disabled by setting/clearing

control bit TMR 1 ON (T1C O N<0>).

Timer1 also has an internal “Reset input”. This Reset

can be generated by the CCP module (Section 9.0

"Capture/Compare/PWM (CCP) Module").

For the PIC16F627A/628A/648A, when the Timer1

oscill ator is enabl ed (T1OSCEN is se t), the RB7/T1OS I

and RB6/T1OSO/T1CKI pins become inputs. That is,

the TRISB<7:6> value is ignored.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7-6 Unimplemented: Re ad as ‘0’

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Tim er1 Os ci ll ator Enable Control bit

1 = Oscillator is enabled

0 = Oscillator is shut off(1)

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RB6/T1OSO/T1CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS40044B-page 49

PIC16F627A/628A/648A

7.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is

always in sync.

7.2 Timer 1 Operation in Sync hronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mode th e TMR 1 re gis ter pair valu e i ncrem ents on

every rising edge of clock input on pin RB7/T1OSI

when bit T1OSCEN is set or pin RB6/T1OSO/T1CKI

when bi t T1OSCEN is cleared.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The

prescaler stage is an asynchronous ripple-counter.

In this configuration, during Sleep mode, the TMR1

external clock is present, since the synchronization

circu it is shu t off. The p rescal er howeve r will cont inue

to increment.

7.2. 1 EXTERNAL CLOCK INPU T TIMING

FOR SYNCHRONIZED COUNTER

MODE

When an external clock input is used for Timer1 in

synchronized Counter mode, it must meet certain

requirem ent s. The exte rnal clo ck requ iremen t is due to

internal phase clock (Tosc) synchro nization. Also, the re

is a delay in the actual incrementing of the TMR1

When the prescaler is 1:1, the external clock input is

the same as the pre sc ale r outp ut. The synch r on iza tio n

of T1CKI with the internal phase clocks is accom-

plishe d by sampli ng the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necessary for T1CKI to be high for at least 2Tosc (and

a small RC delay of 20 ns) and low for at least 2Tosc

(and a small RC dela y of 20 ns ). Refer to the app rop r i-

ate electrical specifications, parameters 45, 46, and 47.

When a prescaler other than 1:1 is used, the external

clock input is divided by the asynchronous ripple-

counter type prescaler so that the prescaler output is

symmetrical. In order for the external clock to meet the

sampling requirement, the ripple-counter must be

ta ken into accoun t. Therefore, it i s necessary for T1CKI

to have a period of at least 4Tosc (and a small RC delay

of 40 ns) divided by the prescaler value. The only

requirem ent on T1CK I high and l ow time is that th ey do

not viol ate the minimu m pulse wid th requirem ents of 10

ns). Refer to the appropriate electrical specifications,

parameters 45, 46, and 47.

FIGURE 7-1: TIMER1 BLOCK DIAGRAM

TMR1H TMR1L

T1OSC T1SYNC

TMR1CST1CKPS1:T1CKPS0 Sleep Input

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR1ON

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

RB6/T1OSO/T1CKI

RB7/T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

Set flag bit

TMR1IF on

Overflow TMR1

PIC16F627A/628A/648A

DS40044B-page 50 Preliminary  2004 Microchip Technology Inc.

7.3 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the exte rnal

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in soft-

ware are ne eded to read/write th e timer (Section 7.3.2

"Reading and Writing Timer1 in Asynchronous

Counter Mode").

7.3.1 EXTERNAL CLOCK INPUT TIMING

WITH UNSYNCHRONIZED CLOCK

If control bit T1SYNC is set, the timer will increment

comple tely as ynch ronous ly. The input cloc k must me et

certain minimum high an d low time requirements. Refer

to Table 17-8 in the Electrical Specifications Section,

timing parameters 45, 46, and 47.

7.3.2 READING AND WRITING T IMER1 IN

ASYNCHRONOUS COUNTER

MODE

Readi ng the TMR1H or TMR 1L registe r while the timer

is running, from an external asynchronous clock, will

produce a valid read (taken care of in hardware).

However , the user should keep in mind that reading the

16-bit timer in two 8-bit values itself poses certain

problems since the timer may overflow between the

reads.

For write s, it is re commend ed that the us er simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers

while the register is incrementing. This may pro duce an

unpredictable value in the timer registe r.

Reading the 16-bit value requires some care.

Example 7-1 is an example routine to read the 16-bit

timer value. This is useful if the timer cannot be

stopped.

EXAMPLE 7-1: READING A 16-BIT FREE-

RUNNING TIMER

Note: In Asynchronous Counter mode, Timer1

cannot be use d as a ti me- bas e for ca ptu r e

or compare operations.

; All interrupts are disabled

MOVF TMR1H, W ;Read high byte

MOVWF TMPH ;

MOVF TMR1L, W ;Read low byte

MOVWF TMPL ;

MOVF TMR1H, W ;Read high byte

SUBWF TMPH, W ;Sub 1st read with

;2nd read

BTFSC STATUS,Z ;Is result = 0

GOTO CONTINUE ;Good 16-bit read

;

; TMR1L may have rolled over between the

; read of the high and low bytes. Reading

; the high and low bytes now will read a good

; value.

;MOVF TMR1H, W ;Read high byte

MOVWF TMPH ;

MOVF TMR1L, W ;Read low byte

MOVWF TMPL ;

; Re-enable the Interrupts (if required)

CONTINUE ;Continue with your

;code

 2004 Microchip Technology Inc. Preliminary DS40044B-page 51

PIC16F627A/628A/648A

7.4 Timer1 Oscillator

A cryst al oscillator circuit is built in between pin s T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). It will

continu e to run du ring Slee p. It is pri maril y inten ded for

a 32.768 kHz watch crystal. Table 7-1 shows the

capacitor selection for the Timer1 oscillator.

The user m us t pro vi de a sof tware time delay to ensu re

proper oscillator start-up.

TABLE 7-1: CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

7.5 Resetting Timer1 Using a CCP

Trigger Output

If the CCP1 module is configured in Compare mode to

generate a “special event trigger” (CCP1M3:CCP1M0

= 1011), this signal will Reset Timer1.

Timer1 must be configured for either timer or synchro-

nized Counter mode to take advantage of th is feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of operation, the CCPRxH:CCPRxL

registers pair effectively becomes the period register

for Timer1.

7.6 Resetting Timer1 Register Pair

(TMR1H, TMR1L)

TMR1H an d TMR1 L regist ers are not reset to 00h on a

POR or any other Reset except by the CCP1 special

event triggers.

T1CON re gister is rese t to 00h on a Pow er-on Rese t or

a Brown-out Reset, which shuts off the timer and

leaves a 1:1 pres cale. In all other Resets, the register

is unaffected.

7.7 Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Freq C1 C2

32.768 kHz 15 pF 15 pF

These values are for design guidance only.

Consult AN826 (DS00826) for furthe r information

on Crystal/Capacitor Selection.

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all othe r

Resets

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.

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DS40044B-page 52 Preliminary  2004 Microchip Technology Inc.

8.0 TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a

postscaler. It can be used as the PWM time-base for

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

Reset.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits

T2CKPS1:T2CKPS0 (T2CON<1: 0>).

The Timer2 module has an 8-bit period register PR2.

The TMR2 register value increments from 00h until it

matche s t he PR 2 re gis ter value and t hen res ets to 00h

on the next increment cycle. The PR2 register is a

readable and writable register. The PR2 register is

initialized to FFh upon Reset.

The match output of Timer2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a Timer2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

Timer2 can be shut off by cl eari ng cont rol bit T MR2ON

(T2CON<2 >) to minimize power consumption.

8.1 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset, or Brown-out Reset)

The TMR2 register is not cleared when T2CON is

written.

8.2 TMR2 Output

The TMR2 output (before the postscaler) is fed to the

Synchron ous Seria l Port m odu le whi ch op tio nal ly use s

it to generate shift clock.

FIGURE 8-1: TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets flag

TMR2 reg

output

Reset

Postscaler

Prescaler

PR2 reg

FOSC/

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

to T2CKPS<1:0>

TOUTPS<3:0>

 2004 Microchip Technology Inc. Preliminary DS40044B-page 53

PIC16F627A/628A/648A

TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

bit 7 Unimplemented: Re ad as ‘0’

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postsc ale Value

0001 = 1:2 Postsc ale Value

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale S elect bits

00 = 1:1 Prescaler Value

01 = 1:4 Prescaler Value

1x = 1:16 Prescaler Value

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

11h TMR2 Timer2 module’s register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

92h PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.

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NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 55

PIC16F627A/628A/648A

9.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

The CCP (C ap ture /Com p a r e/PW M) m od ule co nt ai ns a

16-bit register which can operate as a 16-bit capture

master/slave Duty Cycle register. Table 9-1 shows the

timer resources of the CCP module modes.

CCP1 Mo dul e

Capture/Compare/PWM Register1 (CCPR1) is

comprised of two 8-bit registers: CCPR1L (low byte)

and CCPR1H (high byte). The CCP1CON register

controls the operation of CCP1. All are readable and

writable.

Additional information on the CCP module is available

in the PICmicro® Mid-Range Reference Manual

(DS33023).

TABLE 9-1: CCP MODE - TIMER

RESOURCE

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1

Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0 ’

bit 5-4 CCP1X:CCP1Y: PWM Least Significant bi ts

Capture Mode: Unused

Compare Mode: Unused

PWM Mode: Th ese bit s are the tw o LSbs of the PWM duty cycl e. The ei ght MSbs are found in

CCPRxL.

bit 3-0 CCP1M3:CCP1M0: CCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP1 module)

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mo de, every 16th rising edge

1000 = Compare mode, set output on match (CCP1IF bit is set)

1001 = Compare mode, clear output on match (CCP1IF bit is set)

1010 = Compare mode, ge nera te s oft wa re i nter rupt on match (CCP1I F bi t is se t, CC P1 pi n i s

unaffected)

1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1

11xx = PWM mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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DS40044B-page 56 Preliminary  2004 Microchip Technology Inc.

9.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit val ue of the TMR1 register when an event occurs

on pin RB3/CCP1. An event is defined as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set. It must

be cleared in software. If another capture occurs before

the value in register CCPR1 is read, the old captured

value wi ll be los t.

9.1.1 CCP PIN CONFIGURATION

In Capture mode, the RB3/CCP1 pin should be config-

ured as an input by setting the TRISB<3> bit.

FIGURE 9-1: CAPTURE MODE

OPERATION BLOCK

DIAGRAM

9.1.2 TIMER1 MODE SELECTION

T imer1 mus t be runnin g in T imer mode or synch ronized

Coun ter mod e for t he CCP modul e to us e the cap ture

feature. In Asynchronous Counter mode, the capture

operation may not work.

9.1.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF following any such

change in Operating mode.

9.1.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. This means that any

Reset will clear the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore the first capture may be from

a non-zero prescaler. Example 9-1 shows the recom-

mended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 9-1: CHANGIN G BETWEEN

CAPTURE PRESCALERS

9.2 Compare Mode

In Compare mode, the 16-bit CCPR 1 register value is

constantly compared against the TMR1 register pair

value. Whe n a match occurs, the R B3/C CP 1 pin is:

• Driven High

•Driven Low

• Remains Unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 9-2: COMPARE MODE

OPERATION BLOCK

DIAGRAM

Note: If the RB3/CCP1 is configured as an

output, a write to the port can cause a

capture co ndition.

CCPR1H CCPR1L

TMR1H TMR1L

Set flag bit CCP1IF

(PIR1<2>)

Capture

Enable

Q’s CCP1CON<3:0>

RB3/CCP1

Prescaler

³ 1, 4, 16

and

edge detect

CLRF CCP1CON ;Turn CCP module off

MOVLW NEW_CAPT_PS;Load the W reg with

; the new prescaler

; mode value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

ROutput

Logic

Set flag bit CCP1IF

(PIR1<2>)

match

RB3/CCP1

TRISB<3> CCP1CON<3:0>

Mode Select

Output Enable

Note: Special event trigger will reset Timer1, but not

set interrupt flag bit TMR1IF (PIR1<0>).

 2004 Microchip Technology Inc. Preliminary DS40044B-page 57

PIC16F627A/628A/648A

9.2.1 CCP PIN CONFIGURATION

The user must configure the RB3/CCP1 pin as an

output by clea ring the TRISB<3> bit.

9.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

9.2.3 SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not af fected. On ly a CCP interrupt is generated (if

enabled).

9.2.4 SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 re giste r pai r. Thi s al lows the CC PR1 r eg ist er to

ef fectively b e a 16-bit progra mmable pe riod registe r for

Timer1.

TABLE 9-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Note: Clearing the CCP1CON register will force

the RB3 /CCP1 comp are o utput latch t o the

default l ow le ve l. Th is is n ot th e da t a l atc h.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IFTMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

86h, 186h T RISB PORTB Data Direction Register 1111 1111 1111 1111

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h CCPR 1L C apture/ Compare/PW M registe r1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR 1H Capt ure/ Compare/PW M registe r1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.

PIC16F627A/628A/648A

DS40044B-page 58 Preliminary  2004 Microchip Technology Inc.

9.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pi n is multiplexed with the PORTB da ta latch,

the TRISB<3> bit must be cleared to make the CCP1

pin an output.

Figure 9-3 shows a simplified block diagram of the

CCP module in PWM mo de.

For a st ep by step pr ocedure on h ow to set up the CCP

module for PWM operation, see Section 9.3.3 "Set-Up

for PWM Operatio n".

FIGURE 9-3: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 9-4) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(frequenc y = 1/peri od).

FIGURE 9-4: PWM OUTPUT

9.3.1 PWM PE RIOD

The PWM period is specified by writing to the PR2

following formula:

PWM frequency is defined as 1 / [PWM pe riod].

When TM R2 is equal to PR2, t he following three event s

occur on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from C CPR1L into

CCPR1H

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTB I/O data

latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty cycle registers CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISB<3>

RB3/CCP

Note 1: 8-bit timer is concatenated with 2-bit internal Q

clock or 2 bits of the prescaler to create 10-bit

time-base.

Note: The Timer2 pos t sc al er (s ee Secti on 8.0) is

not used in the determination of the PWM

frequenc y . T he posts caler coul d be used to

have a servo update rate at a different

frequency than the PWM output.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

PWM period PR2()1+[]4 ⋅⋅= Tosc TMR2 prescale⋅value

 2004 Microchip Technology Inc. Preliminary DS40044B-page 59

PIC16F627A/628A/648A

9.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available: the CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

CCPR1L and CC P1CON <5:4> c an be wri tten to a t an y

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycl e. This do uble

buffering is essential f or glitch less PWM operat ion.

When the CCPR1H and 2-bit latch match TMR2

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM

frequency:

For an example PWM period and duty cycle

calculation, see the PICmicro® Mid-Range Reference

Manual (DS33023).

9.3.3 SET-UP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISB<3> bit .

4. Set the TMR2 pres cale value and enable Timer2

by writing to T2CON.

5. Config ure the CCP1 module for PWM opera tion.

TABLE 9-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

TABLE 9-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

(CCPR1L:CCP1CON<5:4>) Tosc TMR2 pres cale⋅⋅

value

PWM d uty cycle =

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be

cleared.

Resolution log Fosc

Fpwm TMR2 Prescaler×

-------------------------------------------------------------





log(2)

--------------------------------------------------------------------------- bits=

PWM

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17

Maximum Resolution (bits) 10 10 10 8 7 6.5

Addr e s s Name Bit 7 Bit 6 Bit 5 Bit 4 Bi t 3 Bit 2 Bit 1 Bi t 0 Value on

POR

Value on

all other

Resets

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111

11h TMR2 Timer2 module’s register 0000 0000 0000 0000

92h PR2 Timer2 module’s period register 1111 1111 1111 1111

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 uuuu uuuu

15h CCPR1L Capture/Compare/PW M regis ter1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.

PIC16F627A/628A/648A

DS40044B-page 60 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 61

PIC16F627A/628A/648A

10.0 COMPARATOR MODULE

The Comparator module contains two analog

comparators. The inputs to the comparators are

multiplexed wi th the RA0 through RA3 pins . The on-chip

Voltage Reference (Section 11.0 "Voltage Reference

Module") can also be an input to the co mp arators.

The CM CON regis ter, sho wn in Registe r 10-1, cont rols

the comparator input and output multiplexers. A block

diagram of the comparator is shown in Figure 10-1.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

bit 7 C2OUT: Comparator 2 Outp ut

When C2INV = 0:

1 = C2 VIN+ > C2 VIN-

0 = C2 VIN+ < C2 VIN-

When C2INV = 1:

1 = C2 VIN+ < C2 VIN-

0 = C2 VIN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Outp ut

When C1INV = 0:

1 = C1 VIN+ > C1 VIN-

0 = C1 VIN+ < C1 VIN-

When C1INV = 1:

1 = C1 VIN+ < C1 VIN-

0 = C1 VIN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion

1 = C2 Output inverted

0 = C2 Output not inverted

bit 4 C1INV: Comparator 1 Output Inversion

1 = C1 Output inverted

0 = C1 Output not inverted

bit 3 CIS: Comparator Input Swit ch

When CM2:CM0: = 001

Then:

1 = C1 VIN- connects to RA3

0 = C1 VIN- connects to RA0

When CM2:CM0 = 010

Then:

1 = C1 VIN- connects to RA3

C2 VIN- connects to RA2

0 = C1 VIN- connects to RA0

C2 VIN- connects to RA1

bit 2-0 CM2:CM0: Comparator Mode

Figure 10-1 shows the Comparator modes and CM2:CM0 bit settings

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

DS40044B-page 62 Preliminary  2004 Microchip Technology Inc.

10.1 Comparator Configuration

There are eight modes of operation for the

comparators. The CMCON register is used to select

the mode. Figure 10-1 shows the eight possible

modes . Th e TRI SA re gist er co ntr ols t he d ata di rect ion

of the comparato r pins for each mode.

If the Comparator mode is changed, the comparator

output level may not be valid for the specified mode

change delay shown in Table 17-2.

FIGURE 10-1: COMPARATOR I/O OPERATING MODES

Note 1: Compa rator in terrupts should b e disable d

during a Comparator mode change,

otherwise a false interrupt may occur.

2: Comparators can have an inverted

output. See Figure 10-3.

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Comparators Reset (POR Default Value)

CM2:CM0 = 000

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Two Independent Comparators

CM2:CM0 = 100

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Two Common Reference Comparators

CM2:CM0 = 011

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1 Off (Read as '0')

One Independent Comparator

CM2:CM0 = 101

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

VIN-

VIN+Off (Read as '0')

Comparators Off

CM2:CM0 = 111

VIN-

VIN+Off (Read as '0')

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Four Inputs M u ltiplexed to Two Comparators

CM2:CM0 = 010

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

From VREF

CIS = 0

CIS = 1

CIS = 0

CIS = 1

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Two Common Reference Comparators with Outputs

CM2:CM0 = 110

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

Open Drain

A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.

RA4/T0CKI/CMP2

RA0/AN0 VIN-

VIN+

RA3/AN3/CMP1

Three Inputs Multiplexed to Two Comparators

CM2:CM0 = 001

RA1/AN1 VIN-

VIN+

RA2/AN2/VREF

CIS = 0

CIS = 1

VSS

RA0/AN0

RA3/AN3/CMP1

RA1/AN1

RA2/AN2/VREF

Module

C1VOUT

C2VOUT

C1VOUT

C2VOUT

Off (Read as '0')

C2VOUT

C1VOUT

C2VOUT

C1VOUT

C2VOUT

C1VOUT

C2VOUT

 2004 Microchip Technology Inc. Preliminary DS40044B-page 63

PIC16F627A/628A/648A

The code example in Example 10-1 depicts the steps

required t o configur e the Compara tor module. RA3 an d

RA4 are confi gured a s digi tal outpu t. RA0 and RA 1 are

configu r ed as the V- inp ut s and RA 2 as the V+ input to

both co mparators.

EXAMPLE 10- 1: INITIALIZI NG

COMPARATOR MODULE

10.2 Comparator Operation

A singl e com pa rator i s sho wn i n Fig ure 10-2 alon g wi th

the relationship between the analog input levels and

the digit al ou tput. When the an alog input a t VIN+ is less

than the analog input VIN-, the output o f the comp arator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 10-2 represent

the uncertainty due to input offsets and response time.

See Table 17-2 for Common Mode Voltage.

10.3 Comparator Reference

An external or internal reference signal may be used

depending on the comparator Operating mode. The

analog s ign al that i s pre se nt at V IN- is compare d to th e

signal at VIN+, and the digital output of the comparator

is adjusted accordingly (Figure 10 -2).

FIGURE 10-2: SINGLE COMPARATOR

10.3.1 EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

Comparator module can be configured to have the

comparators operate from the same or different

reference sources. However, threshold detector

applications may require the same reference. The

reference signal must be between VSS and VDD, and

can be applied to either pin of the comparator(s).

10.3.2 INTERNAL REFERENCE SIGNAL

The Comparator module also allows the selectio n of

an internally generated voltage reference for the

comparators. Section 11.0 "Voltage Reference

Module", contains a detailed description of the

Voltage Referenc e Module that provides this signal.

The internal ref erence si gnal is used when the com-

parators are in mode CM<2:0>=010 (Figure 10-1). In

this mode, the internal voltage reference is applied to

the VIN+ pin of both comparator s.

10.4 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comp arator output is to have a val id level. If the int ernal

reference is changed, the maximum delay of the inter-

nal voltage reference must be considered when using

the comparator outputs. Otherwise, the maximum

delay of the comparators should be used (Table 17-2).

FLAG_REG EQU 0X20

CLRF FLAG_REG ;Init flag register

CLRF PORTA ;Init PORTA

MOVF CMCON, W ;Load comparator bits

ANDLW 0xC0 ;Mask comparator bits

IORWF FLAG_REG,F ;Store bits in flag register

MOVLW 0x03 ;Init comparator mode

MOVWF CMCON ;CM<2:0> = 011

BSF STATUS,RP0 ;Select Bank1

MOVLW 0x07 ;Initialize data direction

MOVWF TRISA ;Set RA<2:0> as inputs

;RA<4:3> as outputs

;TRISA<7:5> always read ‘0’

BCF STATUS,RP0 ;Select Bank 0

CALL DELAY10 ;10µs delay

MOVF CMCON,F ;Read CMCON to end change

;condition

BCF PIR1,CMIF ;Clear pending interrupts

BSF STATUS,RP0 ;Select Bank 1

BSF PIE1,CMIE ;Enable comparator interrupts

BCF STATUS,RP0 ;Select Bank 0

BSF INTCON,PEIE ;Enable peripheral interrupts

BSF INTCON,GIE ;Global interrupt enable

–

Vin+

Vin- Result

Result

VIN-

VIN+

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DS40044B-page 64 Preliminary  2004 Microchip Technology Inc.

10.5 Comparator Outputs

The comparator outputs are read through the CMCON

output s may al so be dire ctly output to the RA3 a nd RA4

I/O pins. When t he CM<2 :0> = 110 or 00 1, multi plexors

in the output path of t he RA3 and RA4/T 0CK1 pins will

switch and the out put of each pin will be the unsynchro-

nized output of the comparator . The uncertainty of each

of the comparators is rela ted to the inp ut offset volt ag e

and the response time given in the specifications.

Figure 10-3 shows the comparator output block

diagram.

The TRISA bits will still function as an output enable/

disable for the RA3 and RA4/T0CK1 pins while in this

mode.

FIGURE 10-3: MODIFIE D COMPARATOR OUTPUT BLOCK DIAGRAM

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert an analog input, according to the

Schmitt Trigger input specification.

2: Analog le vels on any pin that is defined as

a digital input may cause the input buffer

to consume more current than is

specified.

To RA3 or RA4/T0CK1 pin

Set CMIF bit DQ

Reset

From other Comparator

To Data Bus CnVOUT

CnINV

RD CMCON

CMCON<7:6> Q3

 2004 Microchip Technology Inc. Preliminary DS40044B-page 65

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10.6 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

stat us of the out put bits, as rea d from CMCON<7:6> , to

determine the actual change that has occurred. The

CMIF bit, PIR1<6>, is the comparator interrupt flag.

The C MIF bi t mu st be R eset by cl earin g ‘0 ’. Si nce it is

also po ssibl e to write a ‘1 ’ to this reg ister, a s imula ted

interrupt may be initiated.

The CMIE bit (PIE1<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit must also be set. If any of these

bits are clear, the interrupt is not enabled, though the

CMIF bit wil l stil l be se t if an inter r upt co nd itio n occ urs .

The us er, in th e in te r ru pt se rvi c e r o uti ne , ca n clea r t he

inter rupt in the fol lowi ng man ne r :

a) Any write or read of CMCON. This will end the

mismatch condition.

b) Clear flag bit CMIF.

A mismatc h co ndi tio n will co nti nue to set fla g bit CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit CMIF to be cleared.

10.7 Comparator Operation During

Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional if enabled. This interrupt will

wake-up the device from Sleep mode when enabled.

While the comparator is powered-up, higher Sleep

currents than shown in the power-down current

specification will occur. Each comparator that is

operational will consume additional current as shown in

the comparator specifications. To minimize power

consumption while in Sleep mode, turn off the

comp ara tors, C M <2: 0> = 111, before ente ring Sle ep. If

the device wakes up from Sleep, the contents of the

CMCON register are not affected.

10.8 Effects of a Reset

A device Reset forces the CMCON register to its Reset

state. This forces the Comparator module to be in the

comparator Reset mode, CM2:CM0 = 000. This

ensures that all potential inputs are analog inputs.

Device current is minimized when analog inputs are

present at Reset time. The comparators will be

powered-down during the Reset interval.

10.9 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 10-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The an alo g i npu t the r efo re, m us t b e b etween

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum source impedance of 10 kΩ is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR1<6>)

interrupt flag may not get set.

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DS40044B-page 66 Preliminary  2004 Microchip Technology Inc.

FIGURE 10-4: ANALOG INPUT MODE

TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

All Other

Resets

1Fh CMCON C2OUT C1OUT C2INV C1NV CIS CM2 CM1 CM0 0000 0000 0000 0000

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’

RS < 10 K

AIN CPIN

5pF

VDD

VT = 0.6V

RIC

ILEAKAGE

±500 nA

VSS

Legend CPIN = Input Capacitanc e

VT= Threshold Voltage

ILEAKAGE = Leakage Current At The Pin

RIC = Interconnect Resistance

RS= Source Impedance

VA = Analog Voltage

 2004 Microchip Technology Inc. Preliminary DS40044B-page 67

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11.0 VOLTAGE REFERENCE

MODULE

The Voltage Reference is a 16-tap resistor ladder

network that provides a selectable voltage reference.

The resis tor ladder is segment ed to provide two range s

of VREF values and has a power-down function to

conserve power when the reference is not being used.

The VRCON register controls the operation of the

reference as shown in Figure 11-1. The block diagram

is given in Figure 11-1.

11.1 Voltage Reference Configuration

The Voltage Reference can output 16 distinct voltage

levels for each range.

The equations used to calculate the output of the

Voltage Reference are as follows :

if VRR = 1:

if VRR = 0:

The setting time of the Voltage Reference must be

considered when changing the VREF output

(Table 17-3). Example 11-1 demonstrates how Voltage

Referenc e is configured for an output voltage of 1.25V

with VDD = 5.0V.

FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM

VREF VR<3:0>

----------------------VDD×=

VREF VDD 1

---





VR<3:0>

----------------------

DD×=

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

VREN VROE VRR —VR3VR2VR1VR0

bit 7 bit 0

bit 7 VREN: VREF Enable

1 = VREF circ uit powe r ed on

0 = VREF circuit powered down, no IDD drain

bit 6 VROE: VREF Output Enable

1 = VREF is output on RA2 pin

0 = VREF is disconnected from RA2 pin

bit 5 VRR: VREF Rang e sele cti on

1 = Low Range

0 = High Range

bit 4 Unimplemented: Read as ‘0’

bit 3-0 VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15

When VRR = 1: VREF = (VR<3:0>/ 24) * VDD

When VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: R is defined in Table 17-3.

0(From VRCON<3:0>)

16-1 Analog Mux

8R RRRR

REN

REF

16 Stages

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DS40044B-page 68 Preliminary  2004 Microchip Technology Inc.

EXAMPLE 11-1: VOLTA GE REFERENCE

CONFIGURATION

11.2 Voltage Reference Accuracy/Error

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figur e 1 1- 1) keep V REF from approach ing VSS or VDD.

The Voltage Reference is VDD derived and therefore,

the VREF output changes with fluctuations in VDD. The

tested absolute accuracy of the V oltage Reference can

be found in Table 17-3.

11.3 Operation During Sleep

When the device wakes up from Sleep through an

inter rupt or a Watchdo g Time r tim e o ut, the con ten ts of

the VRCON register are not affected. To minimize

current consumption in Sleep mode, the Voltage

Reference should be disable d.

11.4 Effects of a Reset

A device Reset disables the Voltage Reference by

clearing bit VREN (VRCON<7>). This Reset also

discon nects the referenc e from the RA2 p in by cle aring

bit VROE (VRCON<6>) and selects the high voltage

range by clearing bit VRR (VRCON<5>). The VREF

value select bits, VRCON<3:0>, are also cleared.

11.5 Connection Considerations

The Voltage Reference Module operates

indepen dently o f the com parato r module. The outp ut of

the reference generator may be connected to the RA2

pin if the TRISA<2> bit is set and the VROE bit,

VRCON<6>, is set. Enabling the Voltage Reference

output on to the RA2 pi n with an i nput signal pres ent will

increase current consumption. Connecting RA2 as a

digital output with VREF enabled will also increase

current co nsumption.

The RA2 pin can be used as a simple D/A output with

limited drive capability. Due to the limited drive

capa bility, a buffer must be used in co njunction wit h the

Voltage Reference output for external connections to

VREF. Figure 11-2 shows an example buffering

technique.

FIGURE 11-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

MOVLW 0x02 ;4 Inputs Muxed

MOVWF CMCON ;to 2 comps.

BSF STATUS,RP0 ;go to Bank 1

MOVLW 0x07 ;RA3-RA0 are

MOVWF TRISA ;outputs

MOVLW 0xA6 ;enable VREF

MOVWF VRCON ;low range set VR<3:0>=6

BCF STATUS,RP0 ;go to Bank 0

CALL DELAY10 ;10µs delay

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value On

POR

Value On

All Other

Resets

9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000

1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000

85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: — = Unimplemented, read as ‘0’.

Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.

VREF

Module

R(1)

Voltage

Reference

Output

Impedance

RA2

VREF Output

Opamp

 2004 Microchip Technology Inc. Preliminary DS40044B-page 69

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12.0 UNIVERSAL SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

MODULE

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) is also known as a Serial

Communications Interface or SCI. The USART can be

configured as a full-duplex asynchronous system that

can comm unicate with peripheral devices such as C RT

terminals and personal computers, or it can be config-

ured as a half-duplex synchronous system that can

communicate with periphera l devices such as A/D or D/

A integrated circuits, Serial EEPROMs, etc.

The USART can be configured in the foll owing modes:

• Asynchronous (full-duplex)

• Synchronous - Master (half-duplex)

• Synchronous - Slave (half-duplex)

Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have to

be set in order to configure pins RB2/TX/CK and RB1/

RX/DT as the Universal Synchronous Asynchronous

Receiver Transmitter.

Receive Status and Control Register (RCSTA).

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

bit 7 bit 0

bit 7 CSRC: Cloc k Source Sele ct bit

Asynchronous mode

Don’t care

Synchronous mode

1 = Master mode (Clock generated internally from BRG)

0 = Slave mode (Clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Tr ansmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: USART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 Unimplemented: Read as ‘0’

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode

1 = High speed

0 = Low speed

Synchronous mode

Unused in this mode

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of transmit data. Can be parity bit.

Note: SREN/CREN overrides TXEN in SYNC mode .

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

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DS40044B-page 70 Preliminary  2004 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADEN FERR OERR RX9D

bit 7 bit 0

bit 7 SPEN: Seri al Port Enable bit

(Configures RB1/RX/DT and RB2/TX/CK pin s as serial port pin s when bits TRISB<2:1 > are set)

1 = Serial port enabled

0 = Serial port disabled

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode - master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - slave:

Unused in this mode

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables con t in uou s re c eiv e

0 = Disables continuous receive

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, en able interrupt and load of the receive buffer when RSR<8>

is set

0 = Disable s address detec tion, all byt es are rece ived, and ni nth bit can be us ed as pari ty bit

Asynchronous mode 8-bit (RX9 = 0):

Unused in this mode

Synchronous mode

Unused in this mode

bit 2 FERR: Framing Error bit

1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (Can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of received data (Can be parity bit)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS40044B-page 71

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12.1 USART Baud Rate Generator

(BRG)

The BRG supports both the Asynchronous and

Synchron ou s m od es of the U SAR T. It is a dedicated 8-

bit baud rate generator. The SPBRG register controls

the period of a free running 8-bit timer. In Asynchro-

nous mode bit BRGH (TXSTA<2>) also controls the

baud rate. In Synchronous mode bit BRGH is ignored.

Table 12-1 shows the formula for computation of the

baud rat e for dif feren t USART modes, wh ich only a pply

in Master mode (internal clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRG register can be calculate d

using the formula in Table 1 2-1. From this, the error in

baud rate can be determined.

Example 12-1 shows the calculation of the baud rate

error for the following conditions:

FOSC = 16 MHz

Desired Baud Rate = 9600

BRGH = 0

SYNC = 0

EXAMPLE 12-1: CALCULATING BAUD

RATE ERROR

It may be advantageous to use the high baud rate

(BRGH = 1) even for slower baud clocks. This is

becaus e the FOSC/(16(X + 1)) equation c an red uce th e

baud rate error in some cases.

Writi ng a new value to the SPBRG register, causes the

BRG timer to be Reset (or cleared), this ensures the

BRG does not wait for a timer overflow before

outputting the new baud rate.

TABLE 12-1: BAUD RATE FORMULA

TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Desired Baud Rate Fosc

64 x1+()

-----------------------

9600 16000000

64 x1+()

------------------------

x25.042=

Calculated Baud Rate 16000000

64 25 1+()

-------------------------- 9615==

Error (Calculated Baud Rate - Desired Baud Rate)

Desired Baud Rate

----------------------------------------------------------------------------------------------------------

= 9615 9600–

9600

------------------------------0.16%=

SYNC BRG H = 0 (Low Speed) BRGH = 1 (High Speed)

1(Asynchron ous ) Baud Rate = FOSC/(64(X+1))

(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate= FOSC/(16(X+1))

Legend: X = value in SPBRG (0 to 255)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on all

other

Resets

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unkno wn, - = unimplemented read as ‘0’ .

Shaded cells are not used by the BRG.

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DS40044B-page 72 Preliminary  2004 Microchip Technology Inc.

TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE

BAUD

RATE (K)

FOSC = 20 MHz SPBRG

value

(decimal)

16 MHz SPBRG

value

(decimal)

10 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3NA——NA——NA——

1.2NA——NA——NA——

2.4NA——NA——NA——

9.6 NA — — NA — — 9.766 +1.73% 255

19.2 19.53 +1.73% 255 19.23 +0.16% 207 19.23 +0.16% 129

76.8 76.92 +0.16% 64 76.92 +0.16% 51 75.76 -1.36% 32

96 96.15 +0.16% 51 95.24 -0.79% 41 96.15 +0.16% 25

300 294.1 -1.96 16 307.69 +2.56% 12 312.5 +4.17% 7

500 500 0 9 500 0 7 500 0 4

HIGH 5000 — 0 4000 — 0 2500 — 0

LOW 19.53 — 255 15.625 — 255 9.766 — 255

BAUD

RATE (K)

FOSC = 7.15909 MHz S PBRG

value

(decimal)

5.0688 MHz SPBRG

value

(decimal)

4 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3NA——NA——NA——

1.2NA——NA——NA——

2.4NA——NA——NA——

9.6 9.622 +0.23% 185 9.6 0 131 9.615 +0.16% 103

19.2 19.24 +0.23% 92 19.2 0 65 19.231 +0.16% 51

76.8 77.82 +1.32 22 79.2 +3.13% 15 75.923 +0.16% 12

96 94.20 -1.88 18 97.48 +1.54% 12 1000 +4.17% 9

300 298.3 -0.57 5 316.8 5.60% 3 NA ——

500 NA — — NA ——NA——

HIGH 1789.8 — 0 1267 — 0 100 — 0

LOW 6.991 — 255 4.950 — 255 3.906 — 255

BAUD

RATE (K)

FOSC = 3.579545 MHz S PBRG

value

(decimal)

1 MHz SPBRG

value

(decimal)

32.768 kHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3 NA — — NA — — 0.303 +1.14% 26

1.2 NA — — 1.202 +0.16% 207 1.170 -2.48% 6

2.4 NA — — 2.404 +0.16% 103 NA ——

9.6 9.622 +0.23% 92 9.615 +0.16% 25 NA — —

19.2 19.04 -0.83% 46 19.24 +0.16% 12 NA — —

76.8 74.57 -2.90% 11 83.34 +8.51% 2 NA — —

96 99.43 +3.57% 8 NA ——NA ——

300 298.3 0.57% 2 NA — — NA — —

500 NA ——NA—— ——

HIGH 894.9 — 0 250 — 0 8.192 — 0

LOW 3.496 — 255 0.9766 — 255 0.032 — 255

 2004 Microchip Technology Inc. Preliminary DS40044B-page 73

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TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

BAUD

RATE (K)

FOSC = 20 MHz S PBRG

value

(decimal)

16 MHz SPBRG

value

(decimal)

10 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3NA——NA ——NA ——

1.2 1.221 +1.73% 255 1.202 +0.16% 207 1.202 +0.16% 129

2.4 2.404 +0.16% 129 2.404 +0.16% 103 2.404 +0.16% 64

9.6 9.469 -1.36% 32 9.615 +0.16% 25 9.766 +1.73% 15

19.2 19.53 +1.73% 15 19.23 +0.16% 12 19.53 +1.73V 7

76.8 78.13 +1.73% 3 83.33 +8.51% 2 78.13 +1.73% 1

96 104.2 +8.51% 2 NA — — NA — —

300 312.5 +4.17% 0 NA — — NA — —

500 NA — — NA — — NA — —

HIGH 312.5 — 0 250 — 0 156.3 — 0

LOW 1.221 — 255 0.977 — 255 0.6104 — 255

BAUD

RATE (K)

FOSC = 7.15909 MHz SPBRG

value

(decimal)

5.0688 MHz SPBRG

value

(decimal)

4 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3 NA — — 0.31 +3.13% 255 0.3005 -0.17% 207

1.2 1.203 +0.23% 92 1.2 0 65 1.202 +1.67% 51

2.4 2.380 -0.83% 46 2.4 0 32 2.404 +1.67% 25

9.6 9.322 -2.90% 11 9.9 +3.13% 7 NA — —

19.2 18.64 -2.90% 5 19.8 +3.13% 3 NA — —

76.8 NA — — 79.2 +3.13% 0 NA — —

96 NA — — NA — — NA — —

300 NA — — NA — — NA — —

500 NA — — NA — — NA — —

HIGH 111.9 — 0 79.2 — 0 62.500 — 0

LOW 0.437 — 255 0.3094 — 255 3.906 — 255

BAUD

RATE (K)

FOSC = 3.579545 MHz SPBRG

value

(decimal)

1 MHz SPBRG

value

(decimal)

32.768 kHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

0.3 0.301 +0.23% 185 0.300 +0.16% 51 0.256 -14.67% 1

1.2 1.190 -0.83% 46 1.202 +0.16% 12 NA — —

2.4 2.432 +1.32% 22 2.232 -6.99% 6 NA — —

9.6 9.322 -2.90% 5 NA — — NA — —

19.2 18.64 -2.90% 2 NA — — NA — —

76.8NA——NA——NA— —

96 NA — — NA — — NA — —

300 NA — — NA — — NA — —

500 NA — — NA — — NA — —

HIGH 55.93 — 0 15.63 — 0 0.512 — 0

LOW 0.2185 — 255 0.0610 — 255 0.0020 — 255

PIC16F627A/628A/648A

DS40044B-page 74 Preliminary  2004 Microchip Technology Inc.

TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

BAUD

RATE (K)

FOSC = 20 MHz SPBRG

value

(decimal)

16 MHz SPBRG

value

(decimal)

10 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

9600 9.615 +0.16% 129 9.615 +0.16% 103 9.615 +0.16% 64

19200 19.230 +0.16% 64 19.230 +0.16% 51 18.939 -1.36% 32

38400 37.878 -1.36% 32 38.461 +0.16% 25 39.062 +1.7% 15

57600 56.818 -1.36% 21 58.823 +2.12% 16 56.818 -1.36% 10

115200 113.636 -1.36% 10 111.111 -3.55% 8 125 +8.51% 4

250000 250 0 4 250 0 3 NA — —

625000 625 0 1 NA — — 625 0 0

1250000 1250 0 0 NA — — NA — —

BAUD

RATE (K)

FOSC = 7.16 MHz SPBRG

value

(decimal)

5.068 MHz SPBRG

value

(decimal)

4 MHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

9600 9.520 -0.83% 46 9598.485 0.016% 32 9615.385 0.160% 25

19200 19.454 +1.32% 22 18632.35 -2.956% 16 19230.77 0.160% 12

38400 37.286 -2.90% 11 39593.75 3.109% 7 35714.29 -6.994% 6

57600 55.930 -2.90% 7 52791.67 -8.348% 5 62500 8.507% 3

115200 111.860 -2.90% 3 105583.3 -8.348% 2 125000 8.507% 1

250000 NA — — 316750 26.700% 0 250000 0.000% 0

625000 NA — — NA — — NA — —

1250000 NA — — NA — — NA — —

BAUD

RATE (K)

FOSC = 3.579 MHz SPBRG

value

(decimal)

1 MHz SPBRG

value

(decimal)

32.768 kHz SPBRG

value

(decimal)

KBAUD ERROR KBAUD ERROR KBAUD ERROR

9600 9725.543 1.308% 22 8.928 -6.994% 6 NA NA NA

19200 18640.63 -2.913% 11 20833.3 8.507% 2 NA NA NA

38400 37281.25 -2.913% 5 31250 -18.620% 1 NA NA NA

57600 55921.88 -2.913% 3 62500 +8.507 0 NA NA NA

115200 111243.8 -2.913% 1 NA — — NA NA NA

250000 223687.5 -10.525% 0 NA — — NA NA NA

625000 NA — — NA — — NA NA NA

1250000 NA — — NA — — NA NA NA

 2004 Microchip Technology Inc. Preliminary DS40044B-page 75

PIC16F627A/628A/648A

The dat a on t he RB1/RX/D T pin is sampled three time s

by a majority detect circuit to determine if a high or a

low level is present at the RX pin. If bit BRGH

(TXSTA<2>) is clear (i.e., at the low baud rates), the

sampling is done on the seventh, eighth and ninth fall-

ing edges of a x16 clock (Figure 12-3). If bit BRGH is

set (i.e., at the high baud rates), the sampling is done

on t he 3 c lo ck edges preced ing th e s ec on d ri sing edge

after the first falling e dge of a x4 cloc k (Figure 12-4 and

Figure 12-5).

FIGURE 12-1: RX PIN SAMPLING SCHEME. BRGH = 0

FIGURE 12-2: RX PIN SAMPLING SCHEME, BRGH = 1

FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1

Baud CLK

x16 CLK

Start bit bit 0

Samples

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3

Baud CLK for all but Start bit

(RB1/RX/DT pin)

RX pin

Baud CLK

x4 CLK

Q2, Q4 CLK

Start Bit bit 0 bit 1

First falling edge after RX pin goes low

Second rising edge

Samples Samples Samples

1234123412

RX pin

Baud CLK

x4 CLK

Q2, Q4 CLK

Start Bit bit 0

First falling edge after RX pin goes low

Second rising edge

Samples

1234

Baud CLK for all but Start bit

PIC16F627A/628A/648A

DS40044B-page 76 Preliminary  2004 Microchip Technology Inc.

FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1

12.2 USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one Start bit, eight or nine data bits

and one Stop bit). The most common data format is

8-bit. A dedicated 8-bit baud rate generator is used to

derive baud rate frequencies from the oscillator. The

USART transmits and receives the LSb first. The

USART’s transmitter and receiver are functionally

independent but use the same data format and baud

rate. The baud rate generator produces a clock either

x16 or x64 of the bit shift rate, depending on bit BRGH

(TXSTA<2>). Parity is not supported by the hardware,

but can b e im pl em ente d in so ftw are (and sto red as the

ninth data bit). Asynchronous mode is stopped during

Sleep.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the

following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

12.2.1 USART ASYNCHRONOUS

TRANSMITTER

The USART transmitter block diagram is shown in

Figure 12-5. The heart of t he tr ansmi tter is the t rans mit

(serial) shift regist er (TSR). The shi ft register ob tains it s

data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the Stop bit has been

transmitted from the previous load. As soon as the S top

bit is transmitted, t he TSR is loaded with new dat a from

the TXREG register (if available). Once the TXREG

in one TCY), the TXREG register is empty and flag bit

TXIF (PIR1<4>) is set. This interrupt can be enabled/

disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in

software. It will Reset only when new dat a is loaded into

the TXREG register. While flag bit TXIF indicated the

status of the TXREG register, another bit TRMT

(TXSTA<1>) shows the status of the TSR register.

S t atus bit TRMT is a read onl y bit which is set whe n the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data

and the baud rate generator (BRG) has produced a

shift clock (Figure 12-5). The transmission can also be

started by first loading the TXREG register and then

setting enable bit TXEN. Normally when transmission

is first started, the TSR register is empty, so a transfer

to the TXREG register will result in an immediate

transfer to TSR resulting in an empty TXREG. A back-

to-back transfer is thus possible (Figure 12-7). Clearing

enable bit TXEN during a transmission will cause the

transmission to be aborted and will Reset the

transmitter. As a result the RB2/T X/CK pin wi ll rev ert to

hi-impedance.

In order to select 9-bit transmission, transmit bit TX9

(TXSTA<6>) should be set and the ninth bit should be

written to TX9D (TXSTA<0>). The ninth bit must be

written before writing the 8-bit data to the TXREG

to the TSR register (if the TSR is empty). In such a

case, an incorrect ninth data bit maybe loaded in the

TSR registe r.

Baud CLK

x16 CLK

Start bit bit 0

Samples

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3

Baud CLK for all but Start bit

(RB1/RX/DT pin)

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit T XIF is set when en able bit TXEN

is set.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 77

PIC16F627A/628A/648A

FIGURE 12-5: USART TRANSMIT BLOCK DIAGRAM

Follow these steps when setting up an Asynchronous

Transmission:

1. TRISB<1> bit needs to be set and TRISB<2> b it

cleared in order to configure pins RB2/TX/CK

and RB1/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter pins.

2. Initiali ze th e SPBRG re giste r for the ap prop ria te

baud rate. If a high-speed baud rate is desired,

set bit BRGH. (Section 12.1 "USART Baud

Rate Generator (BRG)")

3. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

4. If interrupts are desired, then set enable bit

TXIE.

5. If 9-bit transmission is desired, then set transmit

bit TX9.

6. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. Load data to the TXREG register (starts

transmission).

FIGURE 12-6: ASYNCHR ON OUS TRANSM ISSION

TXIF

TXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate Generator TX9D

MSb LSb

Data Bus

TXREG registe r

TSR register

(8) 0

TX9

TRMT SPEN

RB2/TX/CK pin

Pin Buffer

and Control

² ² ²

WORD 1 Stop Bit

WORD 1

Transmit Shift Reg

Start Bit Bit 0 Bit 1 Bit 7/8

Write to TXREG Word 1

BRG output

(shift clock)

RB2/TX/CK (pin)

TXIF bit

(Transmit buffer

reg. empty f lag)

TRMT b it

(Transmit shift

reg. empty fl ag)

PIC16F627A/628A/648A

DS40044B-page 78 Preliminary  2004 Microchip Technology Inc.

FIGURE 12-7: ASYNCHRONOUS T RANSMISSION (BACK TO BACK)

TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transm it data register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generat or Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented locations read as ‘0’.

Shaded cells are not used for Asynchronous Transmission.

Tr an smit Shift Reg.

Write to TXREG

BRG output

(shift clock)

RB2/TX/CK (pin)

TXIF bit

(inte rru pt reg . flag)

TRMT bi t

(Transmit shift

reg. empty flag)

Word 1 Word 2

WORD 1 WORD 2

Start Bit Stop Bit St ar t Bit

Transmit Shift Reg.

WORD 1 WORD 2

Bit 0 Bit 1 Bit 7/8 Bit 0

Note: This timing diagram shows two consecutive transmissions.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 79

PIC16F627A/628A/648A

12.2.2 USART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 12-8.

The data is received on the RB1/RX/DT pin and drives

the data recovery block. The data recovery block is

actuall y a hi gh-spe ed shi fter oper ating a t x16 ti mes th e

baud rate, whereas the main receive serial shifter

operates at the bit rate or at FOSC.

When Asynchronous mode is selected, reception is

enabled by setti ng bit CRE N (RCSTA<4>).

The heart of the receiver is the receive (serial) shift

received data in the RSR is transferred to the RCREG

bit R CIF ( PIR1<5 >) i s set. T he ac tual interr upt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read-only bit, which is

cleared by the hardware. It is cleared when the RCREG

double buffered register, (i.e., it is a two deep FIFO). It

is possible for two bytes of data to be received and

transferred to the RCREG FIFO and a third byte begin

shifting to the RSR register. On the detection of the

Stop bit of the third byte, if the RCREG register is still

full then overrun error bit OERR (RCSTA<1>) will be

set. The word in the RSR will be lost. The RCREG

the F IF O. Ov err u n bi t OE RR ha s to b e cl e ar ed in s of t-

ware. Th is is done by re setting the re ceive logi c (CREN

is cleared and then set). If bit OERR is set, transfers

from the RSR register to the RCREG register are inhib-

ited, so it is es sen tia l to c lea r error bi t OER R if it is se t.

Framing error bit FERR (RCST A<2>) is set if a Stop bit

is detected as clear. Bit FERR and the 9th receive bit

are bu ffered the same way as the receive data. Read-

ing the RCREG, will load bits RX9D and FERR with

new va lues, therefo re it is es sentia l for the user to read

the RCSTA register before reading RCREG register in

order not to lose the old FERR and RX9D inform ation .

FIGURE 12-8: USA RT RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RB1/RX/DT Pin Buf fer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR register

MSb LSb

RX9D RCREG register FIFO

Interrupt RCIF

RCIE Data Bus

³ 64

³ 16

or Stop Start

(8) 710

RX9

² ² ²

RX9

ADEN

RX9

ADEN

RSR<8>

Enable

Load of

Receive

Buffer

RCREG register

RX9D

PIC16F627A/628A/648A

DS40044B-page 80 Preliminary  2004 Microchip Technology Inc.

FIGURE 12-9: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT

FIGURE 12-10: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST

FIGURE 12-11: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY

VALID DATA BYTE

START

BIT BIT1BIT0 BIT8 BIT0STOP

BIT

START

BIT BIT8 STOP

BIT

RB1/RX/DT (PIN)

RCV BUFFER REG

RCV SHIFT REG

READ RCV

BUFFER REG

RCREG

RCIF

(INTERRUPT FLAG)

WORD 1

RCREG

BIT8 = 0, DATA BYTE BIT8 = 1, ADDRESS BYTE

ADEN = 1

(ADDRESS MATCH

ENABLE)

‘1’ ‘1’

Note: This timing diagram sho ws a data byte followed by an addres s byte. The data by te is not read into th e RCREG

(Receive Buffer) because ADEN = 1 and Bit 8 = 0.

START

BIT BIT1BIT0 BIT8 BIT0STOP

BIT

START

BIT BIT8 STOP

BIT

RB1/RX/DT (PIN)

REG

RCV BUFFER REG

RCV SHIFT

READ RCV

BUFFER REG

RCREG

RCIF

(INTERRUPT FLAG)

WORD 1

RCREG

BIT8 = 1, ADDRESS BYTE BIT8 = 0, DATA BYTE

ADEN = 1

(ADDRESS MATCH

ENABLE)

‘1’ ‘1’

Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG

(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.

START

BIT BIT1BIT0 BIT8 BIT0STOP

BIT

START

BIT BIT8 STOP

BIT

RB1/RX/DT (PIN)

REG

RCV BUFFER REG

RCV SHIFT

READ RCV

BUFFER REG

RCREG

RCIF

(INTERRUPT FLAG)

WORD 2

RCREG

BIT8 = 1, ADDRESS BYTE BIT8 = 0, DATA BYTE

ADEN

(ADDRESS MATCH

ENABLE)

WORD 1

RCREG

Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG

(Receive Buffer) because ADEN was updated after an address mat ch, and was cleared to a ‘0’, so the contents

of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 81

PIC16F627A/628A/648A

Follow these steps when setting up an Asynchronous

Reception:

1. TRISB<1> bit needs to be set and TRISB<2> b it

cleared in order to configure pins RB2/TX/CK

and RB1/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter pins.

2. Initiali ze th e SPBRG re giste r for the ap prop ria te

baud rate. If a high-speed baud rate is desired,

set bit BRGH. (Section 12.1 "USART Baud

Rate Generator (BRG)").

3. Enable the asynchronous serial port by clearing

bit SYNC, and setting bit SPEN.

4. If interrupts are desired, then set enable bit

RCIE.

5. If 9-bit reception is de sired, then set bit RX9.

6. Enable the reception by setting bit CREN.

7. Flag bit RCIF will be set when reception is com-

plete an d an interru pt will be generated i f enable

bit RCIE wa s set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during r eception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

enable bit C RE N.

TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0 00 0 -0 00 0000 -00 0

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 000 0 00 0x 0000 000 x

1Ah RCREG USART Receive data register0000 00 00 0000 000 0

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 000 0 -0 00 00 00 -00 0

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0 00 0 -0 10 0000 -01 0

99h SP BR G Ba ud R a te Ge nerator Reg i ster 0000 00 00 00 00 000 0

Legend: x = unknown, - = unimplemented location s read as ‘0’. Sha ded cells are not used for Asynchronous Reception.

PIC16F627A/628A/648A

DS40044B-page 82 Preliminary  2004 Microchip Technology Inc.

12.3 USART Address Detect Function

12.3.1 USART 9-BIT RECEIVER WITH

ADDR ES S DET E CT

When the RX9 bit is set in the RCSTA register, 9 bits

are receiv ed and the ni nth bit i s pl aced in the RX9D bit

of the RCSTA register. The USART module has a

special provision for multi-processor communication.

Multiprocessor communication is enabled by setting

the ADEN bit (RCSTA<3>) along with the RX9 bit. The

port is now programmed such that when the last bit is

received, the contents of the receive shift register

(RSR) are tra nsferred to the receive b uffer, the ninth b it

of the RSR (RSR<8>) is transferred to RX9D, and the

recei ve int errup t is set if and onl y if RSR<8 > = 1. This

feature can be used in a multi-processor system as

follows:

A master processor intends to transmit a block of data

to one of many slaves . It must first send out a n address

byte that identifies the target slave. An addres s byte is

identified by setting the ninth bit (RSR<8>) to a ‘1’

(instead of a ‘0’ for a data byte). If the ADEN and RX9

bits are set in the slave’s RCSTA register, enabling

multiprocessor communication, all data bytes will be

ignored. However, if the ninth received bit is equal to a

‘1’, indicating that the received byte is an address, the

slave will be interrupted and the contents of the RSR

allows the slave to be interrupted only by addresses, so

that the slav e can exam ine th e rece ived byte t o see if it

is being addressed. The addressed slave will then cle ar

its ADEN bit and prepare to receive data bytes from the

master.

When ADEN is enabled (= ‘1’), all data bytes are

ignored. Following the Stop bit, the data will not be

loaded into the receive buffer, and no interrupt will

occur. If another byte is shifted into the RSR register,

the previous data byte will be lost.

The ADEN bit will only take effect when the receiver is

configured in 9-bit mode (RX9 = ‘1’). When ADEN is

disabled (= ‘0’), all data bytes are received and the 9th

bit can be used as the p ari ty bit .

The receive block diagram is shown in Figure 12-8.

Reception is enabled by setting bit CREN

(RCSTA<4>).

12.3.1.1 Setting up 9-bit mode with Address

Detect

Follow these steps when setting up Asynchronous

Reception with Address Detect Enabled:

1. TRISB<1> bit nee ds to be set and TRISB<2> bit

cleared in order to configure pins RB2/TX/CK

and RB1/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter pins.

2. Initiali ze the SPBRG re gis ter for the ap prop ria te

baud rate. If a high-speed baud rate is desired,

set bit BRGH.

3. Enabl e asynch ronous comm unicatio n by settin g

or clearing bit SYNC and setting bit SPEN.

4. If interrupts are desired, then set enable bit

RCIE.

5. Set bit RX9 to enable 9-bit reception.

6. Set ADEN to enable address detect.

7. Enable the reception by setting enable bit CREN

or SREN.

8. Flag bit RCIF will be set when reception is

complete, and an interrupt will be generated if

enable bit RCIE was set.

9. Read the 8-bit received data by reading the

RCREG register to determine if the device is

being addressed.

10. If any error occurred, cl ear the error by clearing

enable bit CREN if it was already set.

11. If the de vice has been address ed (RSR<8> = ‘1 ’

with address match enabled), clear the ADEN

and RCIF bits to allow data bytes and address

bytes to be read into the receive buffer and

interrupt the C PU.

TABLE 12-8: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0 00 0 -0 00 00 00 -00 0

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCR EG USART Receive data register 0000 00 00 00 00 000 0

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -0 00 0000 -00 0

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -01 0

99h SPBRG Baud Rate Generator Register 000 0 00 00 0000 000 0

Legend: x = unknown, - = unimplemented location s read as ‘0’. Sha ded cells are not used for Asynchronous Reception.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 83

PIC16F627A/628A/648A

12.4 USART Synchronous Master

Mode

In Sync hronous Ma ster mode, the data is transmi tted in

a half-duplex manner, (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

additio n enable bit SPEN (RCSTA<7>) is set in o rder to

configure the RB2/TX/CK and RB1/RX/DT I/O pins to

CK (clo ck) and DT (data) li nes respect ively . The Master

mode i ndicates that the processo r transmit s the master

clock on the CK line. The Master mode is entered by

setting bit CSRC (TXSTA<7>).

12.4.1 USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 12-5. The hear t of the tr ansmi tter is the trans mit

(serial) shift regist er (TSR). The shi ft register ob tains it s

data from the read/write transmit buffer register

TXREG. The TXREG register is loaded with data in

software. The TSR regi ster is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new da ta from the TXREG (if available). Once the

TXREG regi ster transfers the data to the TSR register

(occurs in one Tcycle), the TXREG is empty and inter-

rupt bit, TXIF (PIR1<4>) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will Reset onl y when new dat a is loaded into the

TXREG register . While flag bit TXIF indicates the status

of th e T XR EG r egi st e r, anot h er b it T RMT (T XS TA<1> )

shows the status of the TSR register. TRMT is a read

only bit which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory so it is not

availa ble to the user.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data.

The fir st data bit will be shifte d out on the next av ailable

rising edge of the clock on the CK line. Data out is

stab le around the fal ling edge of the sync hronous cloc k

(Figure 12-12). The transmission can also be started

by first loading the TXREG register and then setting bit

TXEN (Fi gure 12-13). This is adv ant ageous wh en sl ow

baud rate s are selec ted, since th e BRG is kep t in Reset

when bits TXEN, CREN, and SREN are clear. Setting

enable bit TXEN will start the BRG, creating a shift

clock immediately. Normally when transmission is first

started, the TSR register is empty, so a transfer to the

TXREG regi ster will result in an immediate transfer to

TSR resulting in an empty TXREG. Back-to-back

transfers are possible.

Clearing enable bit TXEN, during a transmission, will

cause the transmission to be aborted and will Reset the

transmitter . The DT and CK pins will revert to hi-imped-

ance. If either bit CREN or bit SREN is set, during a

transmission, the transmission is aborted and the DT

pin reverts to a hi-impedance state (for a reception).

The CK pin will remain an output if bit CSRC is set

(internal clock). The transmitter logic however is not

Reset although it is disconnected from the pins. In

order to Reset the transmitter, the user has to clear bit

TXEN. If bit SREN is set (to interrupt an on-going

transmission and receive a single word), then after the

single word is received, bit SREN will be cleared and

the serial port will revert back to transmitting since bit

TXEN is still set. The DT line will immediately switch

from hi-impedance Receive mode to transmit and start

driving. To avoid this, bit TXEN shou ld be cleared.

In order to select 9-bit transmission, the TX9

(TXSTA<6>) bit should be set and the ninth bit should

be written to bit TX9D (TXSTA<0>). The ninth bit must

be written before writing the 8-bit data to the TXREG

result in an immediate transfer of the data to the TSR

the TXREG was writt en befo re writ ing the “new” T X9D,

the “present” value of bit TX9D is loaded.

Follow these steps when setting up a Synchronous

Master Transmis sion:

1. TRISB<1> bit nee ds to be set and TRISB<2> b it

cleared in order to configure pins RB2/TX/CK

and RB1/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter pins.

2. Initiali ze the SPBRG re gis ter for the ap prop ria te

baud rate (Section 12.1 "USART Baud Rate

Generator (BRG)").

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

4. If interrupts are desired, then set enable bit

TXIE.

5. If 9-bit tran sm is si on is des ired , then set bit TX9.

6. Enable the transmission by setting bit TXEN.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. S tart transmission by loading dat a to the TXREG

PIC16F627A/628A/648A

DS40044B-page 84 Preliminary  2004 Microchip Technology Inc.

TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

FIGURE 12-12: SYNCHRONOUS TRANSMISSION

FIGURE 12-13: SYNCHRONOUS TR ANSMISSION (THROUGH TXEN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Value on all

other Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -0 00 0000 -00 0

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transmit data register 0000 00 00 00 00 000 0

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0 00 0 -0 00 00 00 -00 0

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -0 10 00 00 -01 0

99h S PBRG Baud Rate Generator Register 0000 00 00 00 00 000 0

Legend: x = unknown, - = unimplemented, read as ‘0’ . Shaded cells are not used f or Sync hronous Ma st er Transmission.

BIT 0 BIT 1 BIT 7

WORD 1

Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

BIT 2 B IT 0 BIT 1 BIT 7

RB1/RX/DT PIN

RB2/TX/CK PIN

WRITE TO

TXREG REG

TXIF BI T

(INTERRUPT FLAG)

TRMT

TXEN BI T

‘1’ ‘1’

WORD 2

TRMT BIT

WRITE WORD1 WRITE WORD2

Note: Sync Master Mode; SPBR G = ‘0’. Continuous transmission of two 8-bit words.

RB1/RX/DT PIN

RB2/ TX/CK PIN

WR IT E TO

TXREG REG

TXIF BI T

TRMT BIT

BIT0 BIT1 BIT2 BIT6 BIT7

TXEN BI T

 2004 Microchip Technology Inc. Preliminary DS40044B-page 85

PIC16F627A/628A/648A

12.4.2 USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN

(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is

sampled on the RB1/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, then only a single

word is received. If enable bit CREN is set, the recep-

tion is c ontinuous until CREN is cleared. If bo th bits are

set then CREN takes precedence. After clocking the

last bit, the received data in the Receive Shift Register

(RSR) is transferred to the RCREG register (if it is

empty). When the transfer is complete, interrupt flag bit

RCIF (PIR1<5>) is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read only bit which is

Reset by the hardware. In this case it is Reset when the

RCREG register has been read and is empty. The

RCREG is a double buffered register, (i.e., it is a two

deep FIFO). It is possible for two bytes of data to be

received and transferred to the RCREG FIFO and a

third byte to beg in shifting into the RSR register. On the

clocking of the last bit of the third byte, if the RCREG

(RCSTA<1>) is set. The word in the RSR will be lost.

The RCREG register can be read twice to retrieve the

two bytes in the FIFO. Bit OERR has to be cleared in

software (by clearing bit CREN). If bit OERR is set,

transfers from the RSR to the RCREG are inhibited, so

it is essential to clear bit OERR if it is set. The 9th

receive bit is buffered the same way as the receive

data. Reading the RCREG register, will load bit RX9D

with a new v alue, therefo re it is essen tial for the use r to

read the RCSTA register before reading RCREG in

order not to lose the old RX9D information.

Follow these steps when setting up a Synchronous

Master Reception:

1. TRISB<1> bit nee ds to be set and TRISB<2> b it

cleared in order to configure pins RB2/TX/CK

and RB1/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter pins.

2. Initiali ze the SPBRG re gis ter for the ap prop ria te

baud rate. (Section 12.1 "USART Baud Rate

Generator (BRG)").

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

4. Ensure bits CREN and SREN are clear.

5. If interrupts are desired, then set enable bit

RCIE.

6. If 9-bit reception is desired, then set bit RX9.

7. If a single reception is required, set bit SREN.

For continuous reception set bit CREN.

8. Interru pt flag bit RCIF wil l be set when recep tion

is comple te and an interrupt will be generated if

enable bit RCIE was set.

9. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCREG register.

11 . If any error occurred, clear the error by clearing

bit CREN.

TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Address Na m e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR Value on all

other Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive data register 0000 0000 0000 0000

8Ch PIE1 EEPIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE -000 0000 -000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Gener ator Reg ist er 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented read as ‘0 ’. Sha ded cells are not used for Synchronous Master Reception .

PIC16F627A/628A/648A

DS40044B-page 86 Preliminary  2004 Microchip Technology Inc.

FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

12.5 USART Synchronous Slave Mode

Synchronous Slave mode dif fers from the Master mode

in the fact that the shift clock is supplied externally at

the RB2 /TX/CK pin (instea d of being su pplied intern ally

in Master mode). This allows the device to transfer or

receive data while in Sleep mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

12.5.1 USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the synchronous Master and Slave

modes are identical except in the case of the Sleep

mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shifted ou t of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from Sleep and if the global interrupt is

enabled , the p rog ram wil l bran ch to the in terrupt

vector (0004h).

Follow these steps when setting up a Synchronous

Slave Transmission:

1. TRISB<1> bit nee ds to be set and TRISB<2> b it

cleared in order to configure pins RB2/TX/CK

and RB1/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter pins.

2. Enable the synchronous slave serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

3. Clear bits CREN and SREN.

4. If interrupts are desired, then set enable bit

TXIE.

5. If 9-bit tran sm is si on is des ired , then set bit TX9.

6. Enable the transmission by setting enable bit

TXEN.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

8. S tart transmission by loading dat a to the TXREG

CREN BIT

RB1/RX/DT PIN

RB2/TX/CK PIN

WRITE TO

BIT SREN

SREN BIT

RCIF BIT

(INTERRUPT)

READ

RXREG

Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q2 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

‘0’

BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7

‘0’

Q1Q2Q3Q4

Note: Timing diagram demons tra tes Sync Mast er Mode with bit SREN = ‘1’ and bit BRG = ‘0’.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 87

PIC16F627A/628A/648A

12.5.2 USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Mlave

modes is identical except in the case of the Sleep

mode. Also, bit SREN is a don't care in Slave mode.

If receive is enabled, by setting bit CREN, prior to the

SLEEP inst ruction , then a w ord m ay be rec eived durin g

Sleep. On completely receiving the word, the RSR

and if enabl e bit RCIE bit is set , the interrupt gene rated

will wake the chip from Sleep. If the global interrupt is

enabled , the pro gram wil l branc h to the interru pt vec tor

(0004h).

Follow these steps when setting up a Synchronous

Slave Reception:

1. TRISB<1> bit needs to be set and TRISB<2> b it

cleared in order to configure pins RB2/TX/CK

and RB1/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter pins.

2. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

3. If interrupts are desired, then set enable bit

RCIE.

4. If 9-bit reception is desired, then set bit RX9.

5. To enable reception, set enable bit CREN.

6. Flag bit RCIF will be set when reception is

complete and an interrupt will be generated, if

enable bit RCIE was set.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

bit CREN.

TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on

POR Value on all

other Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0 00 0 -0 00 0000 -00 0

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 000 0 00 0x 00 00 000 x

19h TXREG U SART Transmit data register 0000 00 00 0000 000 0

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0 00 0 -0 00 00 00 -00 0

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -0 10 0000 -01 0

99h SPBRG B aud Rate Gen er at or Re gist er 0000 00 00 0000 000 0

Legend: x = unknown, - = unimplemented read as ‘0 ’. Sha ded cells are not used for Synchronous Slave Transmission.

Address Na m e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Value on all

other Resets

0Ch PIR1 EEIF CMIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive data register 0000 0000 0000 0000

8Ch PIE1 EEIE CMIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Gener ator Reg ist er 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented read as ‘0’. Sha ded cells are no t us ed for Synchronous Slave Recept i on.

PIC16F627A/628A/648A

DS40044B-page 88 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 89

PIC16F627A/628A/648A

13.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This me mo ry

is not d irectly mapp ed in the register file spa ce. Instea d

it is indirectly addressed through the Special Function

Registers (SFRs). There are four SFRs used to read

and write this memory. These regist ers are:

• EECON1

• EECON2 (Not a physically implemented register)

• EEDATA

• EEADR

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEPROM location

being accessed. PIC16F627A/628A devices have 128

bytes of dat a EEPROM w ith an add res s ra nge from 0h

to 7Fh. PIC16F648A device has 256 bytes of data

EEPROM with an address range from 0h to FFh.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the n ew data (erase be fore write). The EEPROM

data memory is rated for high erase/write c ycles. The

write time is controlled by an on-chip timer. The write-

time will vary with voltage and temperature as well as

from chip to chip. Please refer to AC specifications fo r

exact limits.

When the device is code protected, the CPU can

continu e to rea d and wr ite th e data EEPROM memory.

A device programmer can no longer access

this memory.

Additional information on the data EEPROM is

available in the PICmicro® Mid-Range Reference

Manual (DS33023).

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0

bit 7 bit 0

bit 7-0 EEDATn: Byte value to write to or read from Data EEPROM memory location.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

EADR7 EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0

bit 7 bit 0

bit 7 PIC16F627A/628A - Unimplemented Address: Must be set to ‘0’

PIC16F648A - EEADR: Set to ‘1’ specifies top 128 locations (128-256) of EEPROM Read/Write

Operation

bit 6-0 EEADR: Specifies one of 128 lo cations of EEPROM Read/Write Operation

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F627A/628A/648A

DS40044B-page 90 Preliminary  2004 Microchip Technology Inc.

13.1 EEADR

The PIC16F648A EEADR register addresses 256

bytes of data EEPROM. All eight bits in the register

(EEADR<7:0>) are required.

The PIC16F627A/628A EEADR register addresses

only th e firs t 128 bytes o f dat a EEPROM so only seven

of the eight bits in the register (EEADR<6:0>) are

required. The upper bit is address decoded. This

means that this bit should always be '0' to ensure that

the address is in the 128 byte memory space.

13.2 EECON1 AND EECON2

REGISTERS

EECON1 is the control register with four low order bits

physically implemented. The upper-four bits are non-

existent and read as '0's.

Control bits RD and WR initiate read and write,

resp ec ti v el y. Th es e bi ts cann o t be cl ear e d, onl y s et , in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prev ents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation.

On powe r-up, the WR EN bit is clear. T he WRERR bi t is

set when a write operation is interrupted by a MCLR

Reset or a WDT Time out Reset during normal opera-

tion. In these situations, following Reset, the user can

check the WRERR bit and rewrite the location. The

data and address will be unchanged in the EEDATA

and EEADR registers.

Interrupt flag bit EEIF in the PIR1 register is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the Data EEPROM write sequence.

U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

— — — — WRERR WREN WR RD

bit 7 bit 0

bit 7-4 Unimplemented: Read as ‘0’

bit 3 WRERR: EEPROM Error Flag bit

1 = A wri te operatio n is premat urely termi nated (any MCLR Re set, any WDT Res et during n or-

mal operation or BOR Reset)

0 = The write ope rati on com pl ete d

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the data EEPROM

bit 1 WR: Write Co ntro l bit

1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.

0 = Write cycle to the data EEPROM is com plete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit

can only be set (not cleared) in software).

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2004 Microchip Technology Inc. Preliminary DS40044B-page 91

PIC16F627A/628A/648A

13.3 READING THE EEPROM DATA

MEMORY

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1<0>). The data is available, in the very

next cycle, in the EEDATA register; therefore it can be

read in the next instructi on. EEDAT A will hol d this value

until another read or until it is written to by the user

(during a write operation).

EXAMPLE 13-1: DATA EEPROM READ

13.4 WRITING TO THE EEPROM DATA

MEMORY

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

specific sequence to initiate the write for each byte.

EXAMPLE 13-2: DATA EEPROM WRITE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number what is not equal to

the required cycles to execute the required sequence

will cause the data not to be written into the EEPROM.

Additionally, the WREN bit in EECON1 must be se t to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit wil l not af fect this wri te cycle. T he WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit in the

PIR1 registers must be cleared by software.

13.5 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the Data

EEPROM should be verified (Example 13-3) to the

desired value to be written. This should be used in

applications where an EEPROM bit will be stressed

near the spe cif ication limit.

EXAMPL E 13- 3: W R ITE VE RIF Y

13.6 PROTECTION AGAIN ST

SPURIOUS WRITE

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also

when enabled, the Power-up Timer (72 ms duration)

prevents EEPROM write.

The write initiate sequence , and th e WREN bit together

help prevent an accidental write during brown-out,

power glitch, or software malfunction.

BSF STATUS, RP0 ;Bank 1

MOVLW CONFIG_ADDR ;

MOVWF EEADR ;Address to read

BSF EECON1, RD ;EE Read

MOVF EEDATA, W ;W = EEDATA

BCF STATUS, RP0 ;Bank 0

Required

Sequence

BSF STATUS, RP0 ;Bank 1

BSF EECON1, WREN ;Enable write

BCF INTCON, GIE ;Disable INTs.

MOVLW 55h ;

MOVWF EECON2 ;Write 55h

MOVLW AAh ;

MOVWF EECON2 ;Write AAh

BSF EECON1,WR ;Set WR bit

;begin write

BSF INTCON, GIE ;Enable INTs.

BSF STATUS, RP0;Bank 1

MOVF EEDATA, W

BSF EECON1, RD ;Read the

;value written

;

;Is the value written (in W reg) and

;read (in EEDATA) the same?

;SUBWF EEDATA, W ;

BTFSS STATUS, Z ;Is difference 0?

GOTO WRITE_ERR ;NO, Write error

: ;YES, Good write

: ;Continue program

PIC16F627A/628A/648A

DS40044B-page 92 Preliminary  2004 Microchip Technology Inc.

13.7 Using the Data EEPROM

The data EEPROM is a h igh en dura nc e, by te add res s-

able array that has been optimized for the storage of

frequently changing information (e.g., program

variables or other data that are updated often).

Frequently changing values will typically be updated

more often than specification D124. If this is not the

case, an array refresh must be performed.

For this reason, variables that change infrequently

(such as constants, IDs, calibration, etc.) should be

stored in Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 13-4.

EXAMPLE 13-4: DATA EEPROM REFRESH ROUTINE

13.8 DATA EEPROM OPERAT ION

DURING CODE PROTECT

When the device is code protected, the CPU is able to

read and write data to the Data EEPROM.

TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Note: If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification D124.

BANKSEL 0X80 ;select Bank1

CLRF EEADR ;start at address 0

BCF INTCON, GIE ;disable interrupts

BSF EECON1, WREN ;enable EE writes

Loop

BSF EECON1, RD ;retrieve data into EEDATA

MOVLW 0x55 ;first step of ...

MOVWF EECON2 ;... required sequence

MOVLW 0xAA ;second step of ...

MOVWF EECON2 ;... required sequence

BSF EECON1, WR ;start write sequence

BTFSC EECON1, WR ;wait for write complete

GOTO $ - 1

#IFDEF __16F648A ;256 bytes in 16F648A

INCFSZ EEADR, f ;test for end of memory

#ELSE ;128 bytes in 16F627A/628A

INCF EEADR, f ;next address

BTFSS EEADR, 7 ;test for end of memory

#ENDIF ;end of conditional assembly

GOTO Loop ;repeat for all locations

BCF EECON1, WREN ;disable EE writes

BSF INTCON, GIE ;enable interrupts (optional)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

V alue on all

other

Resets

9Ah EEDATA EEPROM data register xxxx xxxx uuuu uuuu

9Bh EEADR EEPROM address register xxxx xxxx uuuu uuuu

9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000

9Dh EECON2(1) EEPROM control register 2 ---- ---- ---- ----

Legend: x = unkn own, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condit ion.

Shaded cells are not used by data EEPROM.

Note 1: EECON2 is not a physical re gis ter.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 93

PIC16F627A/628A/648A

14.0 SPECIAL FEATURES OF THE

CPU

Special circuits to deal with the needs of real-time

applications are what se ts a microcontroller apart from

other processors. The PIC16F627A/628A/648A family

has a host of such features intended to maximize

system reliability, minimize cost through elimination of

external components, provide power saving Operating

modes and of fer code prote ction.

These are:

1. OSC selection

2. Reset

3. P ower-on Reset (PO R)

4. Power-up Timer (PWRT)

5. Oscillator Start-Up Timer (OST)

6. Brown-out Reset (BOR)

7. Interrupts

8. Watchdog Timer (WDT)

9. Sleep

10. Code protection

11. ID Locations

12. In-Circuit Serial Programming™ (ICS P™)

The PIC16F627A/628A/648A has a Watchdog Timer

which is controlled by configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers th at of fer nec essa ry delay s on pow er-up. One i s

the Oscillator Start-up Timer (OST), intended to keep

the chip in Reset until the crystal oscillator is stable.

The other is the Power-up Timer (PWRT), which

provides a fixed delay of 72 ms (nominal) on power-up

only, designed to keep the part in Reset while the

power suppl y st abil izes . There is a lso c ircui try to Reset

the device if a Brown-out occurs. With these three

functions on-chip, most applications need no external

Reset circuitry.

The Sleep mo de is des igned to offer a very low curre nt

Power-down mode. The user can wake-up from Sleep

through external Reset, Watchdog Timer wake-up or

through an inte rrupt. Several os cillator opti ons are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of configuration

bits are used to select various options.

14.1 Configuration Bits

The confi guration b its ca n be program med (read as ‘0’)

or left unprogrammed (read as ‘1’) to select various

device configurations. These bits are mapped in

program memory location 2007h.

The user will note that address 2007h is beyond

the user program memory space. In fact, it belongs

to the special configuration memory space (2000h –

3FFFh), which can be accessed only during

programming. See Programming Specification

(DS41196) for additional info rmation.

PIC16F627A/628A/648A

DS40044B-page 94 Preliminary  2004 Microchip Technology Inc.

CP ———— CPD LVP BOREN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0

bit 13 bit 0

bit 13: CP: Flash Program Memory Code Protection bit(2)

(PIC16F648A)

1 = Code protection off

0 = 0000h to 0FFFh code protected

(PIC16F628A)

1 = Code protection off

0 = 0000h to 07FFh code protected

(PIC16F627A)

1 = Code protection off

0 = 0000h to 03FFh code protected

bit 12-9: Unimplemented: Read as ‘0’

bit 8: CPD: Data Code Protection bit(3)

1 = Data memory code protection off

0 = Data memory code protected

bit 7: LVP: Low Voltage Programming Enable

1 = RB4/PGM pin has PGM function, low voltage programming enabled

0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming

bit 6: BOREN: Brown-out Reset Enable bit (1)

1 = BOR Reset enabled

0 = BOR Reset disabled

bit 5: MCLRE: RA5/MCLR pin function select

1 = RA5/MCLR pin function is MCLR

0 = RA5/MCLR pin function is digi tal Input, MCLR internally tied to VDD

bit 3: PWRTEN: Power-up Timer Enable bit (1)

1 = PWRT disabled

0 = PWRT enabled

bit 2: WDTEN: Wa tchd og Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 4, 1-0: FOSC2:FOSC0: Oscillator Selection bits(4)

111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7 /OSC1 /CLK IN

110 = RC oscillato r: I/O func tion on RA6/OSC2 /CLK OUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN

101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

100 = INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN

011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN

010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it did in the PIC16F627/628.

2: The code protection scheme has changed from the code protection scheme used in the PIC16F627/628. The entire Flash program mem-

ory needs to be bulk erased to set the CP bit, turning the code protection off. See Programming Specification DS41196 for details.

3: The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See Programming Specification

DS41196 for details.

4: When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown

 2004 Microchip Technology Inc. Preliminary DS40044B-page 95

PIC16F627A/628A/648A

14.2 Oscillator Configurations

14.2.1 OSCILLATOR TYPE S

The PIC16F627A/628A/648A can be operated in eight

diff erent osci llator optio ns. The user c an program thre e

configuration bits (FOSC2 through FOSC0) to select

one of these eight modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC External R esi st or/C apacitor (2 modes)

• INTOSC Internal Pre cision Oscillat or (2 modes)

• EC Extern al Cloc k In

14.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, LP or HS modes a crystal or ceramic resonator

is connected to the OSC1 and OSC2 pins to establish

oscillation (Figure 14-1). The PIC16F627A/628A/648A

oscillator design requires the use of a parallel cut

crystal. Use of a series cut crystal may give a frequency

out of the crystal manuf acturers specif ications. When in

XT, LP or HS modes, the device can have an external

clock source to drive the OSC1 pin (Figure 14-4).

FIGURE 14-1: CRY STAL OPERATION

(OR CERAMIC

RESONATOR) (HS, XT OR

LP OSC

CONFIGURATION)

T ABLE 14-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

T ABLE 14-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

14.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built.

Prepackaged oscillators provide a wide operating

range and better stability. A well-designed crystal

oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits can be

used; one with series resonance, or one with parallel

resonance.

Figure 14-2 shows implementation of a parallel reso-

nant osc illato r cir cuit. Th e circu it is desig ne d to use the

fundamental frequency of the crystal. The 74AS04

inverter performs the 180° phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This could be used for external oscillator designs.

Note 1: A series resistor may be required for AT strip cut

crystals.

2: See Table 14-1 and Table 14-2 for recommended

values of C1 and C2.

XTAL

OSC2

RS(1)

OSC1

RF Sleep

PIC16F627A/628A/648A

FOSC

Mode Freq OSC1(C1) OSC2(C2)

XT 455 kHz

2.0 MHz

4.0 MHz

22 - 100 pF

15 - 68 pF

22 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz 10 - 68 pF

10 - 22 pF 10 - 68 pF

10 - 22 pF

Note: Higher capacitance increases the stability of the

oscillator but also increases the start-up time. These

values are for design guidance only. Since each

resonator h as its own characteristics, the user shou ld

consult the resonator manufacturer for appropriate

values of external components.

Mode Fr eq OSC1(C1) OSC 2(C2)

LP 32 kHz

200 kHz 15 - 30 pF

0 - 15 pF 15 - 30 pF

0 - 15 pF

XT 100 kHz

2 MHz

4 MHz

68 - 150 pF

15 - 30 pF

150 - 200 pF

15 - 30 pF

HS 8 MHz

10 MHz

20 MHz

15 - 30 pF

Note: Higher capacitance increases the stability of the

oscillator but also increases the start-up time. These

values are for design guidance only. A ser ies resistor

(RS ) may be required in HS mode as well as XT mode

to avoi d o ver driv in g c rystal s wit h l o w dr i ve level spec i-

fication. Since each crystal has its own characteristics,

the user should consult the crystal manufacturer for

appropriate values of external components.

PIC16F627A/628A/648A

DS40044B-page 96 Preliminary  2004 Microchip Technology Inc.

FIGURE 14-2: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 14-3 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crys tal. The inverter performs a 180°

phase shift in a series resonant oscillator circuit. The

330 kΩ resistors prov id e th e ne gative feedback to bia s

the inverters in their linear region.

FIGURE 14-3: EXTERN AL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

14.2.4 PRECISION INTERNAL 4 MHZ

OSCILLATOR

The inte rnal p reci sion oscilla tor prov ides a fix ed 4 MHz

(nominal) system clock at VDD = 5 V and 25°C. See

Section 17.0 "Electrical Speci fications", for in forma-

tion on variation over voltage and temperature.

14.2.5 EXTERNAL CLOC K IN

For applications where a clock is already available

elsewhere, users may directly drive the PIC16F627A/

628A/648A provided that this external clock source

meets the AC/DC timing requirements listed in

Section 17.6 "Timing Diagrams and Specifica-

tions". Figu re 14-4 below shows how an external clock

circuit should be configured.

FIGURE 14-4: EXTERNAL CLOCK INPUT

OPERATION (EC, HS, XT

OR LP OSC

CONFIGURATION)

14.2.6 RC OSCILLATOR

For applications where precise timing is not a require-

ment, the RC oscillator option is available. The

operation and functionality of the RC oscillator is

dependent upon a number of variables. The RC

oscillator frequency is a function of:

• Supply voltage

• Resistor (REXT) and capacitor (CEXT) value s

• Operating temperature.

The oscillator frequency will vary from unit to unit due

to normal process parameter variation. The difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to account for the

tolerance of the external R and C components.

Figure 14-5 shows how the R/C combination is

connected.

FIGURE 14-5: RC OSCILLATOR MODE

The RC Oscillator mode has two options that control

the unused OSC2 pin. The first allows it to be used as

a general purpose I/O port. The other configures the

pin as an output providing the Fosc signal (internal

clock divided by 4) for test or external synchronization

purposes.

14.2.7 CLKOUT

The PIC16F627A/628A/648A can be configured to

provi de a c lock out s ignal by prog rammi ng the c onfig u-

ration word. The oscillator frequency, divided by 4 can

be used fo r test purpose s or to sync hronize oth er logic.

+5V

10K 4.7K

10K

74AS04

XTAL

10K

74AS04 PIC16F627A/628A/648A

CLKIN

TO OTHER

DEVICES

C1 C2

330 KΩ

74AS04 74AS04

PIC16F627A

CLKIN

TO OTHER

DEVICES

XTAL

330 KΩ

74AS04

0.1 PF

628A/648A

Clock From

ext. system PIC16F627A/628A/648A

RA6

RA7/OSC1/CLKIN

RA6/OSC2/CLKOUT

CEXT

VDD

REXT

VSS

PIC16F627A/628A/648A

FOSC/4

Internal

Clock

CLKIN

RA7/OSC1/

RA6/OSC2/CLKOUT

 2004 Microchip Technology Inc. Preliminary DS40044B-page 97

PIC16F627A/628A/648A

14.2.8 SPECIAL FEATURE: DUAL SPEED

OSCILLATOR MODES

A software programmable dual speed Os cillator mode

is provided when the PIC16F627A/628A/648A is

configu red in the INTOSC Oscillator mo de. This feature

allows users to dynamically toggle the oscillator speed

between 4 MHz and 37 kHz nominal in the INTOSC

mode. Applications that require low current power

saving s, bu t c an not tol era te p utt ing the part in to S lee p,

may use this mode.

There is a time delay associated with the transition

between Fast and Slow oscillator speeds. This

Oscillator Speed Transition delay consists of two

existing clock pulses and eight new speed clock

pulses. During this Clock Speed Transition Delay the

System Clock is halted causing the processor to be

frozen in time. During this delay the Program Counter

and the Clock Out stop.

The OSCF bit in the PCON register is used to control Dual

Speed mode. See Section 4.2.2.6 "PCON Register",

14.3 Reset

The PIC16F627A/628A/648A differentiates between

vari ous kin ds of Reset:

a) Power-on Reset (POR)

b) MCLR Reset during normal operation

c) MCLR Reset during Sleep

d) WDT Reset (normal operation)

e) WDT wake-up (Sleep)

f) Brown-out Reset (BOR)

Some regi sters a re not af fected in a ny Rese t conditio n;

their status is unkn ow n on POR and unchanged i n an y

other Reset. Most other registers are reset to a “Reset

state” on Power-on Reset, Brown-out Reset, MCLR

Reset, WDT Reset and MCLR Reset during Sleep.

They are not affected by a WDT wake-up, since this is

viewed as the resumption of norm al op era tion . TO and

PD bits are set or cleared differently in different Reset

situations as indicated in Table 14-4. These bits are

used in software to determine the nature of the Reset.

See Table 14-7 for a full description of Reset states of

all registers.

A simp lified block di agram o f the on -chip R eset cir cuit

is sh own in Figure 14-6.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Table 17-7 for pulse width

specification.

FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/

VDD

OSC1/

WDT

Module

VDD rise

detect

OST/PWRT

WDT

Time out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Reset

Enable OST

Enable PWRT

Sleep

See Table 14-3 for time out situations.

Note 1: This is a separate oscillator from the INTOSC/RC oscillator.

Brown-out

detect Reset BOREN

CLKIN

VPP Pin

10-bit Ripple-counter

Schmitt Trigger Input

On-chip(1)

OSC

PIC16F627A/628A/648A

DS40044B-page 98 Preliminary  2004 Microchip Technology Inc.

14.4 Power-on Reset (POR), Power-up

T imer (PWRT), Oscillator St art-up

Timer (OST) and Brown-out Reset

(BOR)

14.4.1 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the POR, just tie the

MCLR pin through a res is tor to VDD. This will eliminate

external RC components usually needed to create

Power-on Reset. A maximum rise time for VDD is

required. See Electrical S pecifications for details.

The POR circuit does not produce an internal Reset

when VDD declines.

When the device starts normal operation (exits the

Reset condition), device operating parameters

(voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting”.

14.4.2 POWER-UP TIMER (PWRT)

The PWRT provides a fixed 72 ms (nominal) time out

on power-up (POR) or if enabled from a Brown-out

Reset. The PWRT operates on an internal RC oscilla-

tor . The chip is kept in Reset as long as PWRT is active.

The PWRT delay allows the VDD to rise to an accept-

able level. A configuration bit, PWRTE can disable (if

set) or enab le (i f cle are d or pro gram m ed) th e PWR T. It

is recommended that the PWRT be enabled when

Brown-out Reset is enabled.

The Power-Up Time delay will vary from chip to chip

and due to VDD, temperature and process variation.

See DC parameters Table 17-7 for details.

14.4.3 OSCILLATOR START-UP TIMER

(OST)

The OST provides a 1024 oscillator cycle (from OSC1

input) delay after the PWRT delay is over. Program

execution will not start until the OST time out is

complete. This ensures that the crystal oscillator or

resonator has started and stabilized.

The OST time out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

Sleep. See Table 17-7.

14.4.4 BROWN-OUT RESET (BOR)

The PIC16F627A/628A/648A have on-chip BOR

circuitry. A configuration bit, BOREN, can disable (if

clear/programmed) or enable (if set) the BOR Reset

circuitry. If VDD falls below VBOR for longer than TBOR,

the brown-out situation will Reset the chip. A Reset is

not guaranteed to occur if VDD falls below VBOR for

shorter than TBOR. VBOR and TBOR are defined in

Table 17-2 and Table 17-7, resp ectiv el y.

On any Reset (Power-on, Brown-out, Watchdog, etc.),

the chip will remain in Reset until VDD rises above

BVDD (see Figure 14-7). The Power-up Timer will now

be invoked, if enabled, and will keep the chip in Reset

an additional 72 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-u p Timer will be re-initialized. Onc e VDD

rises above VBOR, the Power-Up Timer will execute a

72 ms Reset. Figure 14-7 shows typical Brown-out

situations.

FIGURE 14-7: BROW N-OUT SITUATIONS WITH PWRT ENABLED

72 ms

VBOR

VDD

INTERNAL

RESET

VBOR

VDD

INTERNAL

RESET 72 ms

<72 ms

72 ms

VBOR

VDD

INTERNAL

RESET

≥ TBOR

Note: 72 ms delay only if PWRTE bit is programmed to ‘0’.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 99

PIC16F627A/628A/648A

14.4.5 TIME OUT SEQUENCE

On power-up the time out sequence is as follows: First

PWRT time out is invoked after POR has expired. Then

OST i s ac ti v at ed. T h e tota l t im e ou t w i ll v ary b as e d on

oscillator configuration and PWRTE bit Status. For

example, in RC mode with PWRTE bit set (PWRT

disabled), there will be no time out at all. Figure 14-8,

Figure 14-9 and Figure 14-10 depict time out

sequences.

Since th e time ou ts oc cur from th e POR puls e, if MCLR

is kept low long en ough, the time out s will ex pire. The n

bringing MCLR high will begin execution immediately

(see Figure 14-9). This is useful for testing purposes or

to synchronize more than one PIC16F627A/628A/

648A device operating in parallel.

Table 14-6 shows the Reset conditions for some

special registers, while Table 14-7 shows the Reset

conditions for all the registers.

14.4.6 POWER CONTROL (PCON) STATUS

The power control/Status Register, PCON (address

8Eh) has two bits.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on-Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0

indicating that a brown-out has occurred. The BOR

Status bit is a don’t care and is not necessarily

predictable if the brown-out circuit is disabled (by

setting BORE N bit = 0 in the Confi gura tio n word).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaf fec ted oth erwise. T he user m ust write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset if POR is ‘0’, it will indicate that a

Power-on Reset must have occurred (VDD may have

gone too low).

TABLE 14-3: TIME OUT IN VARIOUS SITUATIONS

TABLE 14-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE

Oscillator Configuration Power-up Brown-out Reset Wake-up

from Sleep

PWRTEN = 0 PWRTEN = 1 PWRTEN = 0 P WRTE N = 1

XT, HS, LP 72 ms +

1024•TOSC 1024•TOSC 72 ms +

1024•TOSC 1024•TOSC 1024•TOSC

RC, EC 72 ms —72 ms ——

INTOSC 72 ms —72 ms —6µs

POR BOR TO PD Condition

0X11Power-on Reset

0X0XIllegal, TO is set on POR

0XX0Illegal, PD is set on POR

10XXBrown-out Reset

110uWDT Reset

1100WDT Wake-up

11uuMCLR Reset during normal operation

1110MCLR Reset during Sleep

Legend: u = unchanged, x = unknown

PIC16F627A/628A/648A

DS40044B-page 100 Preliminary  2004 Microchip Technology Inc.

TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

TABLE 14-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

V alue on all

other

Resets(1)

03h, 83h,

103h , 183h STATUS IRP RP1 RPO TO PD ZDC C0001 1xxx 000q quuu

8Eh PCON ——— — OSCF —PORBOR ---- 1-0x ---- u-uq

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Shaded cells are not us ed by Brown-out Reset.

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watch dog T i mer Reset during normal operation.

Condition Program

Counter Status

Power-on Reset 000h 0001 1xxx ---- 1-0x

MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu

MCLR Reset during Sleep 000h 0001 0uuu ---- 1-uu

WDT Reset 000h 0000 uuuu ---- 1-uu

WDT Wake-up PC + 1 uuu0 0uuu ---- u-uu

Brown-out Reset 000h 000x xuuu ---- 1-u0

Interrupt Wake-up from Sleep PC + 1(1) uuu1 0uuu ---- u-uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the inte rrupt vector

(0004h) after execution of PC+1.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 101

PIC16F627A/628A/648A

TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS

Reset

•MCLR

Reset during normal

operation

•MCLR

Reset during Sleep

• WDT Reset

• Brown-out Reset (1)

• Wake-up from Sleep(7)

through interrupt

• Wake-up from Sleep(7)

through WDT time out

W—xxxx xxxx uuuu uuuu uuuu uuuu

INDF 00h — — —

TMR0 01h, 101h xxxx xxxx uuuu uuuu uuuu uuuu

PCL 02h, 82h,

102h, 182h 0000 0000 0000 0000 PC + 1(3)

STATUS 03h, 83h,

103h, 183h 0001 1xxx 000q quuu(4) uuuq 0uuu(4)

FSR 04h, 84h,

104h, 184h xxxx xxxx uuuu uuuu uuuu uuuu

PORTA 05h xxxx 0000 xxxx 0000 uuuu uuuu

PORTB 06h, 106h xxxx xxxx uuuu uuuu uuuu uuuu

PCLATH 0Ah, 8Ah,

10Ah, 18Ah ---0 0000 ---0 0000 ---u uuuu

INTCON 0Bh, 8Bh,

10Bh,18Bh 0000 000x 0000 000u uuuu uqqq(2)

PIR1 0Ch 0000 -000 0000 -000 qqqq -qqq(2)

TMR1L 0Eh xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H 0Fh xxxx xxxx uuuu uuuu uuuu uuuu

T1CON 10h --00 0000 --uu uuuu(6) --uu uuuu

TMR2 11h 0000 0000 0000 0000 uuuu uuuu

T2CON 12h -000 0000 -000 0000 -uuu uuuu

CCPR1L 15h xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H 16h xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON 17h --00 0000 --00 0000 --uu uuuu

RCSTA 18h 0000 000x 0000 000x uuuu uuuu

TXREG 19h 0000 0000 0000 0000 uuuu uuuu

RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu

CMCON 1Fh 0000 0000 0000 0000 uu-- uuuu

OPTION 81h,181h 1111 1111 1111 1111 uuuu uuuu

TRISA 85h 1111 1111 1111 1111 uuuu uuuu

TRISB 86h, 186h 1111 1111 1111 1111 uuuu uuuu

PIE1 8Ch 0000 -000 0000 -000 uuuu -uuu

PCON 8Eh ---- 1-0x ---- 1-uq(1,5) ---- u-uu

PR2 92h 1111 1111 1111 1111 uuuu uuuu

TXSTA 98h 0000 -010 0000 -010 uuuu -uuu

SPBRG 99h 0000 0000 0000 0000 uuuu uuuu

EEDATA 9Ah xxxx xxxx uuuu uuuu uuuu uuuu

EEADR 9Bh xxxx xxxx uuuu uuuu uuuu uuuu

EECON1 9Ch ---- x000 ---- q000 ---- uuuu

EECON2 9Dh — — —

VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu

Legend: u = unchang ed, x = unknown, - = unim pl e m ente d bi t, read s as ‘0’, q = value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrup t and the GIE bi t is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 14-6 for Reset value fo r sp ecific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All ot her Resets will cause bit 0 = u.

6: Reset to ‘--00 0000’ on a Bro w n-out Reset (BOR).

7: Peripherals generating interrupts for wake-up from Sleep will change the resulting bits in the ass ociated registers.

PIC16F627A/628A/648A

DS40044B-page 102 Preliminary  2004 Microchip Technology Inc.

FIGURE 14-8: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE

FIGURE 14-9: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 14-10: TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

Tpwrt

Tost

VDD

MCLR

INTERNAL POR

PWRT TIME OUT

OST TIME OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME OUT

OST TIME OUT

INTERNAL RESET

Tpwrt

Tost

Tpwrt

Tost

VDD

MCLR

INTERNAL POR

PWRT TIME OUT

OST TIME OUT

INTERNAL RESET

 2004 Microchip Technology Inc. Preliminary DS40044B-page 103

PIC16F627A/628A/648A

FIGURE 14-11: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

FIGURE 14-12: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 14-13: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: External Power- on Reset circuit is required

only if VDD power-up slope is too slow. The

diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 100Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin breakdown

due to Electrostatic Discharge (ESD) or

Electrical Overstress (EOS).

VDD

MCLR

PIC16F627A/628A/648A

VDD

Note 1: This circuit will activ ate Reset when VDD

goes below (Vz + 0.7V) where Vz = Zener

voltage.

2: Internal Brown-out Reset circuitry should

be disabled when using this circuit.

VDD33k

10k

40k

VDD

MCLR

PIC16F627A/628A/648A

Vdd x R1

R1 + R2 = 0.7 V

VDD

R2 40k

VDD

MCLR

PIC16F627A/628A/648A

Note 1: This Brown-out Circuit is less expensive,

albeit less accurate. Transistor Q1 turns off

when VDD is below a certain level such that:

2: Internal Brown-out Reset should be dis-

abled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

VDD x R1

R1 + R2 = 0.7 V

PIC16F627A/628A/648A

DS40044B-page 104 Preliminary  2004 Microchip Technology Inc.

14.5 Interrupts

The PIC16F627A/628A/648A has 10 sources of

interrupt:

• External Inte rrup t RB0/INT

• TMR0 Overfl ow Interru pt

• PORTB Change Interrupts (pins RB7:RB4)

• Comparator Interrupt

• USART Interrupt TX

• USART Interrupt RX

• CCP Interrupt

• TMR1 Overfl ow Interru pt

• TMR2 Mat ch Interrup t

• Data EEPROM Interrupt

The interrupt control register (INTCON) records

individual interrupt requests in flag bits. It also has

individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register. GIE is cleared on Reset.

The “return from interrupt” instruction, RETFIE, exits

interrupt routine as well as sets the GIE bit, which re-

enable RB 0/INT inte rrup t s.

The INT p in interr upt, the RB port ch ange in terrupt an d

the TMR0 overflow interrupt flags are contained in the

INTCON register.

The peripheral interrupt flag is contained in the special

contained in special registers PIE1.

When an interrupt is responded to, the GIE is cleared

to disable any further interrupt, the return address is

pushed i nto the st ack and th e PC is loa ded with 0004 h.

Once in the interrupt service routine the source(s) of

the interrupt can be determined by polling the interrupt

flag bits. The interrupt flag bit(s) must be cleared in

software before re-enabling interrupts to avoid RB0/

INT recursive interru pt s .

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs (Figure 14-

15). The latency is the same for one or two cycle

instructions. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be

cleared in software before re-enabling interrupts to

avoid multiple interrupt requests. Individual interrupt

flag bits are set regardless of the status of their

corresponding mask bit or the GIE bit.

FIGURE 14-14: INTERRUPT LOGIC

Note 1: Individual interrupt flag bits are set

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The CPU will execute a NOP

in the cycle immediately following the

instruction which clears the GIE bit. The

interrupts which were ignored are still

pending to be serviced when the GIE bit

is set again.

TMR2IF

TMR2IE

CCP1IF

CCP1IE

CMIF

CMIE

TXIF

TXIE

RCIF

RCIE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in Sleep mode)

Interrupt to CPU

EEIE

EEIF

TMR1IF

TMR1IE

 2004 Microchip Technology Inc. Preliminary DS40044B-page 105

PIC16F627A/628A/648A

14.5.1 RB0/INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if INTEDG bit (OPTION<6>) is set, or

falling, if INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, the INTF bit

(INTCON<1>) is set. This interrupt can be disabled by

clear ing th e INTE control bit (IN TCON<4> ). The I NTF

bit mu st be cl eared i n softwa re in th e inte rrupt se rvice

routine before re-enabling this interrupt. The RB0/INT

interrupt can wake-up the processor from Sleep, if the

INTE bit w as set pr ior to going into Sleep. The sta tus of

the GIE bit decides whether or not the processor

branche s to the interru pt vector foll owing wake-up. Se e

Section 14.8 "Power-Down Mode (Sleep )" for det ails

on Sleep , and Figur e 14-17 for timing of wake-up f rom

Sleep through RB0/INT interrupt.

14.5.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 6.0 "Timer0 Module".

14.5.3 PORTB INTERRUPT

An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/dis abled

by setting/clearing the RBIE (INTCON<4>) bit. For

operation of PORTB (Section 5.2 "POR TB and TRISB

Registers").

14.5.4 COMPARATOR INTERRUPT

See Section 10.6 "Comparator Interrupts" for

complete description of com p arator interrupt s.

FIGURE 14-15: INT PIN INTERRUPT TIMING

Note: If a change on the I/O pin should occur

when th e read o peratio n is be ing ex ecuted

(start s during the Q2 cycle and ends before

the start of the Q3 cycle), then the RBIF

interrupt flag may not get set.

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INST RUCTION FL OW

Instruction

Fetched

Instruction

Executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycl e

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycl e

Inst ( PC)

—

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available in RC and INTOSC Oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during t he Q4-Q1 cycles.

(1)

(4)

(5) (2)

(3)

PIC16F627A/628A/648A

DS40044B-page 106 Preliminary  2004 Microchip Technology Inc.

TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS

14.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W register and

Status Register). This must be implemented in

software.

Example 14-2 stores and restores the Status and W

in a common memory location (i.e., W_TEMP is

defi ned at 0x 70 in Ban k 0 and is th erefo re, acc essib le

at 0xF0, 0x170 and 0x1F0). The Example 14-2:

• Stores the W register

• Stores the Stat us Reg is ter

• Executes the ISR code

• Restores the Status (and bank select bit register)

• Restores the W register

EXAMPLE 14-2: SAVING THE STATUS

AND W REGISTERS IN

RAM

14.7 Wat chdog Timer (WDT)

The watchdog timer is a free running on-chip RC

oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the CLKIN pin. That means that the

WDT will run , even if th e clock on th e OSC1 and OSC2

pins of the device has been stopped, for example, by

executi on of a SLEEP in struction. During norm al op er-

ation, a WDT time out generates a device Reset. If the

device is in Sleep mode, a WDT time out causes the

device to wak e-up and c ontinu e with norm al opera tio n.

The WDT can be permanently disabled by program-

ming the configuration bit WDTE as clear

(Section 1 4.1 "Configuration Bits").

14.7.1 WDT PERIOD

The WDT ha s a nom inal time out p erio d o f 18 ms (w i th

no prescaler). The time out periods vary with tempera-

ture, VDD and proces s variations from part to part (see

DC Specifications, Table 17-7). If longer time out

periods are desired, a po stsca ler with a divis ion ratio of

up to 1:128 can be assigned to the WDT under

software control by writing to the OPTION register.

Thus, time out periods up to 2.3 seconds can be

realized.

The CLRWDT and SLEEP instructions clear the WDT

and the p ostscal er , if assi gned to the WDT, and prevent

it from timing out and generating a device R eset.

The T O bit in the Status Regi ster will be cleared upon a

Watchdog Timer time out.

14.7.2 WDT PROGRAMMING

CONSIDERATIONS

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time ou t occurs.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

Value on all

other

Resets(1)

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal

operation.

MOVWF W_TEMP ;copy W to temp register,

;could be in any ban k

SWAPF STAT US ,W ;swap status to be sav ed

;into W

BCF STATUS,RP0 ;change to ba nk 0

;regardless of current

;bank

MOVWF STAT US _TEMP ;save status to ba nk 0

;register

:(ISR)

SWAPF STATUS_TEMP,W;swap STATUS_TEMP register

;int o W, set s bank to orig inal

;state

MOVWF STATUS ;move W into STATUS register

SWAPF W_TEMP,F ;swap W_TEMP

SWAPF W_TE MP ,W ;swap W_TEMP into W

 2004 Microchip Technology Inc. Preliminary DS40044B-page 107

PIC16F627A/628A/648A

FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS

14.8 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the Status Register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they

had, before SLEEP was e xecuted (drivi ng high, low,

or hi-impedance) .

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the

comparators, and VREF should be disabled. I/O pins

that are hi-impedance inputs should be pulled high or

low externally to avoid switching currents caused by

floating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The

contribu tion from on ch ip pull-up s on PORTB shou ld be

considered.

The MCLR pin must be at a logic high le vel (VIHMC).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR Reset

Value on all

other

Resets

2007h Config.

bits LVP BOREN MCLRE FOSC2 PWRTE WDTE FOSC1 FOSC0 uuuu uuuu uuuu uuuu

81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.

Note: Shaded cells are not used by the Watchdog Timer.

(Figure 6-1)

Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register .

From TMR0 Clock Source

Watchdog

Timer

WDT

Enable Bit

8 to 1 MUX PS<2:0>

To TMR0

(Figure 6-1)

01PSA

WDT

Time out

PSA

MUX

WDT POSTSCALER/

TMR0 PRESCALER

Note: It should be noted that a Reset generated

by a WDT time out does not drive MCLR

pin low.

PIC16F627A/628A/648A

DS40044B-page 108 Preliminary  2004 Microchip Technology Inc.

14.8.1 WAKE -UP FR OM SLEE P

The devi ce can wake -up from Sleep through one of th e

following events:

1. External Reset input on MCLR pin

2. W a tchdog T i mer w ake-u p (if W DT wa s ena bled)

3. Interrupt from RB0/INT pin, RB Port change, or

any Peripheral Interrupt.

The firs t event wi ll cause a devic e Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the Status Register

can be used to determine the cause of device Reset.

PD bit, which is set on power-up is cleared when Sleep

is in vo ked . TO bit is cleared if WDT wake-up occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake -up throug h an interrupt event, th e corres pond-

ing inte rrupt enabl e bit mu st be set (enabled) . W ake-u p

is regardl ess of the st at e of the GIE bi t. If the G IE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have an NOP after the SLEEP instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

FIGURE 14-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT

14.9 Code Protection

With the Code Protect bit is cleared (Code Protect

enabled ) the contents of the program memory locations

are read out as “00”. See Programing Specification,

DS41196, for details.

14.10 User ID Locations

Four memory locations (2000h-2003h) are designated

as user ID locations where the user can store

check sum or other code-identif ica tio n num be rs. These

locations are not accessible during normal execution

but are readable and writable during program/verify.

Only the Least Sig nificant 4 bits of the user ID locations

are used.

Note: If the global interrupts are disabled (GIE is

cleared ), but any interru pt so urce h as both

its interrupt enabl e b it a nd the correspond-

ing interrup t flag bits set, the device will not

enter Sleep. The SLEEP instruction is

executed as a NOP instruction.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC+1 PC+2

Inst(PC) = Sleep

Inst(PC - 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

Tost(2)

PC+2

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for RC Osc mode.

3: GIE = ‘1’ assumed . In thi s case af ter wake-u p, th e pr ocessor ju mps to the int errupt ro utine. If GIE = ‘0’, execution will continue

in-line.

4: CLKOUT is not available in these Osc modes, but shown here for timing reference.

Note: Only a Bul k E ras e f un cti on ca n set th e CP

and CPD bits by turning off the code

protection. The entire data EEPROM and

Flash program memory will be erased to

turn the code protection off.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 109

PIC16F627A/628A/648A

14.11 In-Ci rcuit Serial Programming

The PIC16F627A/628A/648A microcontrollers can be

serially programmed whi le in the end a pplication cir cuit.

This is simply done with two lines for clock and data,

and three other lines for power, ground, and the

programming voltage. This allows customers to manu-

facture boards with unprogrammed devices and then

program the microcontroller just before shipping the

prod uct. This a lso al lows the m ost r ecent firmw are, o r

a custom firmware to be programmed.

The device is placed into a Program/Verify mode by

holding the RB6 and RB7 pins low while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). RB6 becomes the programming clock

and RB7 becomes the programming data. Both RB6

and RB7 are Schmitt Trigger inputs in this mode.

After Reset, to place the device into Programming/V erify

mode, the program counter (PC) is at location 00h. A 6-

bit command is then supplied to the device. Depending

on the command, 14 bits of program data are then

supplied to or from the device, depending if the

command was a load or a read. For complete details of

serial programming, please refer to the Programming

Specifications (DS41196).

A typical In-Circuit Serial Programming connection is

shown in Figure 14-18.

FIGURE 14-18: TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

14.12 Low Voltage Progr amming

The LVP bit of the configuration word, enables the low

voltage programming. This mode allows the microcon-

troller to be programmed via ICSP using only a 5V

source. This mode remo ve s the requireme nt o f VIHH to

be placed on the MCLR pin. The LVP bit is normally

erased to '1' which enables the low voltage program-

ming. In this mode, the RB4/PGM pin is dedicated to

the programming function and ceases to be a general

purpose I/O pin. The device will enter Programming

mode when a '1' is placed on the RB4/PGM pin. The

HV Programming mode is still available by placing VIHH

on the MCLR pin.

If low-vo lt a ge Pro gram m ing mod e is not used , t he LVP

bit should be programmed to a '0' so that RB4/PGM

becomes a digital I/O pin. To program the device, VIHH

must be placed onto MCLR during programming . The

LVP bit may only be programmed when programming

is entered with VIHH on MCLR. The LVP bit cannot be

programmed when programming is entered with RB4/

PGM.

It should be noted, that once t he L VP bit is programmed

to 0, only high volt age Programming mode can be u sed

to program the device.

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC16F627A/628A/648A

VDD

VSS

RA5/MCLR/VPP

RB6/PGC

RB7/PGD

+5V

VPP

CLK

Data I/O

VDD

Note 1: While in this mode the RB4 pin can no

longer be used as a general purpose I/O

pin.

2: VDD must be 5.0V +10% during erase

operations.

PIC16F627A/628A/648A

DS40044B-page 110 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 111

PIC16F627A/628A/648A

15.0 INSTRUCTION SET SUMMARY

Each PIC16F627A/628A/648A instruction is a 14-bit

word divided into an OPCODE which specifies the

instruction type and one or more operands which

further specify the operation of the instruction. The

PIC16F627A/628A/648A instruction set summary in

Table 15-2 lists byte-oriented, bit-oriented, and

literal and control operations. Table 15-1 shows the

opcode field descriptions.

For byte-oriented instructions, ‘f’ represents a file

designator. The file register designator specifies which

file register is to be used by the instruction.

The desti nation designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W regis ter . If ‘d’ is one, the res ult is placed

in the file register specified in the instruction.

For bit-oriented instructions, ‘b’ represents a bit field

design ator which sel ec t s the nu mb er of the bit af fected

by the op erat ion, while ‘f’ represe nt s the num be r of th e

file in which the bit is located.

For literal and control operations, ‘k’ represents an

eight or eleven bit constant or literal value.

TABLE 15-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basic categories:

•Byte-oriented ope rati ons

•Bit-oriented operations

•Literal and control operations

All instructions are executed within one single

inst ruct ion c yc le , un le ss a co nditional test is tru e or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles with the second cycle executed as a

NOP. One instruction cycle consists of four oscillator

periods . Thus, for an osci llator freque ncy of 4 MHz, the

normal instruction execution time is 1 µs. If a

conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 µs.

Table 15-2 lists the instructions recognized by the

MPASM™ assembler.

Figure 15-1 shows the three general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGURE 15-1: GENERAL FORMAT FOR

INSTRUCTIONS

Field Description

f Register file address (0x00 to 0x7F)

W Working register (accumulator)

b Bit address within an 8-bit file register

k Litera l field, constant data or label

x Don't ca re location (= 0 or 1)

The assemble r will generate code with x = 0. It is the

recommended form of use for comp atibility with all

Microchip so ftware tools.

d Destination select; d = 0: store result in W ,

d = 1: store result in file regist er f.

Default is d = 1

label Label name

TOS Top of Stac k

PC Program Counte r

PCLATH Program Counter High Latc h

GIE Global Interrupt Enable bit

WDT Watchdog Timer/Counter

TO Time out bit

PD P o w er - d own bit

dest Destin ation either the W register or the specified

[ ] Options

( ) Contents

→Assigned to

< > Register bit field

∈In the set of

italics User defined term (font is courier)

Note 1: Any unused opcode is reserved. Use of

any reserved opcode may cause unex-

pected operation.

2: To maintain upward compatibility with

future PICmicro products, do not use the

OPTION and TRIS instr uctions.

Byte-oriented file register operations

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

OPCODE k (literal)

k = 8-bit immediate value

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

13 8 7 6 0

13 10 9 7 06

13 8 7 0

13 11 10 0

PIC16F627A/628A/648A

DS40044B-page 112 Preliminary  2004 Microchip Technology Inc.

TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opco d e Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

—

f, d

—

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inc l usiv e OR W wi th f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtrac t W fr om f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0000

dfff

lfff

0xx0

dfff

ffff

0011

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Se t f

Bit Test f, Skip if Cle ar

Bit Test f, Skip if Set

1(2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

—

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return fr om Subroutine

Go into Standby mode

Subtrac t W fr om l i te ra l

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value pr esent on the

pins themsel ves. For exampl e, if the dat a latc h is ‘1’ for a pin conf igured as inp ut and is driv en low by an exter nal device, t he dat a

will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the

Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed

as a NOP.

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15.1 Instruction Descripti ons

ADDLW Add Literal and W

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Encoding: 11 111x kkkk kkkk

Description: The contents of the W register are

added to the eight bit literal ‘k’ and

the result is placed in the W regist er.

Words: 1

Cycles: 1

Example ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax : [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Encoding: 00 0111 dfff ffff

Description: Add the contents of the W register

with register ‘f’. If ‘d’ is 0 the result is

stored in the W register. If ‘d’ is 1 the

result is stored back in register ‘f’.

Words: 1

Cycles: 1

Example ADDWF REG1, 0

Before Instruction

W=0x17

REG1 = 0xC2

After Instruction

W=0xD9

REG1 = 0xC2

Z=0

C=0

DC = 0

ANDLW AND Literal with W

Syntax : [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Stat us Af fe cte d: Z

Encoding: 11 1001 kkkk kkkk

Description: The contents of W register are

AND’ed with the eight bit literal ‘k’.

The result is placed in the W

Words: 1

Cycles: 1

Example ANDLW 0x5F

Before Instruction

W=0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax : [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Stat us Af fe cte d: Z

Encoding: 00 0101 dfff ffff

Description: AND the W register with register ‘f’.

If ‘d’ is 0 the result is stored in the W

back in register ‘f’.

Words: 1

Cycles: 1

Example ANDWF REG1, 1

Before Instruction

W=0x17

REG1 = 0xC2

After Instruction

W=0x17

REG1 = 0x02

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BCF Bit Clear f

Syntax : [ label ] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 01 00bb bfff ffff

Description: Bit ‘b’ in r egister ‘f’ is cleared.

Words: 1

Cycles: 1

Example BCF REG1, 7

Before Instruction

REG1 = 0xC7

After Instruction

REG1 = 0x47

BSF Bit Set f

Syntax : [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 01 01bb bfff ffff

Description: Bit ‘b’ in register ‘f’ is set.

Words: 1

Cycles: 1

Example BSF REG1, 7

Before Instruction

REG1 = 0x0A

After Instruction

REG1 = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax : [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Stat us Af fe cte d: No ne

Encoding: 01 10bb bfff ffff

Descr iption : If bit ‘b ’ in regis ter ‘f’ is ‘0’ the n the

next instruction is skipped.

If bit ‘b’ is ‘0’ then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a two-

cycle instruct io n.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSC

GOTO

•

REG1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if REG<1> = 0,

PC = address TRUE

if REG<1>=1,

PC = address FALSE

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BTFSS Bit Test f, Skip if Set

Syntax : [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 01 11bb bfff ffff

Desc ription : If bit ‘ b’ in re gister ‘f’ is ‘1’ then th e

next instruction is skipped.

If bit ‘b’ is ‘1’, then the next

instruction fetched during the

current instruction execution, is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSS

GOTO

•

REG1

PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address FALSE

if FLAG<1> = 1,

PC = address TRUE

CALL Call Subroutine

Syntax : [ label ] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Stat us Af fe cte d: No ne

Encoding: 10 0kkk kkkk kkkk

Description: Call Subrou tine. First, return

address (PC+1) is pushed onto

the stack. The eleven bit imme-

diate address is loaded into PC

bits <10:0>. The upper bits of

the PC are loaded from

PCLATH. CALL is a two-cycle

instruction.

Words: 1

Cycles: 2

Example HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE

TOS = Address HERE+1

CLRF Clear f

Syntax : [ label ] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Stat us Af fe cte d: Z

Encoding: 00 0001 1fff ffff

Description: The contents of register ‘f’ are

cleared and the Z bit is set.

Words: 1

Cycles: 1

Example CLRF REG1

Before Instruction

REG1 = 0x5A

After Instruction

REG1 = 0x00

Z=1

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CLRW Clear W

Syntax : [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Encoding: 00 0001 0000 0011

Description: W register is cleared. Zero bit

(Z) is set.

Words: 1

Cycles: 1

Example CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00

Z=1

CLRWDT Clear Watchdog Timer

Syntax : [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets

the prescaler of the WDT. S tatus

bits TO and PD are set.

Words: 1

Cycles: 1

Example CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT count er = 0x00

WDT prescaler = 0

TO =1

PD =1

COMF Complement f

Syntax : [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Stat us Af fe cte d: Z

Encoding: 00 1001 dfff ffff

Description: The contents of register ‘f’ are

complemented. If ‘d’ is 0 the

result is stored in W. If ‘d’ is 1

the re sul t is sto red bac k in regi s-

ter ‘f’.

Words: 1

Cycles: 1

Example COMF REG1, 0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W=0xEC

DECF Decrement f

Syntax : [ label ] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest)

Stat us Af fe cte d: Z

Encoding: 00 0011 dfff ffff

Description: Decrement register ‘f’. If ‘d’ is 0

the result is sto r ed in the W

stored back in regist er ‘f’.

Words: 1

Cycles: 1

Example DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

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DECFSZ Decrement f, Skip if 0

Syntax : [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operati on: (f ) - 1 → (dest); skip if result =

Status Affected: None

Encoding: 00 1011 dfff ffff

Desc ript ion : The conten t s of regi ste r ‘f’ are

decrem ented. If ‘d’ i s 0 the result

is placed in the W register. If ‘d’

is 1 the result is placed back in

If the result is 0, the next instruc-

tion, wh ic h is al rea dy fe tched, is

disc arde d. A NOP is executed

instead making it a two-cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE DECFSZ REG1, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

REG1 = REG1 - 1

if REG1 = 0,

PC = address CONTINUE

if REG1 ≠0,

PC = address HERE+1

GOTO Unconditional Branch

Syntax : [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Stat us Af fe cte d: No ne

Encoding: 10 1kkk kkkk kkkk

Description: GOTO is an unconditional

branch. The eleven-bit immedi-

ate value is loaded into PC bits

<10:0>. The upper bits of PC

are loaded from PCLATH<4:3>.

GOTO is a two-cycle instr uction.

Words: 1

Cycles: 2

Example GOTO THERE

After Instruction

PC = Address THERE

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DS40044B-page 118 Preliminary  2004 Microchip Technology Inc.

INCF I ncrem ent f

Syntax : [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest)

Status Affected: Z

Encoding: 00 1010 dfff ffff

Desc ript ion : The conten t s of regi ste r ‘f’ are

incremented. If ‘d’ is 0 the result

is placed in the W register. If ‘d’

is 1 the result is placed back in

Words: 1

Cycles: 1

Example INCF REG1, 1

Before Instruction

REG1 = 0xFF

Z=0

After Instruction

REG1 = 0x00

Z=1

INCFSZ Increment f, Skip if 0

Syntax : [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest), skip if result = 0

Stat us Af fe cte d: No ne

Encoding: 00 1111 dfff ffff

Description: The contents of register ‘f’ are

increm ent ed. If ‘d’ is 0 th e res ult

is placed in the W register. If ‘d’

is 1 the result is placed back in

If th e re sult is 0, the ne xt instruc-

tion, w hic h is al read y fe tch ed, is

disc arde d. A NOP is executed

instead making it a two-cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE INCFSZ REG1, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

REG1 = REG1 + 1

if CNT = 0,

PC = address CONTINUE

if REG1≠0,

PC = address HERE +1

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IORLW Inclusive OR Literal with W

Syntax : [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affected: Z

Encoding: 11 1000 kkkk kkkk

Desc ription: The c ontents of the W register is

OR’ed with the eight bit literal ‘k’.

The result is placed in the W

Words: 1

Cycles: 1

Example IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W=0xBF

Z=0

IORWF Inclusive OR W with f

Syntax : [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (dest)

Status Affected: Z

Encoding: 00 0100 dfff ffff

Desc ription : Inc lusiv e OR th e W reg ister wi th

placed in the W register. If ‘d’ is

1 the result is pl aced back in

Words: 1

Cycles: 1

Example IORWF REG1, 0

Before Instruction

REG1 = 0x13

W=0x91

After Instruction

REG1 = 0x13

W=0x93

Z=1

MOVLW Move Literal to W

Syntax : [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Stat us Af fe cte d: No ne

Encoding: 11 00xx kkkk kkkk

Description: The eight bit literal ‘k’ is loaded

into W register. The don’t cares

will assemble as 0’s.

Words: 1

Cycles: 1

Example MOVLW 0x5A

After Instruction

W = 0x5A

MOVF Move f

Syntax : [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Stat us Af fe cte d: Z

Encoding: 00 1000 dfff ffff

Description: The contents of register f is

moved to a d estination depen-

dent upon the status of d. If d =

0, destinati on is W reg i ster. If d

= 1, the destinati on is fil e regis -

ter f itself. d = 1 is useful to test

a file register since status flag Z

is affected.

Words: 1

Cycles: 1

Example MOVF REG1, 0

After Instruction

W= value in REG1 register

Z= 1

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MOVWF Move W to f

Syntax : [ label ] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

Status Affected: None

Encoding: 00 0000 1fff ffff

Description: Move data from W register to

Words: 1

Cycles: 1

Example MOVWF REG1

Before Instruction

REG1 = 0xFF

W = 0x4F

After Instruction

REG1 = 0x4F

W = 0x4F

NOP No Operation

Syntax : [ label ] NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 00 0000 0xx0 0000

Description: No operation.

Words: 1

Cycles: 1

Example NOP

OPTION Load Option Register

Syntax: [ label ] OPTION

Operands: None

Operation: (W) → OPTION

Stat us Af fe cte d: None

Encoding: 00 0000 0110 0010

Description: The con tents of t he W register a re

loaded in the OPTION register.

This instruction is supported for

code compatibilit y with PIC16C5X

products. Since OPTION is a

readable/writable register, the

user can directly address it. Using

only register instruction such as

MOVWF.

Words: 1

Cycles: 1

Example To maint ain upward com patibil-

ity with future PICmicro®

products, do not use this

instruction.

RETFIE Return from Interrupt

Syntax : [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Stat us Af fe cte d: No ne

Encoding: 00 0000 0000 1001

Description: Return from Interrupt. Stack is

POPed and Top of Stack (TOS)

is loaded in the PC. Interrupts

are enabled by setting Global

Interr upt Enab le bit , GIE

(INTCON<7>). This is a two-

cycle instruction.

Words: 1

Cycles: 2

Example RETFIE

After Interrupt

PC = TOS

GIE = 1

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RETLW Return with Literal in W

Syntax : [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 11 01xx kkkk kkkk

Description: The W register is loaded with

the eight bit literal ‘k’. The

program counter is loaded from

the top of the stack (the return

address). This is a two-cycle

instruction.

Words: 1

Cycles: 2

Example

TABLE

CALL TABLE;W contains table

;offset value

• ;W now has table value

•

ADDWF PC;W = offset

RETLW k1;Begin table

RETLW k2;

•

RETLW kn; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax : [ label ] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Encoding: 00 0000 0000 1000

Description: Return from subroutine. The

stack is POPed and the top of

the stack (TOS) is loaded into

the program counter. This is a

two-cycle instruction .

Words: 1

Cycles: 2

Example RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Stat us Af fe cte d: C

Encoding: 00 1101 dfff ffff

Description: The conte nts of regist er ‘f’ are

rotated one bit to the left through

the Carr y Flag. If ‘d’ is 0 the result

is plac ed in the W register. If ‘d’ is

1 the result is stored back in

Words: 1

Cycles: 1

Example RLF REG1, 0

Before Instruc tio n

REG1=1110 0110

C=0

After Instruction

REG1=1110 0110

W= 1100 1100

C=1

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RRF Rotate Right f through Carry

Syntax : [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1100 dfff ffff

Desc ript ion : The conten t s of regi ste r ‘f’ are

rotated one bit to the right

through th e Carry Flag . If ‘d’ is 0

the result is placed in the W

plac ed back in register ‘f’.

Words: 1

Cycles: 1

Example RRF REG1, 0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 0111 0011

C=0

SLEEP

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0011

Description: The power-down Status bit, PD

is cleared. Time out Status bit,

TO is set. Wat chdog T imer and

it s pres ca ler are cleare d.

The processor is put into Sleep

mode with the oscillator

stopped. See Section 14.8

"Power-Down Mo de (Sleep)"

for more details.

Words: 1

Cycles: 1

Example: SLEEP

SUBLW Subtract W from Literal

Syntax : [ label ]SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status

Affected: C, DC, Z

Encoding: 11 110x kkkk kkkk

Description: The W register is subtracted (2’s

complement method) from the eight

bit literal ‘k’. The result is placed in

the W register.

Words: 1

Cycles: 1

Example 1: SUBLW 0x02

Before Instruction

W=1

C=?

After Instruction

W=1

C = 1; result is positive

Example 2: Before Instruction

W= 2

C=?

After Instruction

W= 0

C = 1; result is zero

Example 3: Before Instruction

W= 3

C= ?

After Instruction

W= 0xFF

C = 0; result is negati ve

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SUBWF Subtract W from f

Syntax : [ label ] SUBWF f, d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (dest)

Status

Affected: C, DC, Z

Encoding: 00 0010 dfff ffff

Description: Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is 0

the result is stored in the W register.

If ‘d’ is 1 the result is stored back in

Words: 1

Cycles: 1

Example 1: SUBWF REG1, 1

Before Instruc tio n

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C = 1; result is positive

DC = 1

Z=0

Example 2: Before Instruction

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C = 1; result is zer o

Z = DC = 1

Example 3: Before Instruction

REG1 = 1

W=2

C=?

After Instruction

REG1 = 0xFF

W=2

C = 0; result is negative

Z = DC = 0

SWAPF Swap Nibbles in f

Syntax : [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Stat us Af fe cte d: No ne

Encoding: 00 1110 dfff ffff

Description: The upper and lower nibbles of

registe r ‘f’ are e xchan ged. If ‘d’ is

0 the result is placed in W

placed in register ‘f’.

Words: 1

Cycles: 1

Example SWAPF REG1, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W = 0x5A

TRIS Load TRIS Register

Syntax: [ label ] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f;

Stat us Af fe cte d: None

Encoding: 00 0000 0110 0fff

Description: The instruction is supported for

code compatibility with the

PIC16C5X products. Since TRIS

registers are readable and

writable, the user can directly

address them.

Words: 1

Cycles: 1

Example To maint ain upward com patibil-

ity with future PICmicro®

products, do not use this

instruction.

PIC16F627A/628A/648A

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XORLW Exclusive OR Literal with W

Syntax : [ label ]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 11 1010 kkkk kkkk

Description: The contents of the W register

are XOR’ed with the eight bit

liter al ‘k’. The result is placed in

the W register.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruction

W=0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax : [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Stat us Af fe cte d: Z

Encoding: 00 0110 dfff ffff

Descri ption: Exclusive OR the contents of th e

W register with register ‘f’. If ‘d’ is

0 the result is stored in the W

stored back in regist er ‘f’.

Words: 1

Cycles: 1

Example XORWF REG1, 1

Before Instruction

REG1 = 0xAF

W=0xB5

After Instruction

REG1= 0x1A

W=0xB5

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16.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a

full ran ge of hardware a nd softwa re develo pment to ols:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB C30 C Compiler

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Sim ulator

- MPLAB dsPIC30 Software Simulator

•Emulators

- MPLAB ICE 2000 In -Circuit Emulator

- MPLAB ICE 4000 In -Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

-PRO MATE

® II Universal Device Progr a mm er

- PICSTART® Plus Development Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM.netTM De monstration Board

- PICDEM 2 Plus Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board

- PICDEM 18R Demonstration Board

- PICDEM L IN Demo nstration Board

- PICDEM USB Demonstration Board

• Evaluation Kits

-K

EELOQ®

- P ICDEM MSC

-microID

-CAN

- PowerSmart®

-Analog

16.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

based application that contains:

• An interface to deb ugging tools

- simulator

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Exten si ve on-l in e help

The MPLAB IDE allows you to:

• Edit your sour ce files (either assemb ly or C)

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- source files (as sembl y or C)

- mixed assembly and C

- machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve whe n upgrading to tools with increasin g flexibi lity

and power.

16.2 MPASM Assembler

The MPASM assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

The MPASM assembler generates relocatable object

files for the MPLINK object linker, Intel® standard hex

files, MAP files to detail memory usage and symbol

refe rence, absol ute LST fi les th at contain sourc e lines

and generated machine code and COFF files for

debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects

• User de fined m acros to strea mline asse mbly cod e

• Condit ion al as sem bl y for mult i-p urpo se sourc e

files

• Directives that allow complete control over the

assembly p rocess

PIC16F627A/628A/648A

DS40044B-page 126 Preliminary  2004 Microchip Technology Inc.

16.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

16.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can link

relocatable objects from precompiled libraries, using

directives from a linker sc ript.

The MPLIB object librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement , deletion and extr action

16.5 MPLAB C30 C Compiler

The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard

ANSI C programs into dsPIC30F assembly language

source. The compiler also supports many command

line options and language extensions to take full

adv antage of the dsPIC 30F dev ice ha rdwar e capab ili-

ties and afford fine control of the compiler code

generator.

MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been

validated and conform to the ANSI C library standard.

The library includes functions for string manipulation,

dynamic memory allocation, data conversion, time-

keepin g and math func tions (trigonome tric, expone ntial

and hyperbolic). The compiler provides symbolic

information for high-level source debugging with the

MPLAB IDE.

16.6 MPLAB ASM30 Assembler, Linker

and Librarian

MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 compiler uses the

assembler to produce it’s object file. The assembler

generates relocatable object files that can then be

archived or lin ked with other relocatable ob ject files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

16.7 MPLAB SIM Software Simulator

The MPLAB SIM sof tware simulat or allows code deve l-

opment in a PC hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or use r de fined key p ress, to any pin. The exec u-

tion can be performed in Single-Step, Execute Until

Break or Trace mode.

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and MPLAB C18

C Compilers, as well as the MPASM assembler. The

software simulator offers the flexibility to develop and

debug code outside of the laboratory environment,

making it an excellent, economical software

development tool.

16.8 MPLAB SIM30 Software Simulator

The MPLAB SIM30 software simulator allows code

develop ment in a PC hosted en vironment by simulating

the dsPIC30F series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolic

debugging using the MPLAB C30 C Compiler and

MPLAB ASM30 assembler . The simulator runs in either

a Command Line mode for automated tasks, or from

MPLAB IDE. This high-speed simulator is designed to

debug, analyze and optimize time intensive DSP

routines.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 127

PIC16F627A/628A/648A

16.9 MPLAB ICE 2000

High-Performance Universal

In-Circui t Emu lator

The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers. Software control of the

MPLAB ICE 2000 in-circuit emulator is advanced by

the MPLAB Integrated Development Environment,

which all ows ed iting, b uildin g, do wnlo ading and sourc e

debuggi ng from a singl e envi ronm en t.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

featur es. Interchangea ble processo r modules al low the

system to be easi ly reconfi gured for emula tion of d iffer-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

16.10 MPLAB ICE 4000

High-Performance Universal

In-Circui t Emu lator

The MPLAB ICE 4000 universal in-circuit emulator is

intended to provide the product development engineer

with a co mplete micro controller de sign tool se t for high-

end PICm icro microcontrollers. Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debuggi ng from a singl e envi ronm en t.

The MPLAB ICD 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, up to 2 Mb of emulation memory and the

ability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

16.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash

PICmicro MCUs and can be used to develop for these

and other PICmicro microcontrollers. The MPLAB

ICD 2 utilizes the in-circuit debugging capability built

into the Flash devices. This feature, along with

Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)

protocol , offe rs cost ef fective i n-circuit Flash debug ging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by setting

breakpoints, single-stepping and watching variables,

CPU status and peripheral registers. Running at full

speed enables testing hardware and applications in

real-tim e. MPLAB ICD 2 also serves as a devel opment

programmer for selected PICmicro devices.

16.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maxi mum reli abili ty. It features

an LCD display for instructions and error messages

and a modular detachable socket assembly to support

various package types. In Stand-Alone mode, the

PRO MATE II device programmer can read, verify and

program PICmicro devices without a PC connection. It

can also set code protection in this mode.

16.13 MPLAB PM3 Device Programmer

The MPLAB PM3 is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maxi mum reli abili ty. It features

a large LCD display (128 x 64) for menus and error

messages and a modular detachable socket assembly

to support various package types. The ICSP™ cable

assembly is included as a standard item. In Stand-

Alone mode , the M PLAB PM3 devi ce pr ogra mmer ca n

read, verify and program PICmicro devices without a

PC connection. It can also set code protection in this

mode. MPLAB PM3 connects to the host PC via an

RS-232 or USB cable. MPLAB PM3 has high-speed

communications and optimized algorithms for quick

programming of large memory devices and incorpo-

rates an SD/M MC ca rd for file st orage an d secu re dat a

applications.

PIC16F627A/628A/648A

DS40044B-page 128 Preliminary  2004 Microchip Technology Inc.

16.14 PICSTART Plus Development

Programmer

The PICSTART Plus development programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus development programmer supports

most PICmicro devices up to 40 pins. Larger pin count

devices, such as the PIC16C92X and PIC17C76X,

may be supported with an adapter socket. The

PICSTART Plus development programmer is CE

compliant.

16.15 PICDEM 1 PICmicro

Demonstration Board

The PICDEM 1 demo nstrat ion boa rd demo nstrate s the

capabilities of the PIC16C5X (PIC16C54 to

PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,

PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All

necessary hardware and software is included to run

basic demo programs. The sample microcontrollers

provi d ed wi t h the P IC DE M 1 de mo ns t rat i on b oar d c an

be pro gramme d with a PRO MATE II devic e progra m-

mer or a PICSTART Plus development programmer.

The PICDE M 1 demonstrati on board can be conne cted

to the MPLAB ICE in-circuit emulator for testing. A

proto type area extends the ci rcuitry for a dditio nal appli-

cation components. Features include an RS-232

interface, a potentiometer for simulated analog input,

push button switches and eight LEDs.

16.16 PICDEM.net Internet/Ethernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/

Ethernet demonstration board using the PIC18F452

microcontroller and TCP/IP firmware. The board

supports any 40-pin DIP device that conforms to the

standard pinout used by the PIC16F877 or

PIC18C452. This kit features a user friendly TCP/IP

stack, web server with HTML, a 24L256 Serial

EEPROM for Xmodem download to web pages into

Serial EEPROM, ICSP/MPLAB ICD 2 interface con-

nector, an Ethernet interface, RS-232 interface and a

16 x 2 LCD display. Also included is the book and

CD-ROM “TCP/IP Lean, Web Servers for Embedded

Systems,” by Jeremy Bentham

16.17 PICDEM 2 Plus

Demonstration Board

The PICDEM 2 Plus demonstration board supports

many 18, 28 and 40-pin microcontrollers, including

PIC16F87X and PIC18FXX2 devices. All the neces-

sary ha rdware and s oftware is included to run the dem-

onstration programs. The sample microcontrollers

provided with the PICDEM 2 demonstration board can

be programmed with a PRO MATE II device program-

mer, PICSTART Plus development programmer, or

MPLAB ICD 2 with a Universal Programmer Adapter.

The MPLAB I CD 2 and MPLAB ICE in-circuit emul ators

may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area extends the

circuitry for additional application components. Some

of the features include an RS-232 interface, a 2 x 16

LCD display , a piezo speaker, an on-board temperatu re

sensor, four LEDs and sample PIC18F452 and

PIC16F877 Flash microcontrollers.

16.18 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All

the necessary hardware and software is included to run

the demonstration programs.

16.19 PICDEM 4 8/14/18-Pin

Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-

bilities of the 8, 14 and 18-pin PIC16XXXX and

PIC18XXXX MCUs, including the PIC16F818/819,

PIC16F87/88, PIC16F62XA and the PIC18F1320

family of microcontrollers. PICDEM 4 is intended to

showcase the many features of these low pin count

parts, including LIN and Motor Control using ECCP.

Special provisions are made for low-power operation

with the supercapacitor circuit and jumpers allow on-

board hardware to be disabled to eliminate current

draw in this mode. Included on the demo board are pro-

visions for Crystal, RC or Canned Oscillator modes, a

five volt regulator for use with a nine volt wall adapter

or battery, DB-9 RS-232 interface, ICD connector for

programming via ICSP and development with MPLAB

ICD 2, 2 x 16 liquid crystal display, PCB footprints for

H-Bridge motor driver, LIN transceiver and EEPROM.

Also included are: header for expansion, eight LEDs,

four potentiometers, three push buttons and a proto-

typing are a. Inc lud ed with the kit is a PIC16F6 27A and

a PIC18F1 320. Tutoria l firmwar e is inc luded along wi th

the User’s Guide.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 129

PIC16F627A/628A/648A

16.20 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. A

programmed sample is included. The PRO MATE II

device programmer, or the PICSTART Plus develop-

ment programmer, can be used to reprogram the

device for user tailored application development. The

PICDEM 17 demonstration board supports program

download and execution from external on-board Flash

memory. A generous prototype area is available for

user hardware expans ion.

16.21 PICDEM 18R PIC18C601/801

Demonstration Board

The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip

microcontrollers. It provides hardware implementation

of both 8-bit Multiplexed/Demultiplexed and 16-bit

Memory modes. The board includes 2 Mb external

Flash memory and 128 Kb SRAM memory, as well as

serial EEPROM, allowing access to the wide range of

memory types supported by the PIC18C601/801.

16.22 PICDEM LIN PIC16C43X

Demonstration Board

The pow erfu l LI N hard w are a nd s of tw are kit includes a

series of boards and three PICmicro microcontrollers.

The small footprint PIC16C432 and PIC16C433 are

used as slaves in the LIN communication and feature

on-board LIN transceivers. A PIC16F874 Flash

microcontroller serves as the master. All three micro-

controllers are programmed with firmware to provide

LIN b us communication.

16.23 PICkitTM 1 Flash Starter Kit

A complete “development system in a box”, the PICkit

Flash Starter Kit includes a convenient multi-section

board for p rogramming, evaluation a nd development of

8/14-pin Flash PIC® microcontrollers. Powered via

USB, the board operates under a simple Windows GUI.

The PICk it 1 Starter Kit includes the User’s Guide (on

CD ROM), PICkit 1 tutorial software and code for

various applications. Also included are MPLAB® IDE

(Integrated Development Environment) software,

software and hardware “Tips 'n Tricks for 8-pin Flash

PIC® Microcontrollers” Handbook and a USB interface

cable. Supports all current 8/14-pin Flash PIC

microcontrollers, as well as many future planned

devices.

16.24 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM U SB Demo ns trati on Board sho w s o f f th e

capabilities of the PIC16C745 and PIC16C765 USB

microcontrollers. This board provides the basis for

future USB products.

16.25 Evaluation and

Programming Tools

In additio n to the PICDEM seri es of circuits, Microchip

has a line of evaluation kits and demonstration software

for the se products.

•K

EELOQ evaluation and prog ram mi ng too ls for

Microchip’s HCS Secure Data Products

• CAN developers kit for automotive network

applications

• Analog design boards and filter design software

• PowerS mart battery charging evaluation/

calibration kits

•IrDA

® development kit

• microID development and rfLabTM development

software

• SEEVAL® designer kit for memory ev al uat ion an d

endurance calculations

• PICDEM MSC demo boards for Switching mode

power supply, high-power IR driver, delta sigma

ADC and flow rate sensor

Check the Microchip web page and the latest Product

Selector Guide for the complete list of demonstration

and evaluation kits.

PIC16F627A/628A/648A

DS40044B-page 130 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 131

PIC16F627A/628A/648A

17.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings(†)

Ambient temperature under bias.................................................................................................................-40 to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Volt a ge on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V

Volt a ge on MCLR and RA4 with respect to VSS ............................................................................................-0.3 to +14V

Voltage on all other pins with respect to VSS ....................................................................................-0.3V to VDD + 0.3V

Total power diss ipation(1) .....................................................................................................................................800 mW

Maximum curr ent out of VSS pin ...........................................................................................................................300 mA

Maximum curr ent into VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp cur rent, IOK (Vo < 0 or Vo >VDD)...............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum curr ent sunk by PORTA and PORTB (Combined)................................................................................200 mA

Maximum current sourced by PORTA and PORTB (Combined)...........................................................................200 mA

Note 1: Power dissipation is calcu la ted as follow s: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resi stor of 50 -100 Ω should be used wh en applying a “low” level to the MCLR pi n rathe r than

pulling this pin direct ly to VSS.

PIC16F627A/628A/648A

DS40044B-page 132 Preliminary  2004 Microchip Technology Inc.

FIGURE 17-1: PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

FIGURE 17-2: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

FREQUENCY (MHz)

VDD

(VOLTS)

Note: The shaded region indicates the permissible combinations of voltage and frequency.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

FREQUENCY (MHz)

VDD

(VOLTS)

2.0

Note: The shaded region indicates the permissible combinations of voltage and frequency.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 133

PIC16F627A/628A/648A

17.1 DC Characteri stics: PIC16F627A/628A/648A (Indus trial, Extended)

PIC16LF627A/628A/648A (Industrial)

PIC16LF627A/628A/648A

(Industrial) Stan dard Operating Condi tions (unless otherwise stated)

Operating temperature -40°C ≤ Ta ≤ +85°C for industrial

PIC16F627A/628A/648A

(Industrial, Extended)

Stan dard Operating Co nditions (unless otherwise stated)

Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and

-40°C ≤ Ta ≤ +125°C for extended

Param

No. Sym Characteristic/Device Min Typ† Max Units Conditions

VDD Supply Voltage

D001 PIC16LF627A/628A/648A 2.0 — 5.5 V

PIC16F627A/628A/648A 3.0 —5.5 V

D002 VDR RAM Data Retention

Voltage(1) — 1.5* — V Device in Sleep mode

D003 VPOR VDD Start Voltage

to ensure Power-on Reset —VSS —VSee Section 14.4 on Power-on

Reset for details

D004 SVDD VDD Rise Rate

to ensure Power-on Reset 0.05* — — V/ms See Section 14.4 on Power-on

Reset for details

D005 VBOR Brown-out Reset Vo ltage 3.65

3.65 4.0

4.0 4.35

4.4 V

VBOREN configuration bit is set

BOREN configuration bit is set,

Extended

Legend: Rows with standard voltage device data only are shaded for improved readability.

* These parameters are characterized but not tested.

† Data in “Ty p” column is at 5. 0 V, 25°C, unless otherwise stated. These parameters a re for design guidance only and are

not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

PIC16F627A/628A/648A

DS40044B-page 134 Preliminary  2004 Microchip Technology Inc.

17.2 DC Characteristics: PIC16F627A/628A/648A (Indust rial)

PIC16LF627A/628A/648A (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ Ta ≤ +85°C for industrial

Param

No. LF and F Devi c e

Characteristics Min† Typ Max Units Conditions

VDD Note

Supply Voltage (VDD)

D001 LF 2.0 — 5.5 V —

LF/F 3.0 — 5.5 V —

Power-down Base Current (IPD)

D020 LF — 0.1 0.80 µA 2.0 WDT, BOR, Comparators, VREF, and

T1OSC: disabled

LF/F — 0.1 0.85 µA3.0

—0.22.7 µA5.0

Peripheral Module Current (∆IMOD)(1)

D021 LF —12.0µA 2. 0 WDT Current

LF/F —23.4µA3.0

— 9 17.0 µA5.0

D022 LF/F —32TBDµA 4.5 BOR Current

—33TBDµA5.0

D023 LF —15TBDµA 2. 0 Comparator Current

LF/F —27TBDµA3.0

—49TBDµA5.0

D024 LF —34TBDµA2.0VREF Current

LF/F —50TBDµA3.0

—80TBDµA5.0

D025 LF —1.22.0 µA2.0T1OSC Current

LF/F —1.32.2 µA3.0

—1.82.9 µA5.0

Supply Cu r r e nt (IDD)

D010 LF —1215 µA2.0FOSC = 32 kHz

LP Oscillator Mode

LF/F —2125 µA3.0

—3848 µA5.0

D011 LF — 130 190 µA2.0FOSC = 1 MHz

XT Oscillator Mode

LF/F — 220 340 µA3.0

— 370 520 µA5.0

D012 LF — 270 350 µA2.0FOSC = 4 MHz

XT Oscillator Mode

LF/F — 430 600 µA3.0

— 780 995 µA5.0

D013 LF/F — 2.6 2.9 mA 4.5 FOSC = 20 MHz

HS Oscillator Mode

—33.3mA5.0

Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be added to the

base IDD or IPD measurement. Max values should be used when calculating total current consumption.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 135

PIC16F627A/628A/648A

17.3 DC Characteristics: PIC16F627A/628A/648A (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ Ta ≤ +125°C for extended

Param

No. Device Characteristics Min† Typ Max Units Conditions

VDD Note

Supply Voltage (VDD)

D001 — 3.0 — 5.5 V —

Power-down Base Current (IPD)

D020E — —0.1TBDµA 3.0 WDT, BOR, Comparators, VREF, and

T1OSC: disabled

—0.2TBDµA5.0

Peripheral Module Current (∆IMOD)(1)

D021E — —2TBDµA 3.0 WDT Current

—9TBDµA5.0

D022E — —32TBDµA 4.5 BOR Current

—33TBDµA5.0

D023E — —27TBDµA 3.0 Com parator Current

—49TBDµA5.0

D024E — —50TBDµA3.0V

REF Current

—83TBDµA5.0

D025E — —1.3TBDµA3.0T1O

SC Current

—1.8TBDµA5.0

Supply Cu r r e nt (IDD)

D010E — —21TBDµA3.0F

OSC = 32 kHz

LP Oscillator Mode

—38TBDµA5.0

D011E — — 220 TBD µA3.0F

OSC = 1 MHz

XT Oscillator Mode

— 370 TBD µA5.0

D012E — — 430 TBD µA3.0F

OSC = 4 MHz

XT Oscillator Mode

— 780 TBD µA5.0

D013E — — 2.6 TBD mA 4.5 FOSC = 20 MHz

HS Oscillator Mode

—3TBDmA5.0

Note 1: The “∆” current is the additional current consumed when this peripheral is enabled. This current should be added to the

base IDD or IPD measurement. Max values should be used when calculating total current consumption.

PIC16F627A/628A/648A

DS40044B-page 136 Preliminary  2004 Microchip Technology Inc.

17.4 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)

PIC16LF627A/628A/648A (Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operatin g temperature -40°C ≤ TA ≤ +85°C for industrial and

-40°C ≤ TA ≤ +125°C for extended

Operatin g voltage VDD range as described in DC spec T able 17-2 and Table 17-3

Param.

No. Sym Characteristic/Device Min Typ† Max Unit Conditions

VIL Input Low Vol tage

D030

D031

D032

D033

I/O ports

wit h TT L buffe r

with Schmitt Trigger input(4)

MCLR, RA4/T0CKI,OSC1

(in RC mode)

OSC1 (in HS)

OSC1 (in LP and XT)

VSS

—

0.8

0.15 VDD

0.2 VDD

0.3 VDD

0.8

VDD = 4.5V to 5.5V

otherwise

(Note1)

VIH Input High Voltage

D040

D041

D042

D043

D043A

I/O ports

with TTL buffer

with Schmitt Trigger input(4)

MCLR RA4/T0CKI

OSC1 (XT, HS and LP)

OSC1 (in RC mode)

2.0 V

.25 VDD + 0. 8 V

0.8 VDD

0.7 VDD

0.9 VDD

—

VDD

VDD = 4.5V to 5.5V

otherwise

(Note1)

D070 IPURB PORTB weak pull-up

current 50 200 400 µAVDD = 5.0V, VPIN = VSS

IIL Input Leakage Current(2), (3)

D060

D061

D063

I/O por ts (Exc ep t PO RTA)

PORTA(4)

RA4/T0CKI

OSC1 , M CLR

—

±1.0

±0.5

±1.0

±5.0

µA

VSS ≤ VPIN ≤ VDD, pin at hi-impedanc e

VSS ≤ VPIN ≤ VDD, pin at hi-impedance

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD, XT, HS and LP osc

configuration

VOL Output Low Voltage

D080 I/O ports(4) —

——

—0.6

0.6 V

VIOL=8.5 mA, VDD=4.5 V, -40° to +85°C

IOL=7.0 mA, VDD=4.5 V, +85° to +125°C

VOH Outpu t High Voltage (3)

D090 I/O po r ts (Exc ep t R A4 (4) VDD-0.7

VDD-0.7 —

——

—V

VIOH=-3.0 mA, VDD=4.5 V, -40° to +85°C

IOH=-2.5 mA, VDD=4.5 V, +85° to

+125°C

D150 VOD Open-Drain High Voltage — — 8.5* V RA4 pin PIC16F627A/628A/648A,

PIC16LF627A/628A/648A

Capacitive Loading Spec s on Output Pins

D100*

D101*

COSC2

Cio

OSC2 pin

All I/O pins/OSC2 (in RC mode)

—

In XT, HS and LP modes when external

clock used to drive OSC1.

* These p arameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: In RC oscillato r configuration, the OSC1 pin is a Schmitt Trigger input . It is not recommended that the PIC16F 627A/628A/648 A be

driven wit h ex ternal clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on applied vo ltage level. The specified levels repres ent normal operat i ng

conditions. Higher leaka ge current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

4: Includ es OSC1 and OSC2 when configured as I/O pins, CLKIN, or CLK OUT.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 137

PIC16F627A/628A/648A

TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)

PIC16LF627A/628A/648A (Industrial)

DC Characteristics St andard Operating Conditions (unless otherwise sta ted)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

-40°C ≤ TA ≤ +125°C for extended

Operating voltage VDD range as described in DC sp ec Table 17-2 and Table 17-3

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

Data EEPROM Memory

D120

D120A

D121

D122

D123

D124

VDRW

TDEW

TRETD

TREF

Endurance

VDD for read/write

Erase/Write cycle time

Characteristic Retention

Number of Total Erase/Write

Cycles before Refresh(1)

100K

10K

VMIN

—

100

100K

—

10M

—

5.5

—

E/W

Year

E/W

-40°C ≤ TA ≤ 85°C

85°C ≤ TA ≤ 125°C

VMIN = Minimum ope rati ng

voltage

Provided no other

specifications are violated

-40°C to +85°C

Program Flash Memory

D130

D130A

D131

D132

D132A

D133

D133A

D134

VPR

VIE

VPEW

TIE

TPEW

TRETP

Endurance

VDD for read

VDD for Block erase

VDD for write

Block Erase cycle time

Write cycle time

Characteristic Retention

10K

1000

VMIN

4.5

VMIN

—

100

100K

10K

—

5.5

—

E/W

year

-40°C ≤ TA ≤ 85°C

85°C ≤ TA ≤ 125°C

VMIN = Minimum ope rati ng

voltage

VMIN = Minimum ope rati ng

voltage

VDD > 4.5V

Provided no other

specifications are violated

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0 V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: Refer to Section 13.7 "Using the Data EEPROM" for a more detailed discussion on data EEPROM

endurance.

PIC16F627A/628A/648A

DS40044B-page 138 Preliminary  2004 Microchip Technology Inc.

TABLE 17-2: COMPARATOR SPECIFICATIONS

TABLE 17-3: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 2.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated.

Param

No. Characteristics Sym Min Typ Max Units Comments

D300 Input Of fset Volt a ge VIOFF —±5.0 ±10 mV

D301 Input Common Mode Voltage VICM 0—VDD - 1.5* V

D302 Common Mode Rejection Ratio CMRR 55* — — db

D303 Re sponse Time(1) TRESP —

—

300

400

400*

600*

VDD = 3.0V to 5.5V

-40° to +85°C

VDD = 3.0V to 5.5V

-85° to +125°C

VDD = 2.0V to 3.0V

-40° to +85°C

D304 Comp arator Mode Change to

Output Valid TMC2OV — 300 10* µs

* These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from

VSS to VDD.

Operating Conditions: 2.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.

Spec

No. Characteristics Sym Min Typ Max Units Comments

D310 Resolution VRES ——VDD/24

VDD/32 LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

D311 Absolute Accuracy VRAA —

——

—1/4(2)*

1/2(2)*LSb

LSb Low Range (VRR = 1)

High Range (VRR = 0)

D312 Unit Resistor Value (R) VRUR —2k*— Ω

D313 Settling Time(1) TSET ——10*µs

* These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

2: When VDD is between 2.0V and 3.0V the VREF output voltage levels on RA2 described by the

equation:[VDD/2 ± (3-VDD)/2] may cause the Absolu te Accuracy (VRAA) of the VREF outpu t sign al on R A2 to

be greater than the stated max.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 139

PIC16F627A/628A/648A

17.5 Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

FIGURE 17-3: LOAD CONDITIONS

1. TppS2ppS

2. TppS

TF Frequency T Time

Lowercase subscripts (pp) and their meanings:

ppck CLKOUT osc OSC1

io I/O port t0 T0CKI

mc MCLR

Uppe rcase letters and their meanings :

SFFall P Period

HHigh R Rise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-Impedance

VDD/2

PIN PIN

VSS VSS

RL=464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

LOAD CONDITION 1 LOAD CONDITION 2

PIC16F627A/628A/648A

DS40044B-page 140 Preliminary  2004 Microchip Technology Inc.

17.6 Timing Diagrams and Specifications

FIGURE 17-4: EXTERNAL CLOCK TIMING

TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

Fosc External CLKIN Frequ enc y(1) DC — 4 MHz XT and RC Osc mo de,

VDD = 5.0 V

DC — 20 MHz HS, EC Osc mode

DC — 200 kHz LP Osc mode

Oscillator Frequency(1) — — 4 MHz RC Osc mode, VDD = 5.0V

0.1 — 4 MHz XT Osc mode

——

—20

200 MHz

kHz HS Osc mode

LP Osc mode

— 4 — MHz INTOSC mode (fast)

— 37 — kHz INTOSC mode (slow)

1 Tosc External CLKIN Period (1) 250 — — ns XT and RC Osc mode

50 — — ns HS, EC Osc mode

5——µsLP Osc mode

Oscillator Period(1) 250 — — ns RC Osc mode

250 — 10,000 ns XT Osc mode

50 — 1,000 ns HS Osc mode

5——µsLP Osc mode

— 250 — ns INTOSC mode (fast)

—27—µs INTOSC mode (slow)

2 Tcy Instruction Cycle Time 200 TCY DC ns TCY = 4/FOSC

3 TosL,

TosH Extern al CLKIN (OSC1) High

External CLKIN Low 100* — — ns XT oscillator, TOSC L/H duty

cycle

4 RC External Biased RC Fre-

quency 10 kHz* — 4 MHz — VDD = 5 .0V

* These parameters are characterized but not tested.

† Data in “T yp” column is at 5.0V, 25°C unless otherwise sta ted. These parameters are for design guidance only

and are not tested.

Note: Instruction cycle period (Tcy) equals four times the input oscillator time-based period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at “Min” values

with an ex te rnal clo ck appl ie d to the OSC1 pi n. Wh en an exte rna l cl ock inp ut is use d, th e “Ma x” cy cl e tim e

limit is “DC” (no clock) for all devices.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

133

 2004 Microchip Technology Inc. Preliminary DS40044B-page 141

PIC16F627A/628A/648A

TABLE 17-5: PRECISION INTERNAL OSCILLATOR PARAMETERS

FIGURE 17-5: CLKO UT AND I/O TIMING

Parameter

No. Sym Characteristic Min Typ Max Units Conditions

F10 FIOSC Oscillator Center frequency —4—MHz

F13 ∆IOSC Oscillator Stability (jitter) ——±1%V

DD = 3.5 V, 25°C

——±2 % 2.0 V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C

——±5 % 2.0 V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (IND)

-40°C ≤ TA ≤ +125°C (EXT)

F14 TIOSCST Oscillator Wake-up from Sleep

start-up time —6TBDµsV

DD = 2.0V, -40°C to +85°C

—4TBDµsVDD = 3.0V, -40°C to +85°C

—3TBDµsV

DD = 5.0V, -40°C to +85°C

OSC1

CLKOUT

I/O PIN

(INPUT)

I/O PIN

(OUTPUT)

Q4 Q1 Q2 Q3

20, 21

19 18

OLD VALUE NEW VALUE

PIC16F627A/628A/648A

DS40044B-page 142 Preliminary  2004 Microchip Technology Inc.

TABLE 17-6: CLKOUT AND I/O TI MING REQUIREMENTS

FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMI NG

Parameter

No. Sym Characteristic Min Typ† Max Units

10 TosH2ckL OSC1↑ to CLKOUT↓ PIC16F62X — 75 200* ns

10A PIC16LF62X — — 400* ns

11 TosH2ckH OSC1↑ to CLKOUT↑ PIC16F62X — 75 200* ns

11A PIC16LF62X — — 400* ns

12 TckR CLKOUT ris e time PIC1 6F62 X — 35 100* ns

12A PIC16LF62X — — 200* ns

13 TckF CLKOUT fall time PIC16F62X — 35 100* ns

13A PIC16LF62X — — 200* ns

14 TckL2ioV CLKOUT ↓ to Port out valid — — 20* ns

15 TioV2ckH Port in valid before CLKOUT ↑PIC16F62 X Tosc+200 ns* — — ns

PIC16LF62X Tosc+400 ns* — — ns

16 TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns

17 TosH2ioV OSC1↑ (Q1 cycle) to PIC16F62X — 50 150* ns

Port out valid PIC16LF62X — — 300* ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time) 100*

200* ——ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

VDD

MCLR

Internal

POR

PWRT

Time out

OST

Time out

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

 2004 Microchip Technology Inc. Preliminary DS40044B-page 143

PIC16F627A/628A/648A

FIGURE 17-7: BROWN-OUT DETECT TIMING

TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER REQUIREMENTS

FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse W idth (low) 2000

TBD —

TBD ns

ms VDD = 5V, -40°C to +85°C

Extended temperature

31 Twdt Watchdog Tim er Time out Period

(No Prescaler) 7*

TBD 18

TBD 33*

TBD ms

ms VDD = 5V, -40°C to +85°C

Extended temperature

32 Tost Oscillation St art-up Timer Period — 1024TOSC ——TOSC = OSC1 period

33 Tpwrt Power-up Timer Period 28*

TBD 72

TBD 132*

TBD ms

ms VDD = 5V, -40°C to +85°C

Extended temperature

34 TIOZ I/O Hi-impedance from MCLR Low

or Wat chdog Timer Reset — — 2.0* µs

35 TBOR B rown-out Reset pulse width 100* — — µsVDD ≤ VBOR (D005)

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD VBOR

RA4/T0CKI

RB6/T1OSO/T1CKI

TMR0 OR

TMR1

PIC16F627A/628A/648A

DS40044B-page 144 Preliminary  2004 Microchip Technology Inc.

TABLE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

FIGURE 17-9: CAP TURE/COMPARE/PWM TIMINGS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period Greater of:

TCY + 40*

— — ns N = prescale

value (2, 4, ...,

256)

45 Tt1H T1CKI High

Time Synchronous, No Prescaler 0.5TCY + 20* — — ns

Synchronous,

with Prescaler PIC16F62X 15* — — ns

PIC16LF62X 25* — — ns

Asynchronous PIC16F62X 30* — — ns

PIC16LF62X 50* — — ns

46 Tt1L T1CKI Low

Time Synchronous, No Prescaler 0.5TCY + 20* — — ns

Synchronous,

with Prescaler PIC16F62X 15* — — ns

PIC16LF62X 25* — — ns

Asynchronous PIC16F62X 30* — — ns

PIC16LF62X 50* — — ns

47 Tt1P T1CKI input

period Synchronous PIC16F62X Greater of:

TCY + 40*

— — ns N = prescale

value (1, 2, 4, 8)

PIC16LF62X Greater of:

TCY + 40*

———

Asynchronous PIC16F62X 60* — — ns

PIC16LF62X 100* — — ns

Ft1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN) — 32.7(1) —kHz

48 TCKEZt

mr1 Delay from external clock edge to timer

increment 2Tosc — 7Tosc —

* These parameters are chara cte riz ed but not tested .

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This os cillator i s intended t o work on ly with 32. 768 kHz watch c rysta ls and th eir manufactu red toleran ces.

Higher value crystal frequencies may not be compatible with this crystal driver.

(CAPTURE MODE)

50 51

53 54

RB3/CCP1

(COMPARE OR PWM MODE)

RB3/CCP1

 2004 Microchip Technology Inc. Preliminary DS40044B-page 145

PIC16F627A/628A/648A

TABLE 17-9: CAPTURE/COMPARE/PWM REQUIREMENTS

FIGURE 17-10: TIMER0 CLOCK TIMING

TABLE 17-10: TIMER0 CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

50 TccL CCP

input low time No Prescaler 0.5TCY + 20* — — ns

With Prescaler PIC16F62X 10* — — ns

PIC16LF62X 20* — — ns

51 TccH CCP

input high time No Prescaler 0.5TCY + 20* — — ns

With Prescaler PIC16F62X 10* — — ns

PIC16LF62X 20* — — ns

52 TccP CCP input period 3TCY + 40*

N— — ns N = prescale

value (1,4 or 16)

53 TccR CCP output rise time PIC16F62X 10 25* ns

PIC16LF62X 25 45* ns

54 TccF CCP output fall time PIC16F62X 10 25* ns

PIC16LF62X 25 45* ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5V, 25°C unless o t her wise stated. The se p ara meters are for desig n gu ida nc e on ly

and are not tested.

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns

With Prescaler 10* — — ns

42 Tt0P T0CKI Period TCY + 40*

N— — ns N = prescale value

(1, 2, 4, ..., 256)

* These parameters are characterized but not tested.

† Data in “T yp” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

RA4/T0CKI

TMR0

PIC16F627A/628A/648A

DS40044B-page 146 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 147

PIC16F627A/628A/648A

18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

Not Available at this time.

PIC16F627A/628A/648A

DS40044B-page 148 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 149

PIC16F627A/628A/648A

19.0 PACKAGING INFORMATION

19.1 Package Marking Information

* S t anda rd PICmic ro devic e marking consi sts of Micro chip pa rt num ber, ye ar code, week cod e, and trac eabili ty code.

For PICmicro device marking beyond this, cer tain price adders apply. Please check with your Microchip Sales Office.

For QTP devices, any special marking adders are included in QTP price.

20-LEAD SSOP

18-LEAD SOIC (.300")

18-LEAD PDIP (.30 0")

EXAMPLE

28-LEAD QFN

XXXXXXXX

YYWWNNN

EXAMPLE

XXXXXXXXXXXXXX

YYWWNNN

XXXXXXXXXXXXXX PIC16F627A-I/P

0210017

YYWWNNN

XXXXXXXXXXXX

0210017

PIC16F628A

YYWWNNN

XXXXXXXXXXX

XXXXXXXXXXX 0210017

PIC16F648A

16F628A

0210017

-I/ML

-E/SO

-I/SS

Legend: XX...X Customer specific information*

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Note: In the event th e full Mi crochip p ar t numbe r cannot be mar ked on on e line, it wil l be carri e

over to the n ext line thus limiting the number of avai lable characters for c us tom er s pec ifi

information.

PIC16F627A/628A/648A

DS40044B-page 150 Preliminary  2004 Microchip Technology Inc.

18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

1510515105

Mold Draft Angle Bottom 1510515105

Mold Draft Angle Top 10.929.407.87.430.370.310eBOverall Row Spacing § 0.560.460.36.022.018.014BLower Lead Width 1.781.461.14.070.058.045B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 22.9922.8022.61.905.898.890DOverall Length 6.606.356.10.260.250.240E1M ol d ed Packag e Width 8.267.947.62.325.313.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.683.302.92.145.130.115A2Molded Pa ckag e Thick ness 4.323.943.56.170.155.140ATop to Seating Plane 2.54.100

Pitch 1818

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-007

§ Significant Characteristic

 2004 Microchip Technology Inc. Preliminary DS40044B-page 151

PIC16F627A/628A/648A

18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.300.270.23.012.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 11.7311.5311.33.462.454.446DOverall Length 7.597.497.39.299.295.291E1M ol d ed Packag e Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088

Molded Pa ckag e Thick ness 2.642.502.36.104.099.093AOverall Height 1.27.050

Pitch 1818

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-051

§ Significant Characteristic

PIC16F627A/628A/648A

DS40044B-page 152 Preliminary  2004 Microchip Technology Inc.

20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840

Foot Angle 0.250.180.10.010.007.004

Lead Thickness 0.940.750.56.037.030.022LFoot Length 7.347.207.06.289.284.278DOverall Length 5.385.255.11.212.207.201

Molded Package Width 8.187.857.59.322.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026

Pitch 2020

Number of Pins MAXNOMMINMAXNOMMINDime nsion Limits MILLIMETERSINCHES*Units

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-150

Drawing No. C04-072

§ Significant Characteristic

 2004 Microchip Technology Inc. Preliminary DS40044B-page 153

PIC16F627A/628A/648A

28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN)

Lead Width

*Con tro ll ing Pa ra me ter

Notes:

Mold Draft Angle Top

.009

.011 .014 0.23

0.28 0.35

Pitch

Number of Pins

Overall Width

Standoff

Molded Package Length

Overall Length

Molded Package Width

Molded Package Thickness

Overall Height

MAX

Units

Dimension Limits

A.026

.236 BSC

.000

.226 BSC

INCHES

.026 BSC

MIN 28

NOM MAX

0.65

.031

.002 0.00

6.00 BSC

5.75 BSC

MILLIMETERS*

.039

MIN 28

0.65 BSC

NOM

0.80

0.05

1.00

EXPOSED

METAL

PADS

BOTTOM VIEW

.008 REF.Base Thickness A3 0.20 REF.

TOP VI EW

0.85.033

.0004 0.01

.236 BSC

.226 BSC 6.00 BSC

5.75 BSC

Lead Length

Tie Bar Width L .020.024.0300.500.600.75

R .005.007.0100.130.170.23

T ie Bar Length Q.012 .016 .026 0.30 0.40 0.65

Chamfer CH .009.017.0240.240.420.60

CH x 45

Exposed Pa d Width

Exposed Pa d Len gth .140 .146 .152 3.55 3.70 3.85

.140 .146 .152 3.55 3.70 3.85

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC equ i val en t: M0- 220

Drawing No. C04-114

PIC16F627A/628A/648A

DS40044B-page 154 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 155

PIC16F627A/628A/648A

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A

This is a new data sheet.

Revision B

Revis ed 28-Pin QF N Pin Diag ram

Revised Figure 5-4 Block Diagram

Revised Register 7-1 TMR1ON

Revised Example 13-4 Data EEPROM Refresh

Routine

Revised Instruction Set SUBWF, Example 1

Revised DC Characteri stic s 17-2 and 17-3

Revised Tables 17-4 and 17-6

Corrected Table and Figure numbering in Section 17.0

APPENDIX B: DEVICE

DIFFERENCES

The differences between the PIC16F627A/628A/648A

device s listed in this dat a sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Device

Memory

Flash

Program RAM

Data EEPROM

Data

PIC16F627A 1024 x 14 224 x 8 128 x 8

PIC16F628A 2048 x 14 224 x 8 128 x 8

PIC16F648A 4096 x 14 256 x 8 256 x 8

PIC16F627A/628A/648A

DS40044B-page 156 Preliminary  2004 Microchip Technology Inc.

APPENDIX C: DEVICE MIGRATIONS

This section describes the functional and electrical

specification differences when migrating between

functionally similar devices. (such as from a

PIC16F627 to a PIC16F627A).

C.1 PIC16F627/628 to a PIC16F627A/628A

1. ER mode is now RC mode.

2. Code Protection for the Program Memory has

change d from Cod e Pro tect se ction s of me mory

to Code Protect of the whole memory. The

Configuration bits CP0 and CP1 in the

PIC16F627/628 do not exist in the PIC16F627A/

628A. They have been replaced with one

Configuration bit<13> CP.

3. “Brown-out Detect (BOD)” terminology has

changed to “Brown-out Reset (BOR)” to better

represent the function of t he Brown-out circui try .

4. Enabling Brown-out Reset (BOR) does not

automatically enable the Power-up Timer

(PWRT) the way it did in the PIC16F627/628.

5. INTRC is now called INT OSC.

6. Timer1 Oscillator is now designed for

32.768 kHz operation. In the PIC16F627/628

the Timer1 Os cillator was designed to run up to

200 kHz.

7. The Dual Speed Oscillator mode only works in

the INT OSC Oscillator m ode. In the PIC16F62 7/

628 the Dual Speed Oscillator mode worked in

both the INTRC and ER Oscillator modes.

APPENDIX D: MIGRATING FROM

OTHER PICmicro

DEVICES

This discusses some of the issues in migrating from

other PICmicro devices to the PIC16F627A/628A/648A

family of devices.

D.1 PIC16C62X/CE62X to PIC16F627A/628A/

648A Migration

See Microchip web site for availability

(www.microchip.com).

D.2 PIC16C622A to PIC16F627A/628A/648A

Migration

See Microchip web site for availability

(www.microchip.com).

Note: This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performan ce c harac teristi cs than it s ea rlier

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

 2004 Microchip Technology Inc. Preliminary DS40044B-page 157

PIC16F627A/628A/648A

APPENDI X E: DEVELOPMENT

TOOL VERSION

REQUIREMENTS

This lists the minimum requirements (software/

firmware) of the specified development tool to support

the devices listed in this data sheet.

MPLAB® IDE: TBD

MPLAB® SIMULATOR: TBD

MPLAB® ICE 3000:

PIC16F627A/628A/648A Processor Module:

Part Number - TBD

PIC16F627A/628A/648A Device Adapter:

Socket Part Number

18-pin PDIP TBD

18-pin SOIC TBD

20-pin SSOP TBD

28-pin QFN TBD

MPLAB® ICD: TBD

PRO MATE® II: TBD

PICSTART® Plus: TBD

MPASMTM Assembler: TBD

MPLAB® C18 C Compiler: TBD

Note: Please read all associated README.TXT

files that are supplied with the develop-

ment tools. These “read me” files will

discuss product support and any known

limitations.

PIC16F627A/628A/648A

DS40044B-page 158 Preliminary  2004 Microchip Technology Inc.

NOTES:

 2004 Microchip Technology Inc. Preliminary DS40044B-page 159

PIC16F627A/628A/648A

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web site.

The web site is used b y Micr ochip as a me ans to mak e

files and information easily available to customers. To

view t he site, the user must have acce ss to the In ternet

and a web browser, such as Netscape® or Microsoft®

Internet Explorer. Files are also available for FTP

download from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available at the following

URL:

www.microchip.com

The file transfer site is available by using an FTP

service to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errat a

• Job Postin gs

• Mic rochip Consultant Pr ogram Member Listing

• Links to other useful web sites related to

Microchip Products

• Confere nces for prod ucts, Dev elopment Systems,

technical information and more

• Listing of seminars and events

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can rece ive the mo st current u pgrade kit s.The Hot Line

Numbe rs are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

PIC16F627A/628A/648A

DS40044B-page 160 Preliminary  2004 Microchip Technology Inc.

READER RESPONSE

It is ou r intention to pro vi de you with the b es t do cu me ntation poss ib le to ensure succ essfu l use of your M ic roc hip pro d-

uct. If y ou w ish to p rov ide y our co mmen ts on org aniza tion, c larity, subje ct ma tter, and ways i n wh ich o ur doc ument atio n

can better serve you, please FAX your comments to the Te chnical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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Questions:

FAX: (______) _________ - _________

DS40044B

PIC16F627A/628A/648A

1. What are the best feat ures of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2004 Microchip Technology Inc. Preliminary DS40044B-page 161
PIC16F627A/628A/648A
INDEX 
A
A/D Special Event Trigger (CCP) .......................................57
Absolute Maximum Ratings ..............................................131
ADDLW Ins truction ...........................................................113
ADDWF Instruction ...........................................................113
ANDLW Ins truction ...........................................................113
ANDWF Instruction ...........................................................113
Architectural Overview..........................................................9
Assembler
MPASM Assembler...................................................125
B
Baud Rate Error..................................................................71
Baud Rate Formula.............................................................71
BCF Instruction. ................................................................114
Block Diagrams
Comparator
I/O Operating Modes ................. .. .. .... .. ..... .... .. .. ..62
Modified Comparato r Output ....... ........... ............64
I/O Por ts
RB0/INT Pin........................................................37
RB1/RX/DT Pin................................ ........... ........37
RB2/TX/CK Pin...................................................38
RB3/CCP1 Pin................ ................... .................38
RB4/PGM Pin ..... ................... ................... ..........39
RB5 Pin...............................................................40
RB6/T1OSO/T1CKI Pin......................................41
RB7/T1OSI Pin ...................................................42
RC Oscillator Mode...... ...............................................96
USART Receive..........................................................79
USART Transmit.........................................................77
BRGH bit.............................................................................71
Brown-Out Detect (BOD) ....................................................98
BSF Instruction .................................................................114
BTFSC Instruction.............................................................114
BTFSS Ins truction...... ................... ............................ ........115
C
C Compilers
MPLAB C17...................... ........................... .............126
MPLAB C18...................... ........................... .............126
MPLAB C30...................... ........................... .............126
CALL In struction ...............................................................115
Capture (CCP Module) ............................ .... .. .... .. ....... .... .. ..56
Block Diag ram................. ................... ................... ......56
CCP Pin Configuration................................................56
CCPR1H:CCPR1L Registers......................................56
Changing Between Capture Prescalers..... .. ........... .. ..56
Prescaler.....................................................................56
Softwa re In terrupt ....... .......... ................... ...................56
Timer1 Mode Selection....... .... ......... .... .... .... ......... .... ..56
Capture/Compare/PWM (CCP)................................. ..........55
Capture Mode. See Capture
CCP1 ..........................................................................55
CCPR1H Register....... ........... .......... ...................55
CCPR1L Registe r....... ...................................... ..55
CCP2 ..........................................................................55
Compare Mode. See Compare
PWM Mode. See PW M
Timer Resources............... ................... ................... ....55
CCP1CON Register
CCP1M3:CCP1M0 Bits. .......... ........... ................... ......55
CCP1X:CCP1Y Bits............... ................... .................. 55
CCP2CON Register
CCP2M3:CCP2 M0 Bits ......... ................... .................. 55
CCP2X:CCP2Y Bits............... ................... .................. 55
Clocking Scheme/Instruction Cycle.................................... 13
CLRF Instru ction....... ................... ................... .......... ........ 115
CLRW Inst ruction.............................................................. 116
CLRWDT Instru ction..... ................... .......... ................... .... 116
Code Examples
Data EE PROM Refresh Ro ut in e ................ .......... ...... 92
Code Protection................... ............................................. 108
COMF Instruction.............................................................. 116
Comparator
Block Diagrams
I/O Operating Modes..... .. .. .. .... .. .. ....... .. .. .... .. .. .. .. 62
Modified  Co mparator Output... ........... ................ 64
Comparator Module................. .. .. .... .. .. ....... .. .. .... .. .. .. .. 61
Configuration.............................................................. 62
Interrupts .................................................................... 65
Operation.................................................................... 63
Reference................................................................... 63
Compare (CCP Module)............................ .. ......... .. .... .. .... .. 56
Block Diag ram................ ................... ................... ...... 56
CCP Pin Confi g u ration ...... .................. ........... ............ 57
CCPR1H:CCPR1L Registers ..................................... 56
Softwar e  In terrupt..... ........................... ................... .... 57
Special Event Trigger ................................................. 57
Timer1 Mode Selection............................................... 57
Configuration Bits............................................................... 93
Crystal Operation....... ......................................................... 95
D
Data EEPRO M Mem ory........ ................... ........... ................ 89
EECON1 Regist e r ............... ..................................... .. 89
EECON2 Regist e r ............... ..................................... .. 89
Operation During Code Protection ............................. 92
Reading...................................................................... 91
Spuri o u s Write Protect i o n....................... .................... 91
Using .......................................................................... 92
Write Verify ................................................................. 91
Writing to ................ ........... .................. ................... .... 91
Data Memory Organization............................................. .... 15
DECF Instruction .............................................................. 116
DECFSZ Instruction .......................................................... 117
Demonstration Boards
PICDEM 1................................................................. 128
PICDEM 17............................................................... 129
PICDEM 18R............................................................ 129
PICDEM 2 Plus......................................................... 128
PICDEM 3................................................................. 128
PICDEM 4................................................................. 128
PICDEM LIN............................................................. 129
PICDEM USB........................................................... 129
PICDEM.net Internet/Ethernet.................................. 128
Development Support....................................................... 125
Development Tool Version Requirements........................ 157
Device Differences............................................................ 155
Device Migrations............................................................. 156
Dual-speed Oscillator Modes.................................... .... .. .... 97

PIC16F627A/628A/648A
DS40044B-page 162 Preliminary  2004 Microchip Technology Inc.
E
EECON1 regi ster ..... .......... ................... ................... ...........90
EECON2 regi ster ..... .......... ................... ................... ...........90
Errata ....................................................................................3
Evalu a tion and Programming  To o l s........ ..........................129
External Crystal Oscillator Circuit........................................95
G
General-Purpose Register File. ...........................................15
GOTO Instruction..............................................................117
I
I/O Ports......................... ................... ........................... .......31
Bi-Directional...............................................................44
Block Diagrams
RB0/INT Pin........................................................37
RB1/RX/DT Pin.. ................... ........... ...................37
RB2/TX/CK Pin...................................................38
RB3/CCP1 Pin ...................... ................... ...........38
RB4/PGM Pin................................. ................... ..39
RB5 Pin ...............................................................40
RB6/T1OSO/T1CKI Pin ......................................41
RB7/T1OSI Pin ...................................................42
PORTA........................................................................31
PORTB........................................................................36
Programming Consi der a tions .................. ...................44
Succes sive Operations........... ................... .................44
TRISA .........................................................................31
TRISB .........................................................................36
ID Locations......................................................................108
INCF Instruction................................................................118
INCFSZ Instruction............................................................118
In-Cir cuit Serial Programming...........................................109
Indirect Addressing, INDF and FSR Registers....................28
Instruction Flow/Pipelining ..................................................13
Instruction Set
ADDLW .....................................................................113
ADDWF.....................................................................113
ANDLW .....................................................................113
ANDWF.....................................................................113
BCF...........................................................................114
BSF...........................................................................114
BTFSC ......................................................................114
BTFSS ......................................................................115
CALL.........................................................................115
CLRF.........................................................................115
CLRW........................................................................116
CLRWDT...................................................................116
COMF .......................................................................116
DECF ........................................................................116
DECFSZ....................................................................117
GOTO........................................................................117
INCF..........................................................................118
INCFSZ.....................................................................118
IORLW.......................................................................119
IORWF ......................................................................119
MOVF........................................................................119
MOVLW.....................................................................119
MOVWF ....................................................................120
NOP..........................................................................120
OPTION ....................................................................120
RETFIE .....................................................................120
RETLW......................................................................121
RETURN...................................................................121
RLF ...........................................................................121
RRF .......................................................................... 122
SLEEP...................................................................... 122
SUBLW..................................................................... 122
SUBWF..................................................................... 123
SWAPF..................................................................... 123
TRIS ......................................................................... 123
XORLW..................................................................... 124
XORWF .................................................................... 124
Instru ction Set Summary .................................................. 111
INT Interrupt...................................................................... 105
INTCON Register ................................................................ 24
Interrupt Sources
Capture Com ple te (CCP)......................... ........... ........ 56
Compar e  Comp le te  (CCP).......................................... 57
TMR2 to PR2 Match (PWM )....................................... 58
Interrupts........................................................................... 104
Interrupts, Enable Bits
CCP1 Enable (CCP1IE Bit) ......................... ....... .. .. .. ..56
Interrupts, Flag Bits
CCP1 Flag (CCP1IF Bit).............. .......... ................... .. 56
IORLW Instruction ............................................................ 119
IORWF Instruction. ................... ........... ................... .......... 119
M
Memory Organization
Data EE PROM Memory................. ................. 89, 91, 92
Migratin g  fr o m oth e r  PICm ic ro Devices............. ............... 156
MOVF Instruction.............................................................. 119
MOVLW Instruction................. ........................... ............... 119
MOVWF Instruction .......................................................... 120
MPLAB ASM30 Assembler, Linker, Librarian................... 126
MPLAB ICD 2 In-Circuit Debugger................................... 127
MPLAB ICE 2000 High-Performance Universal In-Circuit Em-
ulator................................................................................. 127
MPLAB ICE 4000 High-Performance Universal In-Circuit Em-
ulator................................................................................. 127
MPLAB Integrated Development Environment Software.. 125
MPLAB PM3 Device Programmer.................................... 127
MPLINK Object Linker/MPLIB Object Librarian................ 126
N
NOP Instruction ................................................................ 120
O
OPTION Instruction .......................................................... 120
OPTION Register................................................................ 23
Oscillato r Configurat ions................. .................................... 95
Oscillato r Start-up Timer (OST).. ........................................ 98
P
Package Marking Information........................................... 149
Packagi n g  In fo rmation...... ................... ................... .......... 149
PCL and PCLATH ............................................................... 28
Stack........................................................................... 28
PCON Register................................................................... 27
PICkit 1 Fla sh Starter Kit ......................... ................... ...... 129
PICSTART Plus Deve lopment Program mer..................... 128
PIE1 Register...................................................................... 25
Pin Functions
RC6/TX/CK........................................................... 69–86
RC7/RX/DT........................................................... 69–86
PIR1 Register ..................................................................... 26
Port RB Interrupt............................................................... 105
PORTA ............................................................................... 31
PORTB ............................................................................... 36

 2004 Microchip Technology Inc. Preliminary DS40044B-page 163
PIC16F627A/628A/648A
Power Control/Status Register (PCON)..............................99
Power-Down Mode (SLEEP ) . ...........................................107
Power-On Re set (POR)............ ........... ...............................98
Power-up  Timer (PWRT) ........ ........... .................. ...............98
PR2 Register.................................................................52, 58
PRO MATE II Univer sal Device Programmer...................127
Program Memory O rganizat ion...........................................15
PWM (CCP Module) ......................................................... ..58
Block Diag ram................. ................... ................... ......58
Simpl i fied PWM ......................... ................... ......58
CCPR1H:CCPR1L Registers......................................58
Duty Cycle............. .................. ........... ................... ......59
Example Frequencies/Resolutions .............................59
Period..........................................................................58
Set-Up for PWM Operat ion.........................................59
TMR2 to PR2 Match ...................................................58
Q
Q-Clock...............................................................................59
Quick-Turnaround-Production (QTP) Devices......................7
R
RC Oscillator.......................................................................96
RC Oscillator Mode
Block Diag ram................. ................... ................... ......96
Registers
MapsPIC16F627A .................................................16, 17
PIC16F628A .................................................16, 17
Reset...................................................................................97
RETFIE Instruction...................... ................... ...................120
RETLW Instruction............................................................121
RETURN Instru ction .........................................................121
Revision History................................................................155
RLF Instru ction................ ................... .................. .............121
RRF Instruction............... ................... .......... ................... ..122
S
Serial Communication Interface (SCI) Module, See USART
Serialized Quick-Turnaround-Pr oduct ion (SQTP ) Devices...7
SLEEP In struction....................... ............................ ..........122
Softwa re Simulator (MPLAB  SIM )................ ................... ..126
Softwa re Simulator (MPLAB  SIM 3 0 )................ .................126
Special Event Trigger. See Compare
Speci a l Features of the CPU ............... ................... ............93
Special Function Registers.................................................18
Statu s Reg i ster ................. .......... ................... ................... ..22
SUBLW Ins truction..... ............................ ................... ........122
SUBWF Instruction ...........................................................123
SWAPF Ins truction..... ................... ............................ ........123
T
T1CKPS0 bit .......................................................................48
T1CKPS1 bit .......................................................................48
T1OSCEN bit......................................................................48
T1SYNC bit........................... ........................... ...................48
T2CKPS0 bit .......................................................................53
T2CKPS1 bit .......................................................................53
Timer0
Block Diagrams
Timer0/WDT .......................................................46
External Clock Input....................................................45
Interrupt.......................................................................45
Prescaler.....................................................................46
Switching  Prescaler Assign men t..................... ............47
Timer0 Module......................... .. .. .... .. ....... .. .... .. .... .. .. .. 45
Timer1
Asynchronous Counter Mode..................................... 50
Capacitor Selection .................................................... 51
External Clock Input ................................................... 49
External Clock Input Timing........................................ 50
Oscillator..................................................................... 51
Prescaler .............................................................. 49, 51
Resetting Timer1 ........................................................ 51
Resetting Timer1 Registers........................................ 51
Special Event Trigger (CCP ) ...................................... 57
Synchronized Counter Mode................................ ...... 49
Timer Mode....... ................... ................... .................. .. 49
TMR1H....................................................................... 50
TMR1L........................................................................ 50
Timer2
Block Diag ram................ ................... ................... ...... 52
Postscaler................................................................... 52
PR2 register................................................................ 52
Prescaler .............................................................. 52, 59
Timer2 Module......................... .. .. .... .. ....... .. .... .. .... .. .. .. 52
TMR2 output............................................................... 52
TMR2 to PR2 Match Interrupt..................................... 58
Timing Diagrams
Timer0....................................................................... 143
Timer1....................................................................... 143
USART
Asynchronous Receiver ...................................... 80
USART Asynchronous Mas ter Transmission ............. 77
USART Asynchronous Reception .............................. 80
USA RT RX Pin Sa mpli n g ..... ...... ...... .. ..... ...... .. ..... 75 , 7 6
USART Synchronous R eception................................ 86
USART Synchronous Transmission........................... 84
Timing Diagrams and Specifications ................................ 140
TMR0 Interrupt.................................................................. 105
TMR1CS bit........................ ................... ................... .......... 48
TMR1ON bit........................................................................ 48
TMR2ON bit........................................................................ 53
TOUTPS0 bit ...................................................................... 53
TOUTPS1 bit ...................................................................... 53
TOUTPS2 bit ...................................................................... 53
TOUTPS3 bit ...................................................................... 53
TRIS Instr u ction............ ................... ................... .............. 123
TRISA................................................................................. 31
TRISB................................................................................. 36
U
Universal Synchronous Asynchronous Receiver Transmitter
(USART)............................................................................. 69
Asynchronous Receiver
Setting Up Reception.......................................... 82
Asynchronous Receiver Mode
Address Detect................................................... 82
Block Diag ram....................... ................... .......... 82
USART
Asynchronous Mode................................................... 76
Asynchronous Receiver. ... .......................................... 79
Asynchronous Receptio n.. .......................................... 81
Asynchronous Transmission....................................... 77
Asynchronous Transmitter.......................................... 76
Baud Rate Generator (BRG) ............................. ......... 71
Block Diagrams
Transmit.............................................................. 77
USART Receive. ........... ................... .......... ........ 79
BRGH bit .................................................................... 71

PIC16F627A/628A/648A
DS40044B-page 164 Preliminary  2004 Microchip Technology Inc.
Sampling.........................................................72, 73, 74
Synchronous Master Mode.........................................83
Synchronous Master Reception..................................85
Synchronous Master Transmission.............................83
Synchronous Slave Mode.............................. .... .........86
Synchronous Slave Reception...... .. ......... .... .. .... ....... ..87
Synchronous Slave Transmit......................................86
V
Voltage Reference
Configuration...............................................................67
Voltage Reference Module..........................................67
W
Watchdog Timer (WDT)..... ......... .... .. .... ......... .... .... .. .... .....106
WWW, On-Line Support ........................................................3
X
XORLW Ins truction ...........................................................124
XORWF Instr u ction.. .......... ................... ................... .........124

 2004 Microchip Technology Inc. Preliminary DS40044B-page 165

PIC16F627A/628A/648A

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

* JW Devices are UV er asable and can be programm ed to any device configuration . JW Devices meet the electrical requirem ent of

each oscillator type.

Sales and Support

PART NO. -X /XX XXX

PatternPackageTemperature

Range

Device

Device PIC16F6 27A /6 28 A/648A:Standard VDD range 3.0V to 5.5V

PIC16F627A/628A/648ATVDD range 3.0V to 5.5V (Tape

and Reel)

PIC16LF627A/628A/648A:VDD range 2.0V to 5.5V

PIC16LF627A/628A/648AT:VDD range 2.0V to 5.5V (Tape

and Reel)

Temperatu re Rang e I = -40°C to +85°C

E=-40°C to +125°C

Package P = PDIP

SO = SOIC (Gull Wing, 300 mil body)

SS = SSOP (209 m il)

ML = QFN (28 Lead)

Pattern 3-Digit Pattern Code for QTP (blank otherwise).

Examples:

a) PIC16F627A - E/P 301 = Extended Temp.,

PDIP package, 20 MHz, normal VDD limits,

QTP pattern #301.

b) PIC16LF627A - I/SO = Industrial Temp.,

SOIC package, 20 MHz, extended VDD limits.

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local M i croc hip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

New Customer Notification System

DS40044B-page 166 Preliminary  2004 Microchip Technology Inc.

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Fax: 949-263-1338

San Jose

1300 Terra Bella Avenue

Mountain View, CA 94043

Tel : 650 -2 15- 144 4

Fax: 650-961-0286

Toronto

6285 Northam Drive, Suite 108

Mississ aug a, Ontario L4V 1X5, C ana da

Tel : 905 -6 73- 069 9

Fax: 905-673-6509

ASIA/PACIFIC

Australia

Suite 22, 41 Rawson Street

Epping 2121, NSW

Australia

Tel: 61- 2- 986 8-6 73 3

Fax: 61-2-9868-6755

China - Beijing

Unit 706B

Wan Tai Bei Hai Bldg .

No. 6 Chaoyangmen Bei Str.

Beijing, 100027, China

Tel: 86- 10 -85 282 10 0

Fax: 86-10-85282104

China - Chengdu

Rm. 2401-2402, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Chengdu 610016, China

Tel: 86- 28 -86 766 20 0

Fax: 86-28-86766599

China - Fuzhou

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Fuzhou 350001, China

Tel: 86- 59 1-7 503 50 6

Fax: 86-591-7503521

China - Hong Kong SAR

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel : 852 -2 401 -12 00

Fax: 852-2401-3431

China - Sh a ngha i

Room 701, Bldg. B

Far East International Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Tel: 86- 21 -62 75- 57 00

Fax: 86-21-6275-5060

China - Shenzhen

Rm. 1812, 18/F, Building A, United Plaza

No. 5022 Binhe Road, Futian District

Shenzhen 518033, China

Tel: 86- 75 5-8 290 13 80

Fax: 86-755-8295-1393

China - Sh unde

Room 401, Hongjian Building, No. 2

Fengxiangnan Road, Ronggui Town, Shunde

District, Foshan City , Guangdong 528303, China

Tel: 86-757-28395507 Fax: 86-75 7-28395571

China - Qingda o

Rm. B505A, Fullhope Plaza,

No. 12 Hong Kong Central Rd.

Qingdao 266071, China

Tel: 86-532-5027355 Fax: 86-532-5027205

India

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalo re, 560 025, Indi a

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel : 81- 45 -47 1- 616 6 Fax: 81-4 5-471-61 22

Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea 135-882

Tel: 82-2-554-7200 Fax: 82-2-558-5932 or

82-2-558-5934

Singapore

200 Middle Road

#07-02 Prime Centre

Singapore, 188980

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Kaohsiung Branch

30F - 1 No. 8

Min Chuan 2nd Road

Kaohsiung 806, Taiwan

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Taiwan

Taiwan Branch

11F-3, No. 207

Tung Hua Nort h Ro ad

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Austria

Durisolstrasse 2

A-4600 Wels

Austria

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45-4420-9895 Fax: 45-4420-9910

France

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - l er Etage

91300 Massy, France

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy

Via Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands

P. A. De Biesbosch 14

NL-5152 SC Drunen, Netherlands

Tel: 31-416-690399

Fax: 31-416-690340

United Kingdom

505 Eskdale Road

Winnersh T riangle

Wokingham

Berk shire, England RG41 5TU

Tel: 44-118-921-5869

Fax: 44-118-921-5820

01/26/04

WORLDWIDE SALES AND SERVICE