LM555CN - Texas Instruments High-Performance Analog

LM555

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SNAS548C –FEBRUARY 2000–REVISED MARCH 2013

LM555 Timer

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1FEATURES DESCRIPTION

The LM555 is a highly stable device for generating

2• Direct Replacement for SE555/NE555 accurate time delays or oscillation. Additional

• Timing from Microseconds through Hours terminals are provided for triggering or resetting if

• Operates in Both Astable and Monostable desired. In the time delay mode of operation, the time

Modes is precisely controlled by one external resistor and

capacitor. For astable operation as an oscillator, the

• Adjustable Duty Cycle free running frequency and duty cycle are accurately

• Output Can Source or Sink 200 mA controlled with two external resistors and one

• Output and Supply TTL Compatible capacitor. The circuit may be triggered and reset on

falling waveforms, and the output circuit can source

• Temperature Stability Better than 0.005% per or sink up to 200mA or drive TTL circuits.

°C

• Normally On and Normally Off Output

• Available in 8-pin VSSOP Package

APPLICATIONS

• Precision Timing

• Pulse Generation

• Sequential Timing

• Time Delay Generation

• Pulse Width Modulation

• Pulse Position Modulation

• Linear Ramp Generator

Schematic Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LM555

SNAS548C –FEBRUARY 2000–REVISED MARCH 2013

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Connection Diagram

Top View

Figure 1. PDIP, SOIC,

and VSSOP Packages

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)

Supply Voltage +18V

Power Dissipation (3)

LM555CM, LM555CN(4) 1180 mW

LM555CMM 613 mW

Operating Temperature Ranges

LM555C 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Soldering Information

PDIP Package

Soldering (10 Seconds) 260°C

Small Outline Packages

(SOIC and VSSOP)

Vapor Phase (60 Seconds) 215°C

Infrared (15 Seconds) 220°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical

specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within the

Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication

of device performance.

(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(3) For operating at elevated temperatures the device must be derated above 25°C based on a +150°C maximum junction temperature and

a thermal resistance of 106°C/W (PDIP), 170°C/W (S0IC-8), and 204°C/W (VSSOP) junction to ambient.

(4) Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.

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Electrical Characteristics (1) (2)

(TA= 25°C, VCC = +5V to +15V, unless otherwise specified) Limits

Parameter Test Conditions LM555C Units

Min Typ Max

Supply Voltage 4.5 16 V

Supply Current VCC = 5V, RL=∞3 6 mA

VCC = 15V, RL=∞10 15

(Low State) (3)

Timing Error, Monostable

Initial Accuracy 1 %

Drift with Temperature RA= 1k to 100kΩ, 50 ppm/°C

C = 0.1μF, (4)

Accuracy over Temperature 1.5 %

Drift with Supply 0.1 %/V

Timing Error, Astable

Initial Accuracy 2.25 %

Drift with Temperature RA, RB= 1k to 100kΩ, 150 ppm/°C

C = 0.1μF, (4)

Accuracy over Temperature 3.0 %

Drift with Supply 0.30 %/V

Threshold Voltage 0.667 x VCC

Trigger Voltage VCC = 15V 5 V

VCC = 5V 1.67 V

Trigger Current 0.5 0.9 μA

Reset Voltage 0.4 0.5 1 V

Reset Current 0.1 0.4 mA

Threshold Current (5) 0.1 0.25 μA

Control Voltage Level VCC = 15V 9 10 11 V

VCC = 5V 2.6 3.33 4

Pin 7 Leakage Output High 1 100 nA

Pin 7 Sat (6)

Output Low VCC = 15V, I7= 15mA 180 mV

Output Low VCC = 4.5V, I7= 4.5mA 80 200 mV

Output Voltage Drop (Low) VCC = 15V

ISINK = 10mA 0.1 0.25 V

ISINK = 50mA 0.4 0.75 V

ISINK = 100mA 2 2.5 V

ISINK = 200mA 2.5 V

VCC = 5V

ISINK = 8mA V

ISINK = 5mA 0.25 0.35 V

(1) All voltages are measured with respect to the ground pin, unless otherwise specified.

(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical

specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within the

Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication

of device performance.

(3) Supply current when output high typically 1 mA less at VCC = 5V.

(4) Tested at VCC = 5V and VCC = 15V.

(5) This will determine the maximum value of RA+ RBfor 15V operation. The maximum total (RA+ RB) is 20MΩ.

(6) No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.

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Electrical Characteristics (1) (2) (continued)

(TA= 25°C, VCC = +5V to +15V, unless otherwise specified) Limits

Parameter Test Conditions LM555C Units

Min Typ Max

Output Voltage Drop (High) ISOURCE = 200mA, VCC = 15V 12.5 V

ISOURCE = 100mA, VCC = 15V 12.75 13.3 V

VCC = 5V 2.75 3.3 V

Rise Time of Output 100 ns

Fall Time of Output 100 ns

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Typical Performance Characteristics

Minimum Pulse Width Supply Current vs.

Required for Triggering Supply Voltage

Figure 2. Figure 3.

High Output Voltage vs. Low Output Voltage vs.

Output Source Current Output Sink Current

Figure 4. Figure 5.

Low Output Voltage vs. Low Output Voltage vs.

Output Sink Current Output Sink Current

Figure 6. Figure 7.

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Typical Performance Characteristics (continued)

Output Propagation Delay vs. Output Propagation Delay vs.

Voltage Level of Trigger Pulse Voltage Level of Trigger Pulse

Figure 8. Figure 9.

Discharge Transistor (Pin 7) Discharge Transistor (Pin 7)

Voltage Voltage

vs. vs.

Sink Current Sink Current

Figure 10. Figure 11.

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SNAS548C –FEBRUARY 2000–REVISED MARCH 2013

APPLICATIONS INFORMATION

MONOSTABLE OPERATION

In this mode of operation, the timer functions as a one-shot (Figure 12). The external capacitor is initially held

discharged by a transistor inside the timer. Upon application of a negative trigger pulse of less than 1/3 VCC to

pin 2, the flip-flop is set which both releases the short circuit across the capacitor and drives the output high.

Figure 12. Monostable

The voltage across the capacitor then increases exponentially for a period of t = 1.1 RAC, at the end of which

time the voltage equals 2/3 VCC. The comparator then resets the flip-flop which in turn discharges the capacitor

and drives the output to its low state. Figure 13 shows the waveforms generated in this mode of operation. Since

the charge and the threshold level of the comparator are both directly proportional to supply voltage, the timing

interval is independent of supply.

VCC = 5V Top Trace: Input 5V/Div.

TIME = 0.1 ms/DIV. Middle Trace: Output 5V/Div.

RA= 9.1kΩBottom Trace: Capacitor Voltage 2V/Div.

C = 0.01μF

Figure 13. Monostable Waveforms

During the timing cycle when the output is high, the further application of a trigger pulse will not effect the circuit

so long as the trigger input is returned high at least 10μs before the end of the timing interval. However the circuit

can be reset during this time by the application of a negative pulse to the reset terminal (pin 4). The output will

then remain in the low state until a trigger pulse is again applied.

When the reset function is not in use, it is recommended that it be connected to VCC to avoid any possibility of

false triggering.

Figure 14 is a nomograph for easy determination of R, C values for various time delays.

NOTE

In monostable operation, the trigger should be driven high before the end of timing cycle.

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Figure 14. Time Delay

ASTABLE OPERATION

If the circuit is connected as shown in Figure 15 (pins 2 and 6 connected) it will trigger itself and free run as a

multivibrator. The external capacitor charges through RA+ RBand discharges through RB. Thus the duty cycle

may be precisely set by the ratio of these two resistors.

Figure 15. Astable

In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the

triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply

voltage.

Figure 16 shows the waveforms generated in this mode of operation.

VCC = 5V Top Trace: Output 5V/Div.

TIME = 20μs/DIV. Bottom Trace: Capacitor Voltage 1V/Div.

RA= 3.9kΩ

RB= 3kΩ

C = 0.01μF

Figure 16. Astable Waveforms

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SNAS548C –FEBRUARY 2000–REVISED MARCH 2013

The charge time (output high) is given by:

t1= 0.693 (RA+ RB) C (1)

And the discharge time (output low) by:

t2= 0.693 (RB) C (2)

Thus the total period is:

T = t1+ t2= 0.693 (RA+2RB) C (3)

The frequency of oscillation is:

(4)

Figure 17 may be used for quick determination of these RC values.

The duty cycle is:

(5)

Figure 17. Free Running Frequency

FREQUENCY DIVIDER

The monostable circuit of Figure 12 can be used as a frequency divider by adjusting the length of the timing

cycle. Figure 18 shows the waveforms generated in a divide by three circuit.

VCC = 5V Top Trace: Input 4V/Div.

TIME = 20μs/DIV. Middle Trace: Output 2V/Div.

RA= 9.1kΩBottom Trace: Capacitor 2V/Div.

C = 0.01μF

Figure 18. Frequency Divider

PULSE WIDTH MODULATOR

When the timer is connected in the monostable mode and triggered with a continuous pulse train, the output

pulse width can be modulated by a signal applied to pin 5. Figure 19 shows the circuit, and in Figure 20 are

some waveform examples.

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Figure 19. Pulse Width Modulator

VCC = 5V Top Trace: Modulation 1V/Div.

TIME = 0.2 ms/DIV. Bottom Trace: Output Voltage 2V/Div.

RA= 9.1kΩ

C = 0.01μF

Figure 20. Pulse Width Modulator

PULSE POSITION MODULATOR

This application uses the timer connected for astable operation, as in Figure 21, with a modulating signal again

applied to the control voltage terminal. The pulse position varies with the modulating signal, since the threshold

voltage and hence the time delay is varied. Figure 22 shows the waveforms generated for a triangle wave

modulation signal.

Figure 21. Pulse Position Modulator

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SNAS548C –FEBRUARY 2000–REVISED MARCH 2013

VCC = 5V Top Trace: Modulation Input 1V/Div.

TIME = 0.1 ms/DIV. Bottom Trace: Output 2V/Div.

RA= 3.9kΩ

RB= 3kΩ

C = 0.01μF

Figure 22. Pulse Position Modulator

LINEAR RAMP

When the pullup resistor, RA, in the monostable circuit is replaced by a constant current source, a linear ramp is

generated. Figure 23 shows a circuit configuration that will perform this function.

Figure 23.

Figure 24 shows waveforms generated by the linear ramp.

The time interval is given by:

(6)

VBE ≃0.6V (7)

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VCC = 5V Top Trace: Input 3V/Div.

TIME = 20μs/DIV. Middle Trace: Output 5V/Div.

R1= 47kΩBottom Trace: Capacitor Voltage 1V/Div.

R2= 100kΩ

RE= 2.7 kΩ

C = 0.01 μF

Figure 24. Linear Ramp

50% DUTY CYCLE OSCILLATOR

For a 50% duty cycle, the resistors RAand RBmay be connected as in Figure 25. The time period for the output

high is the same as previous, t1= 0.693 RAC. For the output low it is t2=

(8)

Thus the frequency of oscillation is:

(9)

Figure 25. 50% Duty Cycle Oscillator

Note that this circuit will not oscillate if RBis greater than 1/2 RAbecause the junction of RAand RBcannot bring

pin 2 down to 1/3 VCC and trigger the lower comparator.

ADDITIONAL INFORMATION

Adequate power supply bypassing is necessary to protect associated circuitry. Minimum recommended is 0.1μF

in parallel with 1μF electrolytic.

Lower comparator storage time can be as long as 10μs when pin 2 is driven fully to ground for triggering. This

limits the monostable pulse width to 10μs minimum.

Delay time reset to output is 0.47μs typical. Minimum reset pulse width must be 0.3μs, typical.

Pin 7 current switches within 30ns of the output (pin 3) voltage.

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SNAS548C –FEBRUARY 2000–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 12

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM555CM NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM

555CM

LM555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS

& no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LM

555CM

LM555CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI 0 to 70 Z55

LM555CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 Z55

LM555CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 Z55

LM555CMX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LM

555CM

LM555CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS

& no Sb/Br) SN | CU SN Level-1-260C-UNLIM 0 to 70 LM

555CM

LM555CN NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM

555CN

LM555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS

& no Sb/Br) CU SN Level-1-NA-UNLIM 0 to 70 LM

555CN

MC1455P1 NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM

555CN

NE555V NRND PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM

555CN

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

PACKAGE OPTION ADDENDUM

www.ti.com 1-Nov-2013

Addendum-Page 2

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM555CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM555CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM555CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LM555CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

LM555CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Mar-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM555CMM VSSOP DGK 8 1000 210.0 185.0 35.0

LM555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LM555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

LM555CMX SOIC D 8 2500 367.0 367.0 35.0

LM555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Mar-2013

Pack Materials-Page 2

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